SoC Embedded NS Embedded Systems 3 Jan 2014

8/10/2019 SoC Embedded NS Embedded Systems 3 Jan 2014

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Embedded (HW) Syste

Performance Evaluatio

CommunicationVineet [email protected]


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Outline Introduction

System-on-a-Chip (SoC) Who enables Chip design

Electronic Design automation (EDA) High level, Logic, Layout synthesis

FPGA based synthesis

ES/SoC Communication Modeling Performance Evaluation techniques


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Generic SoC Implementa

Computat PEs

Communi

Bus bas NoC arc

?


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Generic SoC No. of PEs

PE are verified, validated CPU, DSP , IP , ASIC Set-top-box, MPEG-2 decoder

PE are heterogeneous Optimized HW/SW

Separable computation & commuDiverse communication

Proce

L


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System Modeling Models of Computation

Continuous Time Models SIMULINK, VHDL-AMS

Discrete Timed Models

HDLs etc. Synchronous Models Untimed Models

Data Flow Process Networks Synchronous Data Flow, Kahn Proc


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Chip Design: Who Ena Design Technology

Integrated circuit (Chip) design

Applications technologies Wireless/Telecommunication

Computing

Internet Consumer/medical electronics

Enabling technologies

FabricationS f

De

Fabr

k

I


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Design Technology Systems characteristics Billion/Trillion transistors

Heterogeneous, portable, low power, low Desired

Circa 2004, A single hand-held portable syst

Computing, GPS enabled, multimedia/voice/wireless internet

Circa 2020, Similar system which is hands frwearable and controlled by thoughts

VLSI DesignS h i b d h d l


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VLSI Design

Methodology Supported by CAD

Human expertisecentric

Increasing mismatch of

Synthesis models andimplemented circuit

First time correctdesigns are rare/nearly

Architectu

Components

System s

Id

Chip Lay


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Electronic Design Automation

Architecture Synthesis

Components/gate synthesis

System specification

Chip Layout synthesis

SynthesisCAD tools


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Electronic Design Autom What ?

Automating the design process

Design automation using E-CA

How ?

Design description Abstraction, models

Verification/simulation

Transformation between various

Back-annotatio


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E-CAD Why ?

CAD is indispensable

Design size too large

Systems too complex

Huge design efforts

Problem definition dynamically c


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Performance Evalua

Models for System-onCommunication


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Outline

Communication Architectures (C

Performance estimation Statistical estimation Analytical estimation

Proposal for performance evaluamodels

HCFG based approach


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Communication archite CA is fabric

data & con It consist o

1.Logic com

2.Global bu3.Bus inter


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Bus based Single sha

Hierarchicconnected


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Networks on Chip Packe

via chswitch


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NoC TopologiesSPIN

Scalable PrIntegrated N

CLICH. Chip Level

communica

Heterogene


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Commercial Bus Archite IBM Core-Connect

ARM AMBA Palmchip

CoreFrame


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Performance Estimatio

Statistical analysis

- CAG model

- Queueing theory

- Stochastic framework Trace driven simulation

- System level tools (PTO


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Efficiency of Modeling Appr

Models Cl

FSM, Timed-Petri-nets, Markov chains,

Kahn process networks ,Transaction Levelmodels, OSM

Si

mo

Synchronization graph, CAG, Queuingmodel

Anmo


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Significance of interface synth

Abstract Communication


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Alternate Comm. Architecture -

C1,C2 & Mmapped to

C3,C4 & Mmapped to


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Alternate mapping ( Arch-B) - C

C1,C3 & Mmapped to

C2,C4 & Mmapped to


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Queueing model

Kim

CAD


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Markov Model


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Hierarchical bus mode Indivi

Ma Bus s

Pas

Pas

Bridg

Pas


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Hierarchical bus mode

Pi1S1

S

2

SG Introduction

HCFG: An Overview

HCFG h f l ti GSMP d l f SSB hit t


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HCFG approach for evaluating GSMP model of SSB architecture

Results

Conclusions

Evaluating Generalized Semi Markov Process

Model of SoC Bus Architectures using HCFG

Ulhas Deshmukh1 Vineet Sahula2

1Govt. Polytechnic College, Dhule, India

2Department of ECE

Malaviya National Institute of Technology, Jaipur, India

TENCON 2009, Singapore 23-26 November 2009

Ulhas Deshmukh, Vineet Sahula GSMP model evaluation using HCFG

IntroductionHCFG: An Overview

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Results

Conclusions

Outline

1 Introduction

Motivation

Previous work and Proposed work

2 HCFG: An Overview

3 HCFG approach for evaluating GSMP model of SSB architecture

SSB architectureGSMP Model formulation

Model evaluation using HCFG approach

HBB architectureGSMP model formulation


4 Results

5 Conclusions



HCFG approach for evaluating GSMP model of SSB architectureMotivation
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Results

Conclusions


Outline

1 Introduction

Motivation


2 HCFG: An Overview




HBB architectureGSMP model formulationModel evaluation using HCFG approach

4 Results

5 Conclusions



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Results

Conclusions


System level SoC architecture

SW IP1

On Chip Communication

SW IP2

HW IP1 HW IP2

HW Adaption

HW Adaption

HW AdaptionHW Adaption

CPU

CPU

SW Adaption

SW Adaption

SW

SW SoC performs computation

and communication of

system functionalitySystem computation-

Mapped to PEs/IPs

Pre-verified & optimized

Communication

architecture facilitates

communication among IPs



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Results

Conclusions


Issue

Modern-day systems demand for higher performance and

more functions

Designer has to use a number of concurrent and

heterogeneous IPs

Communication among these IPs becomes intricate

Quick performance evaluation of communication

architecture is essential




P i k d P d k
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Results

Conclusions


Outline

1 Introduction

Motivation


2 HCFG: An Overview





4 Results

5 Conclusions




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pp g

Results

Conclusions


Related work & proposed approach

Classification Authors Approach

Analytical P.Knudsen et al.[1] Delay estimation model

S.Dey et al. [2] Synchronization graphT.Mudge et al. [3] SMP model (multi-bus arch.)A.Ramani et al. [4] SMP model (crossbar arch.)Proposed work GSMP model evaluation

using HCFG

Simulation J.Rowson et al. [5] Simulator (Cheetah)X.Zhu et al. [6] Operating State Machine

Hybrid K.Lahiri et al.[7] Simulation + CAGS.Kim et al.[8] Queueing analysis + simulation



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pp g

Results

Conclusions

Hierarchical Concurrent Flow Graph (HCFG)

HCFG approach [9] [10]

An efficient analysis technique

Captures concurrency, hierarchyHandles stochastic variation in task execution times

Quickly compute average values & distribution

Has been used for evaluation and improvement of process

completion time of VLSI design processes [9] [10]

[9] V.Sahula,C.P.Ravikumar,D. Nagchoudhuri,ASP-DAC 2002

[10] V.Sahula and C. P. Ravikumar, VLSI Design,2001

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Results

Conclusions

Communication concurrency in HCFG

T T T

TTT

T T

Ttile, SSource, Ddestination

ST

D

P2 P3 TP1

T2P 3

TP

P1

Source PE

Dest. PE

Path 3Path 1 Path 2

OR concurrency

Multiple communications path can be active

E[TC] =E[Min{TP1, TP2,TP3}]



HCFG approach for evaluating GSMP model of SSB architectureSSB architecture

HBB architecture
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Results

Conclusions

HBB architecture

Outline

1 Introduction

Motivation


2 HCFG: An Overview





4 Results

5 Conclusions

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Results

SSB architecture

HBB architecture


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Results

Conclusions

Model formulation

Arbiter

BUS

MEM

PE PEPE1 2 N

I/FI/F

I/F I/FI/F Computing action

ThePE1 is computing

No request is generated

Modeled ascomputing state

(labeled asstate 0)

Mean sojourn time is0 =T




Results

SSB architecture

HBB architecture
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Results

Conclusions

Model formulation cont.

Arbiter

BUS

MEM

PE PE PE1 N2

I/FI/F

I/F I/F I/F

Accessing action

PE1 generates a request

Bus and memory are idle((1 BUSY)2)

Request wins arbitration (WIN)

PE1 accesses the memory

Modeled asaccessing state(labeled asstate 1)

Mean sojourn time is1 =C




Results

SSB architecture

HBB architecture
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Results

Conclusions


MEM

BUS

CP

P FWPE1

PEk

PCOMP, CCOMM

FWFull Waiting

PEPEPE1 2 N

I/F

I/FI/FI/F

Full waiting action

PE1 &PEkgenerate request

Bus and memory are idle

PE1 does not win arbitration

PEkgets access to memory

PE1 has to wait for full accessing

time ofPEk

Modeled asfull waiting state

(labeled asstate 2)

Mean sojourn time isC




Results

SSB architecture

HBB architecture
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Results

Conclusions


MEM

BUS

PCOMP, CCOMM

RWResidual Waiting

PEk

P PE1

C

RW

PE PE PE N1 2

I/F

I/F I/F I/F

Residual waiting state

PEk is accessing memory

i.e. memory is busy

PE1 generates a requestPE1 force to wait for

residual accessing time of

PEk

Modeled asresidual

waiting state(labeled as

state 3)

Mean sojourn time is

(C2 C)/(2(C 1)




Results

SSB architecture

HBB architecture
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Results

Conclusions

Model input parameters forith PE

Parameters Description

N number of processing elements

Ti mean computing time

Ci mean communication time

C2i second moment of communication time

Terms used in model formulation

BUSY probability that memory or bus busyWIN probability of wining arbitration

k mean sojourn time ofkth state




Results

SSB architecture

HBB architecture
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Conclusions

GSMP model of a PE in SSB

3

0

2 1

3

1

1

0

1

2

11

States of a PE

State 0-computing stateState 1-accessing state

State 2-full waiting state

State 3-residual waiting

state




Results

SSB architecture

HBB architecture
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Conclusions

HCFG based evaluation approach

Transformation of GSMP model to HCFG

Add extra nodeSfor initial task

Draw directed edge(S, x),xis state of GSMP

xshould have zero in-degree (minimum),pSx=1

Mapjs of GSMP model to the Tjs of HCFG node,j=0,1, 2,3,Ts=0

Mappij

of GSMP model, to the weightpij

of an edge (i,j) ofHCFG

Consider one state at a time as a final (F) state




Results

SSB architecture

HBB architecture
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Conclusions

HCFG based evaluation approach cont.

HCFG of a PE in SSB for N=2

2p Z21

1p Z10

1p Z03

1p Zs3

p = 0.3921

p = 0.6122

p = 0.1802

p = 1.0s3

p = 0.6132

p = 0.3931

10p = 1.0 p = 0.43

03

p = 0.3901

T = 0S

T = 22

T = 21

T = 10

T = 13

232

p Z

2p Z02

2p Z01

2p Z31

2p Z22

3S 2F1

0




Results

SSB architecture

HBB architecture
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Conclusions

Computation of steady state probabilities

Describe HCFG in DFLOW tool

Execute DFLOW description to find steady state probability

of being in state F

Repeat for all other states and for varing number of PEs

Performance parameters are computed as follows:

BW = N P1

PU = P0+ P1

L = N(P2+ P3)

W = 22 + 33

1




Results

SSB architecture

HBB architecture
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Conclusions

Outline

1 Introduction

Motivation


2 HCFG: An Overview

3 HCFG approach for evaluating GSMP model of SSB architectureSSB architecture

GSMP Model formulation


HBB architecture

GSMP model formulationModel evaluation using HCFG approach

4 Results

5 Conclusions




Results

C l i

SSB architecture

HBB architecture
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Conclusions

HBB architecture

BusI/f

BusI/f

Bridge

Arbiter ArbiterMEM1 MEM 2

BUS1 BUS2

I/F I/F

I/F

PE2

I/F

PEN

I/F

PE1

I/F

PE2

I/F

PEN

I/F

PE1

I/F I/F

Concurrent communication onBUS1&BUS2

Each PE can accessMEM1&MEM2

ConsiderPE1 mapped toBUS1

MEM1-local memory,MEM2-global memory




Results

Concl sions

SSB architecture

HBB architecture
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Conclusions

GSMP Model of a PE in HBB

2 1

46 5

0

1

4

0

0

2

1

4

4

4

11

6

4

5

13

3

States of a PE

State 0 computing state

State 1 through state 3localMEM1

State 4 through state 6

globalMEM2




Results

Conclusions

SSB architecture

HBB architecture
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Conclusions

Model input parameters

N = number of Processing Elements (PEs)

T= Mean value of of think time

X

= Probability of local requestXg= Probability of global request

C = Mean value of of local connection time

Cg= Mean value of of global connection time

C2l/C2g= Second moment of local/global communicationtime




Results

Conclusions

SSB architecture

HBB architecture
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Conclusions

Model evaluation- HCFG approach

HCFG of a PE in HBB forX=0.1.

21p = 0.27

10p = 1.0

22p = 0.73

31p = 0.27

65p = 0.82

40p = 1.0

55p = 0.82

54

p = 0.1864

p = 0.18

2p Z01

06

p = 0.19

04p = 0.16

32p = 0.73

05p = 0.57

03p = 0.01

01p = 0.027

S0p = 1.0

02p = 0.057

2p Z312

p Z22 2p Z

04

2p Z02

1p Z

10

1p Z40

2p Z65

2p Z64

2p Z05

2p Z04

2p Z

54

1p Z06

1p Z03

2p Z32

2p Z55

1p Zs0

T = 10

T = 22

T = 13

T = 24

T = 25

T = 0S

T = 21

T = 16

2 1

0

456

3

S


Introduction

HCFG: An Overview


Results

Conclusions

SSB architecture

HBB architecture
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Conclusions

Performance metrics of HBB architecture

Performance metrics

BW = N P1BWg = N P4

L = N(P2+ P3)

Lg = N(P5+ P6)

W = 2(2+31)/1+33Wg = 5(5+64)/4+66

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Introduction

HCFG: An Overview


Results

Conclusions

SSB architecture

HBB architecture


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SystemC simulation setup for HBB architecture

sc_indata_BR12;

void bus2_action()

SC_MODULE(bus2)

{

sc_indata_PE1;

//PE11.cc

while(true)

sc_indata_BR12;

void bus2_action()

SC_MODULE(bus2)

{

sc_indata_PE1;

//bus1.cc

while(true)

{

}

//arbiter1.cc

SC_MODULE(arbiter2)

{ sc_inbus2_status;

sc_inreq_PE1;

//some ports

void arbiter2_action() {

while(true){

//rest of the code not shown}

}

SC_CTOR(arbiter2)

SC_THREAD(arbiter2_action);

};

{

}

//arbiter2.cc

SC_MODULE(arbiter2)

{ sc_inbus2_status;

sc_inreq_PE1;

//some ports

void arbiter2_action() {

while(true){

//rest of the code not shown

}}

SC_CTOR(arbiter2)

SC_THREAD(arbiter2_action);

};

MEM 1 Arbiter1

PE 1 PE 2

MEM 1 Arbiter1

PE 1 PE 2

Bus

I/f

Bus

I/f

Bridge

//some other ports

if(PE_grant.read()==1)

{

//rest of the code not shown; }

SC_CTOR(bus2)

}

};

{

{

status_bus2.write(true);

}

}

{

//some other ports

if(PE_grant.read()==1)

{

//rest of the code not shown; }

SC_CTOR(bus2)

}

};

{

{

status_bus2.write(true);

}

}

{

//BR1.cc

SC_MODULE(BR1){

//portssc_out req_BR1;

sc_outdata_BR1;

sc_in_clk clock;

//other ports

void BR1_action()

while(true)

{ if(BR1_grant.read()==1)

//rest of the code;}

SC_CTOR(BR1)

{

SC_THREAD(BR1_action);

sensitive


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Results- SSB architecture

Model Input Parameters -C=2 Cycles,T=2 Cycles,Cv=0.

1 2 3 4 5 6 7 80

0.2

0.4

0.6

0.8

1

Number of PEs

Bandwidth

Simulation Approach

AFOME Approach

HCFG Approach

1 2 3 4 5 6 7 80

0.2

0.4

0.6

0.8

1

Number of PEs (N)

Pro

cessorUtilization

(PU)

Simulation ApproachAFOME Approach

HCFG Approach

PU for T=2,r=0.1


Introduction

HCFG: An Overview


Results

Conclusions
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Results- HBB architecture

Model Input Parameters - N=2,T=2 Cycles,C=Cg=2 Cycles,

Cv=0.

0.2 0.4 0.6 0.80

0.2

0.4

0.6

0.8

1

Probability of local request

Localbandwidth

Simulation Approach

AFOME ApproachHCFG Approach

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0


L

ocalwaitingtime

Simulation Approach

AFOME Approach


Introduction

HCFG: An Overview


Results

Conclusions
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Results- HBB architecture

Model Input Parameters - N=2,T=2 Cycles,C=Cg=2 Cycles,

Cv=0.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90

0.1

0.2

0.3

0.4


G

lobalbandwidth

Simulation Approach

AFOME Approach

HCFG Approach

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90

0.5

1.0

1.5

2.0


G

loalqueuelength

Simulation Appro.AFOME Approach

HCFG Approach


Introduction

HCFG: An Overview


Results

Conclusions
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Conclusions

Proposed analytical approach is time efficient, accurateBesides, it gives stochastic properties quickly as that of

simulation


Introduction

HCFG: An Overview


Results

Conclusions
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Bibliography

1 P. Knudsen and J. Madsen, Integrating communication protocol selection with partitioning inhardware/software codesign in Proc. Int.Symp. Syst. Level Synthesis,1999,111-116.

2 S. Dey and S. Bommu, Performance analysis of a system of communicating processes, in ICCAD, 1997,590-597.

3 T.N.Mudge and H.B.A.Sadoun, A Semi Markov Model for Performance of Multiple-Bus Systems, IEEETrans. On Computers, Vol C-34, No 10, Oct 1985.

4 A.K.Ramani, P.K.Chande and P.C.Sharma, A general model for performance investigations of prioritybased multiprocessor system, IEEE Trans. on Computers, 1992, 747-754

5 J. A. Rowson and A. Sangiovanni-Vincentelli, Interface based design, Proc. Design Automation Conf.,1997, 178-183.

6 X. Zhu, W. Qin, and S. Malik, Modeling operation and microarchitecture concurrency for communicationarchitectures with application to retargetable simulation, IEEE Trans. VLSI Syst., 14(7):707-716, July 2006.

7 K.Lahiri, A. Raghunathan and S. Dey, System-level performance analysis for designing on-chipcommunication architecture, IEEE Tran. CAD, 20(6):768-783, June 2001.

8 S. Kim, C.Im and S. Ha, Schedule-Aware Performance Estimation of Communication Architecture forEfficient Design Space Exploration, IEEE Trans. VLSI System Vol 13, No 5, Pages 539-552, may 2005.

9 V.Sahula, C. P. Ravikumar and D. Nagchoudhuri. Improvement of ASIC Design Processes. ASP-DAC,2002, pages 105-112.

10 V.Sahula and C. P. Ravikumar, The hierarchical concurrent flow graph approach for modeling and analysisof design processes, in Int. Conf. VLSI Design,2001,91-96.

11 U.Deshmukh and V. Sahula, Analytical performance estimation from GSMP model for hierarchical busbridge based SoC communication architecture, in Proceedings of 20th IEEE International Conference onMicroelectronics (ICM), Dec. 2008.


Introduction

HCFG: An Overview


Results

Conclusions
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SoC Embedded NS Embedded Systems 3 Jan 2014

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