Sistemas Operativos: Input/Output Intro and …web.fe.up.pt/~pfs/aulas/so2013/at/8io.pdfI bus mode:...
Transcript of Sistemas Operativos: Input/Output Intro and …web.fe.up.pt/~pfs/aulas/so2013/at/8io.pdfI bus mode:...
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Sistemas Operativos: Input/OutputIntro and HW/SW Interface
Pedro F. Souto ([email protected])
April 14, 2012
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Agenda
Introduction
I/O Controllers and I/O Buses
Modes of Data Transfer
Additional Reading
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Agenda
Introduction
I/O Controllers and I/O Buses
Modes of Data Transfer
Additional Reading
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Input/Output Devices
I Wide variety of I/O devicesDevice Type Data rateKeyboard Human-interface 10 byte/sMouse Human-interface 100 byte/sModem Communication 56 kbit/sISDN line Communication 128 kbit/sLaser printer Human-interface 100 kbyte/sEthernet Communication 10 Mbit/sUSB Bus 12 Mbit/s40× CD-ROM Storage 6 Mbyte/sFast Ethernet Communication 100 Mbit/sEIDE (ATA-2) Storage 16.7 Mbyte/sXGA Monitor Human-interface 60 Mbyte/sGigabit Ethernet Communication 1 Gbit/sPCI bus Bus 528 Mbyte/sHyperTransport Bus Bus 25.6 Gbyte/s
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Agenda
Introduction
I/O Controllers and I/O Buses
Modes of Data Transfer
Additional Reading
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I/O Controllers (1/3)
I An I/O controller is an electronic component thatI Controls the operation of the I/O deviceI Some examples:
I Network cardI Video cardI Hard disk controllerI UART (serial port controller)
I The OS interfaces with the I/O controllerI It is also known as adapter
but not with the device itselfI Nevertheless, the developer of a device driver needs to
have a fairly detailed knowledge of the device’s operation
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I/O Controllers (2/3)Monitor
KeyboardFloppy
disk drive
Hard disk drive
Hard disk
controller
Floppy disk
controller
Keyboard controller
Video controller
MemoryCPU
Bus
I I/O controllers have 4 sets of registersControl registers for configuring and controlling the
device’s operationStatus registers for monitoring the state of the device and
of the operations it performsInput data registers (or buffers) for data transfer from the
deviceOutput data registers (or buffers) for data transfer to the
device
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I/O Controllers (3/3)I Access to these registers may be via:
Memory-mapped I/OI Allows to use any memory access instruction for I/OI There are some issues with caching and VM (to discuss
later)I/O instructions such as in/out
I The system uses different address spaces for memoryand for I/O
I Protection is simplified by making these instructionsprivileged
Two address One address space Two address spaces
Memory
I/O ports
0xFFFF…
0
(a) (b) (c)
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I/O Buses (1/3)
I Except for slow processors, I/O controllers and memoryuse different buses
CPU Memory I/O
BusAll addresses (memory
and I/O) go here
CPU Memory I/O
CPU reads and writes of memory go over this high-bandwidth bus
This memory port is to allow I/O devices access to memory
(a) (b)
I Even, when the controllers are memory-mappedI In this case memory addresses have to be passed to the I/O
busI The bus on which a controller is, usually is not transparent
to the device driver developer
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I/O Buses (2/3)
I On a PC, there are typically 3 types of buses:
ISA bridge
Modem
Mouse
PCI bridgeCPU
Main memory
SCSI USB
Local bus
Sound card
Printer Available ISA slot
ISA bus
IDE disk
Available PCI slot
Key- board
Mon- itor
Graphics adaptor
Level 2 cache
Cache bus Memory bus
PCI bus
I It is up the PCI bridge (or better the north-bridge) to filterthe addresses
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I/O Buses (3/3)
source: http://commons.wikimedia.org/wiki/File:X58_Block_Diagram.png
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Agenda
Introduction
I/O Controllers and I/O Buses
Modes of Data Transfer
Additional Reading
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Programmed I/OI The CPU transfers the data between memory and the
controller’s data registers
String to be printedUser
space
Kernel space
ABCD EFGH
Printed page
(a)
ABCD EFGH
ABCD EFGH
Printed page
(b)
ANext
(c)
ABNext
copy_from_user(buffer, p, count); /* copy data to kernel */for( i = 0; i < count; i++ ) { /* for all characters */
while(*printer_status_reg != READY); /* wait for printer */
*printer_data_reg = p[i]; /* output next character */}
I The CPU must poll the controller to find out if the device isready for the next operation
I Often, it must also check whether the operation succeededI.e. we have busy waiting
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Interrupt-Driven I/0 (1/4)
CPUInterrupt controller
Disk controller
Disk drive
Current instruction
Next instruction
1. Interrupt
3. Return
2. Dispatch to handler
Interrupt handler
(b)(a)
1
3
4 2
I Relies on the processor’s interrupt mechanismI When the device
I completes a commandI detects an event (e.g. reception of a packet)
it generates an HW interrupt
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Interrupt-Driven I/0 (2/4)
CPU
Interrupt controller
3. CPU acks interrupt
2. Controller issues interrupt
1. Device is finished
Disk
Keyboard
Printer
Clock
Bus
12
6
9 348
57
111210
I So that interrupt processing is more efficient, manyprocessors use vectored interrupts
1. The CPU and the interrupt controller execute a HWhandshake protocol
I So that the CPU learns which device generated the interrupt
2. The CPU then invokes the appropriate interrupt handler
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Interrupt-Driven I/0 (3/4)I Before executing the interrupt handler, the CPU
automatically stores some of its state in the stackQuestion which stack should be used? The user’s process
stack?I The SP contents may not be validI It may point to the “end” of a page, leading to a page
faultI Another issue concerns the interrupt precision
I In pipelined or superscalar architectures, the CPU does notexecute one instruction at a time, but several
This is a HW feature with major implications on the OS
Fetch unit
Fetch unit
Fetch unit
Decode unit
Decode unit
Execute unit
Execute unit
Execute unit
Execute unit
Decode unit
Holding buffer
(a) (b)
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Interrupt-Driven I/0 (4/4)
I The processor programs the I/O controller to execute theoperation
copy_from_user(buffer, p, count); /* copy data to kernel */while(*printer_status_reg != READY); /* wait for printer */
*printer_data_reg = p[0]; /* output first character */scheduler(); /* wait for I/O */
I The I/O controller generates an interrupt when theoperation is done
I The interrupt handler does what must be done on thatevent
if( count == 0 ) {unblock_process();
} else {
*printer_data_register = p[i];count--;i++;
}acknowledge_interrupt();return_from_interrupt();
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I/O with DMA (1/5)Problem Interrupt-driven I/O avoids busy waiting but the
processor still has to transfer the dataI For large data blocks and high-speed devices such as
disk accesses, interrupt-driven I/O would lead to a veryhigh CPU utilization
Solution Use DMA, i.e. a dedicated processor that takes overof data transfer for the processor
I The processor has to:I configure the DMA controller for carrying out the data
transferI configure the I/O controller to carry out the operation
I The I/O controller signals the DMA controller when it isready to transfer data
I The DMA controller requests bus access, and does thetransfer when it is granted the bus
I The DMA controller interrupts the processor once thedata block has been transferred
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I/O with DMA (2/5)
CPU
DMA controller
Disk controller
Main memory
Buffer
1. CPU programs the DMA controller
Interrupt when done
2. DMA requests transfer to memory 3. Data transferred
Bus
4. Ack
Address
Count
Control
Drive
I The CPU has to program the DMA controller with:I The memory address with the data bufferI The number of bytes/words to transferI Other parameters such:
I direction of data transfer (read/write)I bus mode: cycle stealing vs. burst modeI transfer mode: flyby vs. fetch-and-deposit
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I/O with DMA (3/5)Fetch and deposit DMA can be also used for
memory-to-memory transfers
source: National Instruments
Flyby DMA
source: National Instruments
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I/O with DMA (4/5)
I The code for initiating the DMA operation (to print a buffer),might be:copy_from_user(buffer, p, count); /* copy data to kernel*/set_up_DMA_io(); /* set up for DMA operation */scheduler(); /* wait for I/O */
I The DMA controller generates an interrupt when the datatransfer is done to avoid busy-waiting
I The interrupt handler for the DMA controller might besomething like:
acknowledge_interrupt();
unblock_process();
return_from_interrupt();
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I/O with DMA (5/5)
I A DMA controller capabilities vary widely:I May handle more than one data transfer simultaneouslyI May handle more than one data buffer per DMA request
I A system may have more than one DMA controllerI Usually, each I/O bus has its own DMA controller, which is
integrated into the bus controller chip
IssuesI Processor data cache coherencyI Physical memory addresses vs virtual memory
addresses (later)
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Agenda
Introduction
I/O Controllers and I/O Buses
Modes of Data Transfer
Additional Reading
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Additional Reading
Sistemas Operativos
I Sections 11.1: Objectivos do Subsistema de E/SI Subsection 11.5.1: Communicação entre o Gestor e
o Periférico
Modern Operating Systems, 2nd. Ed.
I Section 5.1: Principles of I/O Hardware
Operating Systems Concepts, 7th. Ed.
I Section 13.1: OverviewI Section 13.2: Hardware