Signal Integrity and Radiated Emissions of Printed Circuit Board ... · Signal Integrity and...

Signal Integrity and Radiated

Emissions of Printed Circuit

Board Microstrips in Digital

Switching

Wei-Juet (Bert) Wong

B.Eng. M.Eng.

This thesis is presented as part of the requirements for

the award of the Degree of Doctor of Philosophy

of The University of Western Australia

School of Electrical, Electronic and Computer Engineering

September 2013

To my wife Doris (伍彩萍)

and our son Davin (黃樂謙)

and our unborn daughter Dasia (黃樂賢)

i

Acknowledgements

In loving memory of my father and grandparents.

Undertaking the PhD research was never an easy task and throughout the years I have

been very blessed to have many people who have stood by my side at various stages of

my PhD degree. Some of these people I would like to specifically address here. For

those that I did not mention, your support has been invaluable. Thank you!

In particular, to my loving wife and son who have been very patient with me all the way

through my journey. Sincere apologies for the times when my focus have been diverted

elsewhere with this research. I am glad that I can now fully pursue my role as a husband

and as a father. Also, to my family, mum and brother, who also have been very patient

with my endeavours. A very special thank you all!

To all my relatives here in Australia and overseas for your encouragement. Thank you!

My supervisor Professor Antonio Cantoni for his encouragement, enthusiasm and expert

guidance throughout the course of this research. He has a wealth of knowledge to draw

from not just in the engineering field that I have had the privilege to learn from. Thank

you for your understanding and support during the course of my research.

My co-supervisor Dr Ba-Tuong Vo for many helpful discussions on various matters

with regards to my PhD and help with the proofing of this thesis.

Dr Franz Schlagenhaufer for allowing me to use the EMC facility at Curtin University

to conduct my measurements.

My close friends, Dr Tarith Devadason and Dr Joachim Trinkle for your encouragement

and help with proof reading this thesis.

I would also like to gratefully acknowledge the financial assistance from the

Commonwealth Scientific and Industrial Research Organisation (CSIRO) under the

Postgraduate Studentship, by the Information, Communication & Technology Centre,

CSIRO, and the Australian Postgraduate Award scheme.

Above all, I would like to thank the Lord Jesus Christ for giving me the opportunity to

undertake the PhD and to provide me with a job offer prior to the completion of my

PhD. “Now to him who is able to do immeasurably more than all we ask or imagine,

according to his power that is at work within us,” (Ephesians 3:20). Glory be to God!

ii

Abstract

This thesis proposes methods for the modelling and analysis of signal integrity (SI) and

radiated emission (RE) of capacitively loaded printed circuit board interconnections.

Two techniques are considered for achieving a high level of SI, namely source series

damping and destination parallel damping. Low order models are developed for the two

methods which enable a comparison of their SI performance and the identification of

the key parameters that affect SI. Under certain conditions the two methods are shown

to have approximately the same SI performance. However, the two techniques can

exhibit different characteristics in other respects, such as power dissipation, peak

current and RE. One particular characteristic that is studied in the thesis is the

performance with respect to far-field REs. A key objective of this thesis is to develop a

quantitative analysis and a qualitative understanding of the interplay between

electromagnetic compatibility/interference and SI for the two damping techniques.

iii

Commonly Used Acronyms

Note that the letter ‘s’ may be attached to the acronym listed to represent the plural

form.

DPD Destination Parallel Damping

EMC ElectroMagnetic Compatibility

EMI ElectroMagnetic Interference

MoM Method of Moments

PCB Printed Circuit Board

PEC Perfect Electric Conductor

RE Radiated Emission

SDD Source-Destination Damping

SI Signal Integrity

SR Step Response

SDD Source-Destination Damping

SSD Source Series Damping

TEM Transverse ElectroMagnetic

TF Transfer Function

TL Transmission Line

iv

Contents

Acknowledgements ........................................................................................ i

Abstract ......................................................................................................... ii

Commonly Used Acronyms.........................................................................iii

Contents........................................................................................................ iv

Chapter 1. Introduction ................................................................................. 1

1.1 Work Published/Produced by the Author...............................................................1

1.1.1 Internal Documents.........................................................................................2

1.1.2 Computational Implementation/Models: Examples and Results....................2

1.2 General Background...............................................................................................2

1.3 Motivation and Context of Research......................................................................4

1.3.1 Two Termination (Damping) Methods for SI-RE..........................................5

1.3.2 Related Work..................................................................................................6

1.3.3 Approach ........................................................................................................6

1.4 Summary of Contributions .....................................................................................7

1.5 Organisation of Thesis............................................................................................8

Chapter 2. Interconnect Modelling ............................................................. 11

2.1 Introduction ..........................................................................................................11

2.2 SSD and DPD Termination Schemes...................................................................12

2.3 PCB Transmission Line Model ............................................................................15

2.3.1 Transmission Line Model .............................................................................15

2.4 Analysis of Point-to-Point Interconnect ...............................................................16

2.4.1 Voltage Transfer Function for Point-to-Point Interconnect..........................16

2.4.2 Parasitics .......................................................................................................19

2.4.3 Currents for RE.............................................................................................20

2.5 Conclusion............................................................................................................22

Chapter 3. SI Modelling.............................................................................. 23

3.1 Introduction ..........................................................................................................23

3.2 2nd-Order Rational Approximation to TF............................................................24

3.3 Characterisation of SI...........................................................................................29

3.3.1 Peak and Steady-State Currents....................................................................30

3.3.2 Delay, Incident-Wave Switching and Settling Time ....................................31

3.3.3 Effects of the Rise Time for Finite Rise Time Step Input ............................37

3.4 Conclusions ..........................................................................................................56

v

Chapter 4. SI Validation.............................................................................. 58

4.1 Introduction ..........................................................................................................58

4.2 SI-SR Validation ..................................................................................................59

4.2.1 Validation Results.........................................................................................60

4.3 Conclusion............................................................................................................69

Chapter 5. RE Modelling ............................................................................ 70

5.1 Introduction ..........................................................................................................70

5.2 RE-Approximation Modelling .............................................................................71

5.2.1 Modelling Approach.....................................................................................72

5.2.2 Assumptions and Limitations .......................................................................73

5.2.3 Derivation of Results ....................................................................................74

5.3 FEKO RE Modelling and Comparison ................................................................76

5.4 Characterisation of RE with Finite Bandwidth Source ........................................82

5.4.1 Results: RE Performance Studies for the SSD and DPD .............................83

5.4.2 Discussion.....................................................................................................86

5.5 Conclusion............................................................................................................86

Chapter 6. RE Validation ............................................................................ 88

6.1 Introduction ..........................................................................................................88

6.2 RE Validation .......................................................................................................88

6.2.1 Validation Results.........................................................................................89

6.3 Conclusion............................................................................................................98

Chapter 7. Conclusion and Future Work .................................................... 99

7.1 Conclusion............................................................................................................99

7.2 Future Work .......................................................................................................100

Appendix A. Glossary and Reference Guide............................................ 102

A.1 Mathematical Conventions................................................................................102

A.2 Common Unit Symbols/Abbreviations .............................................................103

A.3 Definition of Symbols .......................................................................................104

A.4 Physical Constants.............................................................................................105

A.5 Abbreviations and Acronyms ............................................................................106

A.6 Software Packages.............................................................................................107

Appendix B. Useful Conversion Formulae............................................... 108

B.1 Decibel to Neper Conversion.............................................................................108

B.2 Metric to Mils Conversion.................................................................................108

B.3 Ounces to Mils Conversion ...............................................................................108

B.4 dBm to Voltage Conversion in 50 Systems...................................................108

vi

B.5 dBV Far Field Conversion in FEKO...............................................................109

B.6 Electric Far Field Vertical Polarisation Conversion..........................................109

Appendix C. Derivations and Results for Chapter 3 ................................ 110

C.1 2nd-Order Voltage TF Approximations for the Damping Termination Schemes..................................................................................................................................110

C.1.1 2nd-Order Voltage TF Approximation for the SSD Termination Scheme 111

C.1.2 2nd-Order Voltage TF Approximation for the DPD Termination Scheme112

C.1.3 2nd-Order Voltage TF Approximation for the SDD Termination Scheme112

C.2 Envelope-Bound Approximations of the Exact Lossless Voltage TF for the Damping Termination Schemes ...............................................................................114

C.2.1 Envelope-Bound Approximations of the Exact SSD Termination Scheme.............................................................................................................................115

C.3 2nd-Order Voltage SRs......................................................................................116

C.4 Delay Approximation for a 2nd-Order Step ......................................................117

C.5 Initial Current Transient Approximations for a Step Input using Reflection Coefficients ..............................................................................................................119

C.5.1 SSD Current Transient Approximation of the Step Input using Reflection Coefficients..........................................................................................................122

C.5.2 DPD Current Transient Approximation of the Step Input using Reflection Coefficients..........................................................................................................123

C.6 Steady-State Current for a Step Input................................................................124

Appendix D. Design of PCB Interconnects for the Validation Results Presented in Chapter 4 .............................................................................. 126

D.1 Damping Design Considerations.......................................................................126

D.1.1 Termination Scheme Damping Design Considerations.............................126

D.1.2 Steady-State Value of the Voltage Step Response ....................................127

D.2 Test Microstrip PCB Designs............................................................................128

D.2.1 Background on the Microstrip Design.......................................................128

D.2.2 Attenuator Design......................................................................................130

D.2.3 Damping Resistances Design ....................................................................132

D.3 SI Experimental Setup.......................................................................................134

D.3.1 SI Experimental Setup Validation .............................................................136

Appendix E. Derivations and Results for Chapter 5................................. 143

E.1 Microstrip RE Planar Model..............................................................................143

E.1.1 RE Contributions from End Currents.........................................................144

E.1.2 RE Contributions from Polarisation Currents ............................................145

E.1.3 RE Contributions from Line Currents........................................................146

E.2 Complete Microstrip RE Model.........................................................................148

E.2.1 Planar Model Extension .............................................................................148

vii

E.3 Comparison of RE Model to Other Results .......................................................154

Appendix F. Experimental Details for Chapter 6 ..................................... 158

F.1 Microstrip Board Preparations ...........................................................................159

F.2 Calibration..........................................................................................................160

F.2.1 Conducted Loop Calibration ......................................................................161

F.2.2 Test Standard Loop Calibration .................................................................162

F.2.3 Calibration Factors and Verification ..........................................................163

F.3 RE Experimental Setup ......................................................................................168

F.3.1 Antenna Positioning for the Observation Point..........................................169

F.3.2 Test Board Interface to the Reference Plane ..............................................170

F.3.3 External Chamber Setup.............................................................................172

References ................................................................................................. 174

1.1 Work Published/Produced by the Author

Chapter 1 1

Chapter 1. Introduction

1.1 Work Published/Produced by the Author

The following research publications by the author are related to the research work in the

thesis:

Recent Publications

[R‐1] B. Wong and A. Cantoni, “Improved radiated emission model of two damping

schemes for signal integrity management on microstrips validated with MoM,”

in Asia-Pacific Int. Symp. Exhibition Electromagn. Compat., no. 113, pp. 1–4,

2013 © Engineers Australia. ISBN: 978-1-922107-02-2.

[R‐2] B. Wong and A. Cantoni, “MoM validation of the predicted radiated emissions

of two signal integrity damping schemes on PCB microstrips,” in 6th Asia-

Pacific Conf. Environ. Electromagn., Shanghai, China, Nov. 2012, pp. 175–177.

[R‐3] B. W.-J. Wong and A. Cantoni, “Modeling and analysis of radiated emissions

and signal integrity of capacitively loaded printed circuit board

interconnections,” IEEE Trans. Electromagn. Compat., vol. 54, no. 5, pp 1087–

1096, Oct. 2012.

[R‐4] B. Wong, “Some important modelling considerations of signal integrity and

radiated emissions for the study of damping termination schemes,” in

Electromagn. Compat. Soc. Newslett., Electromagn. Compat. Soc. Australia,

IEEE Electromagn. Compat. Soc., Australia, June 2012, iss. 57, pp. 14–15.

[R‐5] B. Wong and A. Cantoni, “Radiated emissions and signal integrity of printed

circuit board microstrips,” in Electromagn. Compat. Symp. 2010, Electromagn.

Compat. Soc. Aust., IEEE Electromagn. Compat. Soc., Melbourne, Victoria,

Australia, Sept. 8–10, 2010, pp. 1–6.

Past Publications

[P‐1] W.-J. Wong. (2007). The impact of transmission line terminations on radiated

emissions, M.Eng. thesis, Curtin Univ. Technol., Perth, WA, Australia. [Online].

Available: http://link.library.curtin.edu.au/p?cur_digitool_dc16943

1.2 General Background

Chapter 1 2

[P‐2] B. Wong and J. Trinkle, “Accurate measurements in semi-anechoic chambers,”

in Electromagn. Compat. Symp. 2006, Electromagn. Compat. Soc. Aust., IEEE

Electromagn. Compat. Soc., Melbourne, Victoria, Australia, Sept. 12–14, 2006,

pp. 11–20.

[P‐3] B. Wong, K. Fynn, F. Schlagenhaufer, and A. Cantoni, “The impact of

transmission line terminations on radiated emissions,” in Proc IEEE Int. Symp.

Electromagn. Compat., Montreal, QC, Canada, Aug. 2001, vol. 1, pp. 52-56.

1.1.1 Internal Documents

Some internal reports written by the author and colleagues [1]–[12] have been

referenced in the thesis. These reports are available on request via email

([email protected]) contact. Some of the reports may also be downloaded

from the link below:

[L‐1] http://www.eece.uwa.edu.au/research/electromagnetic-compatibility/_nocache

1.1.2 Computational Implementation/Models: Examples and Results

Software for the generation and presentation of numerical results presented in the thesis

has been implemented with MathWorks MATLAB and where applicable, checked with

Wolfram Mathematica, Cadence OrCAD Capture and FEKO software packages. More

information on the mentioned packages can be found in appendix section A.6. To obtain

the source files for the packages, requests can be made directly to the author via email

([email protected]).


Major challenges are faced by electronic designers to make electronic systems behave

correctly in a hostile electromagnetic environment. Operation in the gigahertz range

causes unwanted effects to dominate and possible interference with other electronic

devices. A better understanding of the interaction and behaviour of electromagnetic

phenomena and electronic circuits enables a better design of high-speed digital systems

to meet the fast growing needs of the consumer marketplace.


Chapter 1 3

In simple terms, electromagnetic compatibility (EMC) is concerned with ensuring the

correct operation of electrical/electronic equipment in a hostile electromagnetic

environment. This requires an appropriate understanding of the source, path(s) and

reception of electromagnetic energy. Furthermore, the topics of emission and

susceptibility (immunity) are also of significant importance. The term emission refers to

the unwanted generation of electromagnetic energy. On the other hand susceptibility

refers to its propensity to be influenced adversely by electromagnetic interference

(EMI). Advisory and compliance boards for EMC related matters have been established

all over the world to manage the standards and requirements for the electromagnetic

operation of electrical/electronic equipment before making these available to the

consumer market.

The term signal integrity (SI) within the context of the design of electrical/electronic

equipment refers to the management of the quality of an electrical signal. On a printed

circuit board (PCB), SI plays an important role to ensure the correct transmission and

reception of signals along interconnections.

Two classes of interconnections commonly found on PCBs are worth mentioning.

Microstrips are a type of interconnection fabricated on a PCB with a conducting trace

separated from an electrical conducting reference plane by a dielectric (substrate) layer,

whereas striplines are traces sandwiched in between the conducting planes separated by

the substrate material. Microstrips are widely used in the PCB fabrication process for

electronic designs because of their lower production costs in comparison to striplines.

However, microstrips are not enclosed structures on PCBs and consequently are sources

of and victims to unintentional radiation. As microstrip lines are used extensively in

high-speed digital PCB designs, their behaviour in the context of EMC-EMI especially

in the area of radiated emission (RE) is an important subject matter for investigation.

Attempting to improve SI with microstrip interconnects does not necessarily improve

the EMC-EMI performance of the system. The work reported in the thesis is concerned

with an exploration of SI-EMC-EMI issues related to the microstrip interconnection

with particular consideration given to the relationships and interplay between SI and

RE. The development of simple models that allow the joint consideration of SI and RE

is a key objective of the work reported in the thesis. The contributions allow insights to

be gained for some commonly used methods for the management of SI on PCB

interconnects and also provide quantitative model for SI and RE performance to be

1.3 Motivation and Context of Research

Chapter 1 4

predicted. Furthermore, the simplicity of the models makes them directly useful to guide

design of interconnects.

Figure 1.1 provides a pictorial overview of the key topics that arise in the design of a

point-to-point PCB interconnection from the perspective of SI and RE [1].

Figure 1.1 SI-RE roadmap.

From the SI perspective, the design of a PCB interconnect is concerned with ensuring

the integrity of the signals generated at the source, travelling through the

interconnection path, and then arriving at the receiver. However, the electrical currents

generated by the signal source travelling along the interconnection also give rise to

electromagnetic radiation. Although there have been extensive studies in the area of SI

and RE, the treatments have been mutually exclusive and without any insights into

potential tradeoffs between SI and RE, performance and without simple models to allow

easy quantitative prediction.


In the context of practical research and development in the engineering design of high-

speed digital systems, interconnect design plays a critical role [19]–[24]. The SI-RE

Receiver End Management

Damping

Resistor

Receiver Equalisation

Compensation

Transmission Line Issues

Impedance Mismatch

Overshoot, Undershoot & Ringing

Attenuation

Dielectric Absorption Losses

Skin Effect

Source End

Signal Integrity Management

Receiver End

Signal Integrity Management

Source End Management

Damping

Resistor

Pre-Emphasis

Signal Amplitude

Signal Integrity (SI)

Microstrip Interconnect

Radiated Emission (RE)

Electromagnetic Compatibility


Chapter 1 5

roadmap as shown in Figure 1.1 highlights the many issues of high-speed digital design

such as transmission line effects, reflections caused by impedance mismatches,

attenuation, etc [19]–[27]. For the assurance of SI in high-speed digital design, the PCB

interconnect/trace must be treated as a transmission line. Transmission line effects are

problematic at high speeds and can be managed with the introduction of termination

management schemes such as series, parallel, Thévenin, RC/AC [24]. Terminations

involving damping resistances placed at the source or receiver/destination end of single-

ended transmission lines will form the core study of this research work.

Figure 1.2 illustrates the location of the termination components and other elements of a

point-to-point interconnection that is the focus of the work reported in the thesis.

Figure 1.2 A physical representation of the use of damping terminations that may be found on a PCB

trace.

1.3.1 Two Termination (Damping) Methods for SI-RE

In the thesis, two important schemes are considered for the management of SI, [R-1]–

[R-3], [R-5], [P-1], [P-3]. The two schemes, namely the source series damping (SSD)

and destination parallel damping (DPD), will be studied in detail as the choice of

damping termination for the management of SI. An interconnect with resistance added

in series with the source is referred to as the SSD scheme or SSD in short. An

interconnect with resistance added as a shunt across the destination capacitance is

referred to as the DPD scheme or DPD in short. For this thesis, we use the term

Microstrip Trace l

Source (Driver)

Destination (Receiver)

Dielectric

Ground Plane

h

w

(Parallel Damping)

(Series Damping)

LZ

SZ

EH

, CZ

z

O

xy

oP


Chapter 1 6

damping to refer to damping resistors. These termination techniques also affect the RE

from the trace. The origin of the term “damping” will be evident when the approximate

model for determining SI performance is developed and the RE results are presented

(see also Chapter 3, pp. 23–57 and Chapter 5, pp. 70–87). Other termination techniques

[24], [35]–[36] are sometimes used. These are briefly reviewed in the thesis and their

relation to the SSD and DPD is noted.

1.3.2 Related Work

There is a plethora of published works on PCB designs in the areas of SI and/or EMC-

EMI. Discussions of issues and design approaches in SI and EMC-EMI are given in

[27]–[34]. Reference [35] introduces some termination schemes for impedance

matching which are suitable for digital systems using standard logic families; [36]

explores termination schemes, their roles and benefits in SI in the case of resistive

loading; [37] uses a co-simulation approach utilizing a full-wave electromagnetic tool to

study matched terminations; and [38] reports a study of the geometrical parameters of a

microstrip for the case of series termination for managing reflections. A comprehensive

study on terminations is also given in [19]–[20], but in the context of SI these works

only consider matching in the context of managing transmission line reflections. The

work in [35] notes that improved SI generally improves RE. However, the question of

the relative merits of different terminations with respect to RE is yet to be addressed in

any depth for capacitively loaded interconnects. A key objective of this research is to

develop simple models that allow easy quantitative analysis and provide insights into

the interplay between EMC-EMI and SI for two commonly used termination

schemes/techniques. The focus is confined to SI-RE issues in the context of short PCB

traces. Notwithstanding the short trace constraint the results presented in the thesis show

that work is applicable to traces of practical interest.

1.3.3 Approach

A good understanding of the roles of the damping resistors and well founded

comparisons between the two damping schemes can be achieved using simplified

analytical models that feature the interconnect parameters and SI/RE performance in an

easily understood form. For example, the models allow a comparison of SSD and DPD

under equivalent SI conditions. In the thesis, we determine the termination parameters

for SSD and DPD which yield approximately equal time domain step responses. To this

1.4 Summary of Contributions

Chapter 1 7

end, we develop simple 2nd-order models for the SSD and DPD that are suitable

approximations for capacitively loaded short PCB traces.

In relation to the REs, approximate analytical models are required to compute the

magnitude of the radiated electric far-field applied to the SSD and DPD termination

schemes. The computation of the electric far-field can be obtained through the various

approaches listed in [39]. For the purpose of obtaining a quantitative understanding of

the impact of the damping provided by SSD and DPD on REs, an analytical model for

the REs from short traces is chosen to enable fast numerical computation of REs. The

calculation of the magnitude of the electric far-field for a short trace, based on the

currents along the trace which is modeled as a transmission line, may be tackled using

the results of recent works listed in [R-1]–[R-5] and references therein.

1.4 Summary of Contributions

The key contributions of the research work reported in the thesis are as follows:

1‐A1 The development of a 2nd-order model for point-to-point interconnects that

permits the characterisation of the SI performance of two frequently encountered

termination schemes. The model also provides a basis for the design of an

interconnect to achieve the required SI performance in terms of key indicators such

as settling time and incident-wave switching (see definition in subsection 3.3.2, pp.

32–33). Furthermore, the 2nd-order model allows the selection of interconnect

parameters for the two termination schemes such that comparable SI performance is

achieved and other characteristics such as peak transient current, steady-state current

and RE performance achieved by the two termination methods can be legitimately

compared.

1‐A2 The development of a simple model for predicting the RE performance of two

termination schemes. The prediction of RE using the model is computationally

efficient and very useful for the characterisation of the RE performance of SSD and

DPD under approximately equal SI conditions. The model developed allows for

interconnect losses and hence enables the impact of the assumption of no loss to be

evaluated.

1.5 Organisation of Thesis

Chapter 1 8

1‐A3 The application of the simple models developed to compare the relative RE

performance of SSD and DPD under equivalent performance with respect to SI.

1‐A4 The experimental validation of the simple models developed using time

domain step response measurements on printed circuit traces and the measurements

of emission from the traces in an EMI chamber.


Figure 1.3 illustrates the topics covered in each chapter and the order in which they are

covered. Detailed derivations that support each of the chapters are relegated to the

appendices to avoid interrupting the flow of the key concepts.

Figure 1.3 Core thesis outline.

Introduction (Chapter 1)

Interconnect Modelling (Chapter 2)

SI Modelling (Chapter 3)

SI Validation (Chapter 4)

RE Modelling (Chapter 5)

RE Validation (Chapter 6)

Conclusion and Future Work (Chapter 7)

(Appendices A–F)


Chapter 1 9

Chapter 1 presents the key topics that arise in the design of a point-to-point PCB

interconnection from the perspective of SI and RE and the motivation that underpins the

core contributions arising from this work. In the context of high-speed digital switching,

the SSD and DPD termination schemes for SI management are introduced. Related

work within the context of this research on damping terminations is reviewed. Lists of

research contributions as well as relevant research publications are also given. A

structural overview of this thesis is finally presented.

Chapter 2 presents the SSD and DPD termination schemes studied in the thesis. The

modelling of a PCB trace which is the transmission line in an interconnect is

established. The assumptions that underpin the modelling are clearly identified. The

transmission line model is used in subsequent chapters. In the first instance, low order

models are developed for predicting the SI performance of SSD and DPD, and also for

identifying the key parameters that control SI performance. The transmission line model

is also used in the development of an analytical model for predicting REs from a trace,

and hence from SSD and DPD based interconnects

Chapter 3 presents 2nd-order approximations for the transfer function of point-to-point

interconnect that can be used to determine the SI performance characteristics of SSD

and DPD. The relationship between the step response of a 2nd-order system and SI

performance characteristics is established. The nature of the 2nd-order approximation

and its dependence on system parameters such as pulse rise/fall time, capacitive load

and line delay is explored.

Chapter 4 is concerned with the design of the SI experiments to obtain SI measurements

for the validation of the 2nd-order models developed in Chapter 3. The chapter also

presents a range of experimental results which are compared to results predicted using

the 2nd-order model that has been developed for SSD and DPD.

Chapter 5 presents modelling of RE from a PCB trace which is the transmission line in

a point-to-point interconnect. The REs predicted with the model for the SSD and DPD

interconnects is compared to those obtained using a FEKO method of moments (MoM)

simulation. The RE model is also used to characterise the REs from the SSD and DPD

interconnects with finite bandwidth source.


Chapter 1 10

Chapter 6 is concerned with the design of RE experiments to obtain RE measurements

for the validation of the RE model developed in Chapter 5. The chapter also presents a

range of experimental results which are compared to results predicted using the RE

model applied to SSD and DPD.

Chapter 7 presents key conclusions regarding the work presented in the thesis. Avenues

for future work relating to the two damping schemes are also identified.

The appendices include all relevant derivations, simulation models and the design of the

experimental setup for this research work. Included is the glossary and reference guide

to the terminology, symbols, etc used throughout this thesis.

2.1 Introduction

Chapter 2 11

Chapter 2. Interconnect Modelling

2.1 Introduction

In Chapter 1 an overview has been given in terms of the main issues arising from the

design of a point-to-point PCB interconnection from the perspective of SI and RE.

Management of SI can be achieved via the SSD and DPD termination schemes studied

in the thesis and variants of these. The damping terminations will affect the RE

performance of a PCB interconnection.

In this chapter, the model of a PCB trace which is the transmission line in a point-to-

point interconnect is established. The assumptions that underpin the modelling are

clearly identified. The assumptions and approximations help us to reduce the

complexity of the derived formulations from the theory. The transmission line model is

used in subsequent chapters. In Chapter 3, 2nd-order models are developed for

predicting the SI performance of SSD and DPD, and also for identifying the key

parameters that control SI performance. The transmission line model is also used in

Chapter 5 as part of the development of an analytical model for predicting REs from a

trace, and hence for predicting the RE from SSD and DPD based interconnects

For SI analysis, the lossless transmission line model can be used to approximately

model short interconnections. The terminations for the SSD and DPD together with the

transmission line model can be used to determine the input source terminal to

destination terminal behaviour, i.e. the transfer function, of a point-to-point

interconnect. SSD and DPD represent idealised scenarios that do not include parasitics

present on a point-to-point PCB interconnect. For example, connecting vias can be

modelled using inductances and capacitances. Key parasitics that may affect the

experimental setup for the step response have been investigated. In the thesis, we are

interested in capturing the main trends of the step response waveforms. Hence the

parasitic effects have been assumed to be negligible.

For RE analysis, the lossy transmission line model is used to obtain the position-time

current distribution. For high-speed digital PCB designs, both the common-mode and

differential-mode currents are central to the emitted radiation. For the point-to-point

interconnect, the common-mode current is considered small in comparison to the

functional differential-mode currents at high speeds [40]. In the thesis, we investigate

2.2 SSD and DPD Termination Schemes

Chapter 2 12

the RE from a microstrip due to the differential-mode currents in which the current

distribution from the transmission line model is used. Moreover, as will be seen in the

RE validation results in Chapter 6, the RE due to the intentional differential-mode

currents can be measured experimentally with some care.

This chapter is organised into three main sections. In the next section, the SSD and DPD

termination schemes are described and electrical models presented. In section 2.3 a PCB

transmission line model is presented including a subsection on model assumptions and

approximations. The analysis of a point-to-point interconnect is given in section 2.4.

Section 2.4 presents expressions for the transfer function and the transmission line

currents obtained from the transmission line model. A subsection on the modelling of

parasitics is also presented in section 2.4. Some conclusions are presented in section 2.5.


For accurate modelling of SI in high-speed digital design, the PCB interconnect/trace

must be treated as a transmission line. Transmission line effects are problematic at high

speeds and can be managed with the introduction of terminations such as series,

parallel, Thévenin, RC/AC and diode terminations [24]. In the thesis, we consider two

termination schemes that are suitable for the management of SI for short interconnects.

An interconnect with resistance added in series with the source SV will be referred to as

SSD with the damping designated as SSD.R An interconnect with resistance added in

parallel with the capacitance LC at the destination is referred to as DPD with the

damping designated as DPD.R The idealised models for the SSD and DPD are shown in

Figure 2.1 and Figure 2.2 respectively. In the figures, ,CR dT and l are parameters

related to a transmission line which are described in section 2.3 and subsection 2.4.1.

Figure 2.1 Idealised SSD termination scheme.

, dT l

CR

SSDR

SV LC


Chapter 2 13

Figure 2.2 Idealised DPD termination scheme.

While the SSD model allows for sources with finite resistance as well as any added

series resistance, the idealised DPD model does not allow for a practical scheme. A

model for a finite resistance source is shown in Figure 2.3.

Figure 2.3 Practical DPD or namely the source-destination damping (SDD) termination scheme with

series SDR at source end and parallel DDR at destination end.

Figure 2.4 shows a variant of the SSD in which the damping resistance SLDR is place in

series with the transmission line at the destination. Provided that LC is not zero, it can

be shown that this variant has approximately the same SI characteristics as the SSD.

This variant is relevant for bidirectional point-to-point interconnection in which the role

of source and destination changes depending on the direction of information transfer.

Figure 2.4 Variant of the SSD.

DDR LCCR

SDR

SV

, dT l

CR DPDR SV LC

, dT l

, dT l

LCCRSV

SLDR


Chapter 2 14

Figure 2.5 shows a variant of the DPD. The capacitor, ACDL ,C ensures that there is no

current flow in the steady-state and hence there is no DC power dissipation. The

damping characteristics for the variant are approximately the same as for DPD provided

that the time constant ACDLD DLR C is larger than the two-way delay of the interconnect line.

Figure 2.5 Variant of the DPD (RC/AC).

The AC coupling of the damping resistor, DLD ,R introduces an additional transient

component whose effect on the SI characteristics depends on whether the source signal

is a periodic signal such as a clock or is an aperiodic pulse. The variants of SSD and

DPD noted are not considered in the thesis. However, much of the modelling developed

can be extended to these variants.

Nonlinear terminations also exist [24], [33]. The modelling of these is beyond the scope

of this thesis.

In the thesis, we use the term damping to indicate that loss has been introduced in the

interconnect system which has little loss under the short line assumption. In the SSD

and DPD schemes, the loss is determined by SSDR and DPDR respectively. This damping

due to loss is reflected in the damping factor of the approximate 2nd-order model for

the transfer function of the interconnect that is developed in Chapter 3.

It is worth noting that in contrast to short lines, line loss can be excessive in long lines

and to achieve acceptable SI the issue is not the addition of loss but rather one of

equalisation of the point-to-point transfer function through compensation techniques at

the source and/or the destination [19]–[27]. This is shown in Figure 1.1 as “pre-

emphasis” at the source and “compensation” at the destination.

SV LCCRDLDR

ACDLC

, dT l

2.3 PCB Transmission Line Model

Chapter 2 15

2.3 PCB Transmission Line Model

2.3.1 Transmission Line Model

A number of assumptions and approximations in the modelling of a PCB interconnect

can be made to develop simple analytical models for damping analysis. It is shown in

[18] that under the assumptions of quasi-TEM, the trace associated with a point-to-point

interconnect of a PCB can be modelled using a circuit model with per-unit-length

parameters as illustrated in Figure 2.6.

Figure 2.6 L-type distributed per-unit-length (pu) pu pu pu puR L G C parameters.

A model that includes the source and terminations that can be used for the analysis of

SSD and DPD is shown in Figure 2.7.

Figure 2.7 A two-conductor transmission line (TL) with source and terminations.

Connected to the source end terminals is a sinusoidal source SV f with a series source

impedance .SZ f At the load end ,x l a shunt load LZ f is connected. In general,

pu2j fL x puR f x

x x x

lossyI

puG f x pu

1

2j C x

lossyˆ ,I x f lossy

ˆ ,I x x f

lossyˆ ,V x x f lossy

ˆ ,V x f

, Cf Z f

l SZ f

SV LZ f

0x x lx

LV f lossyˆ ,V x f f

x

lossyˆ ,I x f

2.4 Analysis of Point-to-Point Interconnect

Chapter 2 16

SZ f and LZ f are complex frequency dependent quantities, for example, a

capacitor. Along the TL in the x direction there exist voltages lossyˆ ,V x f and currents

lossyˆ , .I x f These voltages and currents are set up by travelling waves traversing back

and forth along the TL with a complex propagation constant of f and a TL

characterised by the complex characteristic impedance CZ f given by [P-1], [13]–

[16]

pu pu pu pu2 2

f f j f

R f j f L G f j f C, (2.1.a)

pu pu

pu pu

2

2C

R f j f LZ f

G f j f C

. (2.1.b)

Note that (2.1.a)–(2.1.b) have been written in terms of the distributed per-unit-length

parameters, as shown in Figure 2.7. For the lossy TL model, puR f and puG f are a

function of frequency .f The complex propagation constant is defined in terms of a real

loss component Np m and an imaginary phase constant rad m .

When the distributed per-unit-length losses puR f and puG f are both zero, the TL

model is known as the lossless TL model.


2.4.1 Voltage Transfer Function for Point-to-Point Interconnect

To transfer a signal faithfully from source to destination, the transfer function (TF)

between the source and destination must be essentially constant over the range of

frequencies that the signal to be transferred contains significant energy. Also, the phase

of the TF should be close to linear with frequency in the same range. Thus, evaluation

of the TF is a starting point for investigating SI performance of an interconnect and

examination of the TF gives many clues as to the likely SI performance of an

interconnect. For digital signals, SI performance indicators are usually specified in the

time domain. High order TFs do not lend themselves to simple characterisation in the

time domain. Hence, in Chapter 3 a 2nd-order rational approximation to the TF obtained


Chapter 2 17

in this subsection is proposed. SI characteristics are quantified using the time domain

step response of this low order approximation.

The TF for the system shown in Figure 2.7 can be obtained by straightforward analysis

[3], [7].

The exact lossless TF ˆ ˆL SH f V f V f for C CZ R may be written as [3]

exactlossless 2cos 2 sin 2

C L

C S L d C S L d

R ZH f

R Z Z fT j R Z Z fT

. (2.2)

In (2.2), ,dT represents the one-way propagation delay which may be written in terms of

the dielectric phase constant, , given by [P-1]

eff

02

d r

l lT

f c, (2.3)

where l is the line length, 0c the speed of light in a vacuum, and effr the effective

permittivity of the dielectric.

The SSD termination scheme presented in Figure 2.1 is defined by terminations

SSDSZ R , (2.4a)

1

2LL CL

Z Zj fC

. (2.4b)

The DPD termination scheme presented in Figure 2.2 is defined by terminations

0SZ , (2.5a)

DPDLL CZ Z R . (2.5b)

The TF models for the exact SSD and exact DPD cases can be obtained by directly

substituting the termination definitions given by (2.4a)–(2.5b) into (2.2) to yield

exactSSD

SSD

cos 2 2 sin 2

2 cos 2 sin 2

C

C d C L d

C L d d

RH f

R fT fR C fT

jR f R C fT fT

, (2.6a)

exact DPDDPD

DPD cos 2 2 sin 2 sin 2d C L d C d

RH f

R fT f R C fT jR fT

. (2.6b)


Chapter 2 18

Special Case: Matched SSD

A special case of the SSD is worth noting at this point since a simple exact TF can be

obtained from (2.6a) for the matching condition when SSD CR R to yield

2

matchedSSD 1 2

dj fT

C L

eH f

j f R C

, (2.7)

where the numerator reflects a pure time delay .dT This TF can be represented by the

circuit in Figure 2.8.

Figure 2.8 Matched SSDR to the characteristic resistance CR of the TL for the SSD.

The step response (SR) corresponding to the TF given by (2.7) is given by

SR step1 , for 0d

C L

t T

R Cdv t e v t T t

. (2.8)

The delay matchs for this SR to reach a fraction thld0 1V of the final steady-state value

can be solved directly from (2.8) and is given by

matchthldln 1s dT V , (2.9)

in which .C LR C

Practical Case: Source-Destination Damping (SDD)

The idealised DPD depicted in Figure 2.2 cannot be realised in practice because the

source will have a small but finite non-zero impedance. Thus, in a practical case, the

DPD is more accurately modelled as shown in Figure 2.3. This model will be referred to

as the SDD scheme.

The TF for the SDD scheme is given by [7]

exact DDSDD

SD DD DD

2SD DD SD DD

cos 2 2 sin 2

2 cos 2 sin 2

C

C d C L d

C L d C d

R RH f

R R R fT f R R C fT

j f R R R C fT R R R fT

. (2.10)

LC step dv t T

SSD CR R SRv t


Chapter 2 19

2.4.2 Parasitics

For the experimental validation that will be presented in Chapter 4 and Chapter 6, the

microstrip PCB test board used have been realised based on designs from the ideal SSD

and DPD schemes. From a practical point of view, the actual PCB test boards have via

connections and other short trace interconnections as shown in Figure 2.9. These

connections together with the surface mount devices (SMDs), pads, etc form parasitics.

Additionally, the measurement setup will also introduce parasitics, for example, from

the probe loading as shown in Figure 2.10 for the SR measurements used for validating

the 2nd-order models developed for SI.

Figure 2.9 Example of sources of parasitics on a test PCB.

Figure 2.10 A probe loading model [85].

Source End Destination End

Via Via

Short Connecting

Traces

Short Connecting

Trace

SMD Pads

SMD Pads

Probe


Chapter 2 20

As part of the modelling and design of the experiment, these various parasitics have

been investigated in detail by including them in the model as shown in Figure 2.11 for

the OrCAD (PSPICE) model. For example, the vias can be modelled as additional series

inductances as shown in Figure 2.11. Although the parasitics are important

considerations for the experimental design process, they complicate the validation

models from theory. Moreover, we are interested in developing simple yet useful

models to address high-speed digital design challenges that will meet SI-RE. Insofar as

the parasitics are concerned, their effects can be considered small and can be neglected.

For example, the load capacitances used on the PCB test boards have a 0.25 pF

tolerance and the probe capacitance for the SR validation measurements presented in

Chapter 4 is nominally 0.8 pF as shown in Figure 2.10. With additional stray

capacitances from the vias, pads, etc the total added capacitances to the nominal value

of the load capacitance will be somewhere in the range of 1 pF to 2 pF, which can be

considered small. The validation models have been deliberately kept simple to make the

key modelling parameters tractable since we will see the differences when comparing to

the total effect taken from the measurements results.

Figure 2.11 Investigations of parasitics.

2.4.3 Currents for RE

The TL current obtained from the model shown in Figure 2.7 is given by [P-1], [13]–

[16]

lossy

lossy

ˆ coshˆ ,

sinh

CS

L

Z f f l xV fI x f

D f Z f f l x

, (2.11a)

Probe Loading Model Vias: Series Inductances


Chapter 2 21

lossy

2

cosh

sinh

C S L

C S L

D f Z f Z f Z f l

Z f Z f Z f l

. (2.11b)

Equation (2.11a) will be used to derive the RE presented in Chapter 5. Note that lossyI

represents the time-harmonic phasor current in which the time factor 2j fte has been

suppressed. Moreover, at high frequencies, the differential trace currents become a

significant RE contributor [40]. The thesis is concerned with REs due to differential

currents. For the microstrip, there are the dielectric polarisation currents that contribute

to the RE [P-1]. The dielectric polarisation currents are caused by electric dipole

moments in the dielectric. When an excitation is applied to the microstrip the bound

electrons in the dielectric will align themselves creating these dipole moments also

described in [P-1]. The dielectric polarisation currents can be modelled with TL

currents, lossyˆ ,I as [P-1], [41]

polpol,

lossy

ˆˆ

ˆ11

z

r

dI xJ dy

dxdI x

dx

, (2.12)

in which pol, ˆ

zJ is the z component of the dielectric polarisation current density and r

is the dielectric permittivity.

Equation (2.12) can be used to relate the dielectric polarisation current density on the

microstrip to the trace current. Hence, the RE due to the dielectric can be obtained.

It is important to note that the TL model assumes a quasi-TEM field structure which

will hold for thin traces and microstrips with thin dielectrics up to several millimetres,

for frequencies of practical interest.

It should also be noted that the TL model does not consider common-mode currents

which may exist in a practical PCB interconnect. For digital interconnects the common-

mode currents are more relevant to RE than SI in most cases. The RE model developed

in Chapter 5 is based on the currents predicted using the TL model shown in Figure 2.7

and hence the RE model inherits the limitation that it does not include contributions to

RE from common-mode currents associated with an interconnect. Consideration of this

limitation is very important in the design of the experimental setup described in Chapter

6 used for the validation of the RE model.

2.5 Conclusion

Chapter 2 22

2.5 Conclusion

Microstrip interconnect modelling that leads to simple approximate models for SI and

RE in Chapter 3 and Chapter 5 respectively have been described. The TL model is used

to develop exact lossless (2.6a)–(2.6b) TF models for the SSD and DPD under

investigation. For the special matched case for the SSD, a simple first-order TF can be

obtained directly from (2.6a). The exact TF models developed are used for the SI

characterisation of the SSD and DPD in Chapter 3. The currents arising from the TL

model is later used to develop the RE model in Chapter 5.

In this chapter, it has been noted that parasitics for point-to-point interconnects are

important considerations for the experimental design process.

3.1 Introduction

Chapter 3 23

Chapter 3. SI Modelling

3.1 Introduction

The TL modelling presented in Chapter 2 is the foundation for the development of

approximate frequency and time domain models for the characterisation of SI. The

approximate models in both the frequency and time domain help us to gain insights into

the role of damping on SI management of a point-to-point interconnection.

This chapter is concerned with the development of approximate 2nd-order linear time

invariant models that will be shown to be very useful for the characterisation and

prediction of SI performance of SSD and DPD. The nature of the 2nd-order

approximation and its dependence on system parameters such as pulse rise/fall time,

capacitive load and line delay is explored using PSPICE. Naturally the ultimate

validation of the approximation is with experimental measurements. This is presented in

Chapter 4.

A number of approaches can be used to obtain finite order rational approximations to

the TF of the point-to-point interconnect [46]–[47]. One approach, referred to here as,

the multipole approach, [3]–[5] can yield approximations of any desired order including

the Padé approximation [48]–[49] of a specified order. The author has investigated, [3]–

[7], the use of multipole techniques based on [50]–[51]. However, the models do not

provide directly accessible insights on the impact of the interconnect parameters on SI

performance. Hence, low order approximations have also been investigated. Some

advantages of using the low order approximations may often produce simpler and

computationally efficient models compared to the multipole approach, but at the

expense of reduced accuracy at high frequencies. 2nd-order approximations have been

found to be more useful. A very direct approach to obtain a 2nd-order approximation is

via a Taylor series truncation of the transcendental TF given by (2.2). This approach

referred to henceforth as the 2nd-order approximation is described in this chapter.

As already noted, some aspects of SI performance can be deduced from the TF.

However, SI performance of a point-to-point interconnect can be assessed more directly

from the time domain behaviour, such as from the SR, associated with the TF.

Moreover, characteristics such as damping, incident-wave switching, settling time and

delay, are directly observable from the SR of the interconnect. Thus, as described in this

3.2 2nd-Order Rational Approximation to TF

Chapter 3 24

chapter, the SR associated with the approximate 2nd-order TF for the 2nd-order

approximation is used to provide the characterisation of the SI performance of the point-

to-point interconnect.

Elements of the work presented in this chapter on low order modelling and SI

characterisation have been published by the author in [3]–[5].

The chapter is organised into two main sections. Discussions and results related to the

development of the framework for the characterisation of SI are presented in section

3.2. In section 3.3, the simple 2nd-order models and the various time domain

characterisation models are presented. Some conclusions are offered in section 3.4.


There are several methods for obtaining finite order rational function approximations to

the TF in (2.2). It has been found that a simple 2nd-order rational approximation is more

useful than higher order approximations for the purpose of characterisation of SI

performance of SSD and DPD and also for the purpose of allowing a comparison of the

relative merits of SSD and DPD. It is shown in appendix section C.1 that under suitable

assumptions the TF (2.2) can be approximated by the following 2nd-order rational TF

[55]–[56],

2

2nd2 2

22

n

n n s j f

H fs s

. (3.1)

The derivation in appendix section C.1 involves a first term Taylor series truncation and

the use of cos 1l and sin ,l l based on the underlying assumption that 1.l

Note that is a function of and hence the assumption involves the length of the TL

and the frequency range of interest. The shorter the line, the higher the frequency range

over which the assumption 1l is valid. The maximum frequency of interest is

dictated by the frequency extent of the spectrum of the source driving the interconnect.

For digital signals this maximum frequency is determined primarily by the rise/fall time

of the source. Indeed, the impact of rise and fall time on the quality of the low order

approximation is considered in some detail in subsection 3.3.3.

The 2nd-order TF approximations for the SSD and DPD schemes, can be obtained from

(2.6a)–(2.6b). Define SSD or SSD written in a compact notation SSD, DPD


Chapter 3 25

in (3.1), then 2ndSSD, DPDH may be expressed as shown in Table 3.1.

Description 2nd-Order SSD, DPD and SDD TF Approximations

SSD and DPD TF

2

2ndSSD, DPD 2 2

SSD, DPD 22

n

n n s j f

H fs s

(3.2)

SSD and DPD System Natural Frequency

1 n

C L dR C T (3.3)

SSD Damping Factor

SSDSSD

1

2

C L d

C C L d

R R C T

R R C T (3.4)

DPD Damping Factor DPD

DPD

1

2 C d

C L

R T

R R C (3.5)

Table 3.1 2nd-order TF approximations for SSD and DPD termination schemes.

For the SDD termination scheme, the TF can be approximated by another form of the

2nd-order rational TF given by [7],

SDD

SDD SDD

2SDD2nd

SDD 2 2

22

n

n n s j f

KH f

s s

, (3.6)

in which SDDK is a scaling factor.

The coefficients in the TF, 2ndSDD ,H given by (3.6) are given in Table 3.2.

Description 2nd-Order SDD TF Approximation

SDD Scaling Factor

DDSDD

SD DD

RK

R R

(3.7)

SDD System Natural Frequency

SDD

SDD

1 C L dn

R C T

K (3.8)

SDD SDD SD DDK (3.9a)

SDSD

1

2C L d

C C L d

R R C T

R R C T

(3.9b)SDD Damping

Factor

DDDD

1

2C d

C L

R T

R R C (3.9c)

Table 3.2 2nd-order TF approximations for SDD termination scheme.


Chapter 3 26

A key result of the approximate 2nd-order modelling is that we can see that, for the

same line length and same load capacitance, it is possible to achieve identical

approximate 2nd-order TFs by choosing the appropriate damping resistors for SSD and

DPD schemes. This is important since the relative merits of SSD and DPD with respect

to characteristics such as RE, power dissipation and peak currents can be compared

under the condition that the two schemes have the same TF and hence the same SR, a

useful practical condition.

An indication of the key characteristics of the 2nd-order approximation in the frequency

domain can be gained from the following Figure 3.1, Figure 3.2 and Figure 3.3. The

figures show the TF given by (2.2) and the approximation (3.2) for SSD and DPD for a

number of parameter sets that yield a damping of 0.5. The effect of different

damping factors is examined in more detail in subsection 3.3.2 which is concerned with

the time domain SR of the system and the approximation.

Figure 3.1 2nd-order TF model in comparison to the exact TF models for the SSD and DPD termination

schemes for a trace length of 5 cml SSD DPD70 , 10 pF, 0.5, 32.1 , 45.8 .C LR C R R

30 100 1000 2000-40

-30

-20

-10

0

10

20

Frequency (f/MHz)

Vol

tage

TF

Mag

nit

ude

(dB

)

2nd-Order: SSD, DPDExact SSDExact DPD


Chapter 3 27





30 100 1000 2000-40

-30

-20

-10

0

10

20

Frequency (f/MHz)

Vol

tage

TF

Mag

nit

ude

(dB

)


30 100 1000 2000-40

-30

-20

-10

0

10

20

Frequency (f/MHz)

Vol

tage

TF

Mag

nit

ude

(dB

)



Chapter 3 28

Observations:

3‐A1 The 2nd-order approximation captures the key characteristics at low

frequencies - the first peak, the location of the first peak, the control of the first peak

with the damping due to the termination. The actual TF has repeated resonances at

high frequencies. As one would expect, these are not represented by a 2nd-order

rational approximation since additional modes would be required.

3‐A2 The 2nd-order approximation may well be acceptable if the high order

resonances are not excited due to the limited spectrum of the source. This is

investigated below by considering a source with finite transition time. A real

interconnect will also have losses at high frequencies that have not been included in

the interconnect model of Chapter 2. The impact of these losses will be evident in

the experimental validation results that are presented in Chapter 4.

3‐A3 For the SSD, the peaks of the higher order resonances are bounded and

decrease as the frequency increases. Hence, the 2nd-order approximation can be

expected to be quite useful for prediction of the response of SSD.

A useful result that may be obtained for the magnitude of the exact TF for the SSD is

the upper envelope-bound derived in appendix subsection C.2.1, which is given by

SSD

exactSSD

2 1min ,

1

2C Lx C

f R C L x R R R

H ff C R

. (3.10)

As shown in [6] a similar useful bound for DPD does not exist for the condition

2 1.C Lf R C

Note that the function (3.10) is inversely proportional to .f This means that as the

frequency increases, the magnitude of the resonance peaks of the TF for SSD diminish.

Furthermore, damping the low order peaks in the frequency domain by design

automatically dampens the high frequency peaks. Therefore, the high frequency

components of the propagating signal are further reduced in amplitude, which

consequently improves the model for short length TLs for SSD.

3.3 Characterisation of SI

Chapter 3 29

An example plot of the envelope-bound for the SSD in comparison to the exact value is

given for a 10 cm TL and with a characteristic resistance of 70 ,CR which results

in an approximate one-way TL delay of 0.6 ns.dT As can be seen in Figure 3.4, as the

frequency increases, the high frequency resonances decrease in amplitude when

damping is introduced, which is equivalent to adding the SSD ,R and which can be

obtained via (3.4).

Figure 3.4 SSD upper envelope-bound 10 cm, 70 , 10 pF, 0.5 .C Ll R C


For the characterisation of SI of a switching digital signal, the peak current, the steady-

state current, incident-wave switching, settling time and delay are important aspects to

be considered. Note that while we often look at the SR to evaluate SI performance, it is

important to realise that in some circumstances SR does not provide adequate

information to assess SI. An eye pattern may be required when delays are long and/or

the transient response persists for longer than the pulse/bit period [13]. This typically

occurs for long lines in which loss, particularly from the skin effect, becomes dominant

at high frequencies. Indeed, under these circumstances there is effectively too much

damping. As noted in the introduction, SI is then achieved through signal pre-

30 100 1000 2000-20

-15

-10

-5

0

5

10

15

20

25

30

Frequency (f/MHz)

Vol

tage

TF

Mag

nit

ude

(dB

)

Upper Envelope-BoundExact


Chapter 3 30

compensation at the source and/or equalisation at the destination and TL matching is

generally used. In addition, differential TL interconnect are employed. The management

of SI on long lines are not considered in the thesis.

This section is broken into three subsections. In the next subsection, the analysis of peak

and steady-state currents is presented. In subsection 3.3.2, the characterisation of delay,

incident-wave switching and settling time of an interconnect based on the 2nd-order

model are presented. Subsection 3.3.3 presents the effects of finite rise/fall time on how

well the SR of the 2nd-order approximation models a point-to-point interconnect based

on SSD and DPD.

3.3.1 Peak and Steady-State Currents

Transient and steady-state currents for the two termination schemes are important

design considerations that determine power dissipation and internal noise generation in

a digital system. Here we examine the peak transient and steady-state currents due to a

step input of 00, .V The derivations of these currents are detailed in Appendix C.

For SSD the corresponding transient currents at 0t and 2 dt T are

0SSD

SSD

0C

Vi

R R

, (3.11a)

SSDSSD

SSD SSD

22 3 C

d P PC C

R Ri T I I

R R R R

, (3.11b)

where

0P

C

VI

R . (3.12)

For DPD the corresponding transient currents at 0t and 2 dt T are

DPD 0 Pi I , (3.13a)

DPD 2 3d Pi T I . (3.13b)

While there are obvious differences between the SSD and DPD, an inspection of the

circuits corresponding to the two schemes shown in Figure 2.1 and Figure 2.2 reveal the

following:

3‐B1 The peak transient current for a step input is less for the SSD circuit compared

to the DPD circuit as can be seen from (3.11a)–(3.13b).


Chapter 3 31

3‐B2 There is zero steady-state current in the SSD circuit irrespective of whether the

digital signal steps from low to high or from high to low as derived in appendix

section C.6. Consequently, there is zero power dissipation in the circuit in the

steady-state.

3‐B3 The steady-state current in a DPD circuit to a step input is 0 DPDV R when the

digital signal steps from low to high and zero when it steps from high to low as

derived in appendix section C.6. Thus, for a high level digital input there is power

dissipation in the steady-state.

3.3.2 Delay, Incident-Wave Switching and Settling Time

Figure 3.5 and Figure 3.6 show the SRs of a 2nd-order system for a positive step and a

negative step respectively. The SRs are plotted for different damping factors. The plots

also show a number of important levels - minimum high, maximum high, maximum low

and minimum low. For a given logic family, these levels are specified by the

manufacturer to ensure that for a given operating condition, the logic performs correctly

and with a defined noise margin. The levels shown in Figure 3.5 and Figure 3.6 are

scaled relative to a unit amplitude signal. The plots can be appropriately scaled to levels

for a particular logic family, for example, for CMOS operating on a 3.3 V supply, the

unit amplitude corresponds to 3.3 V.

Figure 3.5 2nd-order SRs (positive step) for various damping factors and settling times settle

for

100 MHz.nf

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)

= 0.1 = 0.2 = 0.4 = 0.6 = 0.8

Minimum High Level

Maximum High Level

settle0.2 settle

0.6 settle0.4

Delay for Incident-Wave Switching

settle0.8


Chapter 3 32

Figure 3.6 2nd-order SRs (negative step) for various damping factors for 100 MHz.nf

For many types of signals in high-speed digital systems, the settling time of a PCB

interconnect is an important design consideration. For positive transitions, the settling

time, settle , is the time from the initiation of the step to when the signal at the receiver

input remains above the minimum high threshold and does not drop below the threshold

thereafter. For a negative transition, the settling time is the time from the initiation of

the step to when the signal at the receiver input remains below the maximum low

threshold and does not rise above the threshold thereafter. From Figure 3.5 and Figure

3.6 we see the importance of damping in the system to control overshoot and

undershoot in order to achieve an acceptable settling time. With insufficient damping

the settling time is dominated by the multiple cycles of the ringing in the 2nd-order

response.

For level signals with defined logic levels, although the settling time is important, how

the signal settles to the final value is usually not important; for example, address lines

and data lines on memories or inputs to synchronous finite state machines. However, for

some digital signals, such as clock signals and write signals, the nature of the transition

of the signal to above the minimum high or to below the maximum low is critical to

avoid a transition being interpreted as multiple edges at the receiver. The term incident-

wave switching is often used to describe this type of transition of a waveform at the

0 2 4 6 8 10 12 14 16 18 20-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time t (ns)

Un

it V

olta

ge S

R (

V)

= 0.1 = 0.2 = 0.4 = 0.6 = 0.8

Minimum Low Level

Maximum Low Level

Incident-Wave Switching Times A Settling Time


Chapter 3 33

receiver. That is, on low to high transition the waveform crosses some minimum level

acceptable for a digital HIGH and does not return below for the current upward

transition. Similarly, for a high to low transition, incident-wave switching corresponds

to the waveform crossing some maximum low level acceptable as a digital LOW and

the remains below that level. The minimum HIGH level and maximum LOW level are

chosen to provide the required noise immunity of the system. From Figure 3.5 and

Figure 3.6 it can be seen that for a given value of the critical threshold (low and high)

there is a minimum damping factor required to achieve incident-wave switching. This

minimum value of the damping factor also results in the minimum delay.

From Figure 3.5 and Figure 3.6 we also see that for the lower damping cases, the

MAXIMUM high and MINIMUM low are exceeded which may cause unexpected

behaviour in a circuit. Note that when there is not enough damping (loss) present in the

system, the settling time can be very long indeed, for example 0.2 . With damping

0.35 the settling time will be determined by the first transition of the step.

From the settling time for a 2nd-order SR as shown in Figure 3.5, the damping required

for incident-wave and non-incident-wave switching can be determined. It is shown in

appendix section C.4 that the delay time 2nds s for incident-wave switching for a

critical level thldV is given approximately by

2

2

2 2 12nd

thld 2 22 1

111

1 2 1s

n

eV

e

. (3.14)

Furthermore, we note that 2nds could also mean a settling time.

Figure 3.8 shows the normalised incident-wave switching delay norm s nf for six

different critical threshold values in the range thld 0.7, 0.95V for the damping factor

values in the range 0.1, 0.8 . As can be seen from Figure 3.7 there are tradeoffs to

be considered between the delay and damping. It is also clear that for a threshold level

of around 0.8, the tradeoff is not severe. For practical purposes, a damping factor from

0.4 to 0.8 can provide a good compromise between the delay and excessive ringing.


Chapter 3 34

Figure 3.7 2nd-order SRs and approximate delay times for various damping factors for

100 MHz.nf

Figure 3.8 Normalised delay for various voltage thresholds for the range thld 0.7, 0.95V to represent

damping factors for the range 0.1, 0.8 .

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

Damping Factor (-)

Nor

mal

ised

Del

ay (

-)

Vthld

= 0.70

Vthld

= 0.75

Vthld

= 0.80

Vthld

= 0.85

Vthld

= 0.90

Vthld

= 0.95

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)

= 0.1 = 0.2 = 0.4 = 0.6 = 0.8

Threshold Voltage thldV

2nds


Chapter 3 35

For non-incident-wave switching the settling time depends on the number of times that

the SR traverse the critical threshold and can be determined from

pk 2, for

1n

kt k

, (3.15)

with peak value of

21pk 1 cos , for

k

V e k k

. (3.16)

The expressions (3.15)–(3.16) can readily be obtained from the SR for the underdamped

case given by the single cosine expression [54]

2 1SR 2 2

1 cos 1 tan1 1

nt

n

ev t t

, (3.17)

by noting that for 0,t the absolute value of the peaks of the cosine function of SRv t

in (3.17) occur at multiples of .

For the special matched case presented in subsection 2.4.1, which is for SSD ,CR R the

approximate delay matchs given by (2.9) can be compared with the delay 2nd

s obtained

from the 2nd-order model. Two example plots are given in Figure 3.9 and Figure 3.10,

to show match 2nds s for a threshold chosen to be thld 0.8.V The simulation parameters

are for 10 cml corresponding to a delay 0.6 nsdT for a microstrip with 70 .CR

The other key parameters are shown on the plots.


Chapter 3 36

Figure 3.9 Delay comparisons for thld 0.8V 10 cm, 70 , 10 pF, 0.2 .C Ll R C

Figure 3.10 Delay comparisons for thld 0.8V 10 cm, 70 , 10 pF, 0.7 .C Ll R C

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)

Exact: = 0.72nd-Order: = 0.7Matched: R

SSD = R

C


2nds match

s

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)

Exact: = 0.22nd-Order: = 0.2Matched: R

SSD = R

C


2nds match

s


Chapter 3 37

3.3.3 Effects of the Rise Time for Finite Rise Time Step Input

The effects of rise time on how well the SR of the 2nd-order approximation matches the

SR of the TF given by (2.2) are presented here. The SR of the 2nd-order model and that

of the system with TF given by (2.2) were simulated in OrCAD (PSPICE).

Example plots for the SRs due to a step input with finite rise times 0, 0.5, 1 nsrt are

presented below for a TL with parameters 5, 10, 15 cm,l 70 ,CR 10 pFLC

and 0.2, 0.7 . The corresponding propagation delays of the lines simulated is

0.3, 0.6, 0.9 ns.

The plots showing the results of the simulations are grouped under six different

headings. Groups are for a fixed length and damping factor for the various rise times.

Figure captions marked with red indicate changes in simulation parameters between

consecutive figures. A unified discussion of the results is presented after all the plots.

TL Length of 5 cm, 0.2 Damping Factor

Figure 3.11 2nd-order model in comparison to the lossless TL model for the SR via OrCAD simulations

with a rise time of 0 nsrt for the SSD , 70 , 15 cm 0 pF 0.2, .C LR Cl

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)

2nd-Order: tr = 0 ns

SSD (Lossless TL): tr = 0 ns


Chapter 3 38


with a rise time of 0.5 nsrt for the SSD 5 cm, 70 , 10 pF, 0.2 . C Ll R C


with a rise time of 1 nsrt for the SSD 5 cm, 70 , 10 pF, 0.2 . C Ll R C

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)

2nd-Order: tr = 0.5 ns

SSD (Lossless TL): tr = 0.5 ns


Chapter 3 39


with a rise time of 0 nsrt for the DPD 5 cm, 70 , 10 pF, 0.2 . C Ll R C


with a rise time of 0.5 nsrt for the DPD 5 cm, 70 , 10 pF, 0.2 . C Ll R C

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)


DPD (Lossless TL): tr = 0.5 ns

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)


DPD (Lossless TL): tr = 0 ns


Chapter 3 40





with a rise time of 0 nsrt for the SSD 5 cm, 70 , 10 pF 0.7, .C Ll R C

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 41





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 42





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 43





with a rise time of 0 nsrt for the SSD , 70 , 10 pF, 10 cm 0. .2C LCl R

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 44





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 45





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 46






0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 47





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 48





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 49





with a rise time of 0 nsrt for the SSD , 70 , 10 pF, 15 cm 0. .2C LCl R

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 50





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 51





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 52






0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 53





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 54





0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)




Chapter 3 55



Discussion – Effect of Rise Time

Results for the SR comparing the 2nd-order model and the lossless TL model in OrCAD

have been presented in Figure 3.11 to Figure 3.46 for the SSD and DPD schemes.

Real digital systems have signal transitions that are non-ideal in nature. The

investigation of the SR due to the rise time is important for a number of reasons. First,

SI characteristics are directly affected since the rise time of the input signal changes the

bandwidth of the signal to be transferred. Second, we are able to validate the SRs due to

a non-ideal step input for comparison with the experimental results presented in Chapter

4.

From Figure 3.11 to Figure 3.46, in general, we see that the 2nd-order model tracks the

essential behaviour of the lossless TL model.

The rise time, as mentioned earlier affects the bandwidth of the signal source which also

affects residual energy at the resonances in the exact TFs for SSD and DPD. This is

evident by the ripples added to the basic damped sinusoidal response of a 2nd-order

model as can be seen on the plots. It is also clear from the figures that the SR with a

0 2 4 6 8 10 12 14 16 18 200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time t (ns)

Un

it V

olta

ge S

R (

V)



3.4 Conclusions

Chapter 3 56

non-ideal step input have reduced ripples with increasing damping which is desirable

for achieving good signal quality at the receiver end of the TL.

Key deviations in the transients of the SR depend on the high frequency components in

the signal which in turn depend on the interconnect length. We also see that for the

longest length lines of 15 cm,l the 2nd-order model approximation is poor in

comparison to the TL model because the short line assumption 1 l breaks down.

For the short length lines, for example 5 cm,l the SR agreement is good.

The figures presented also show how the various rise times affect the amplitude and

delay of the signal arriving at the receiver. For the intermediate length line of 10 cml

and above for the DPD, the faster rise time of 0.5 nsrt causes more high frequency

ripples which are undesirable. These ripples can be high enough to extend beyond valid

logic level bands causing erroneous logic interpretations at the receiver.

Figure 3.11, Figure 3.14, Figure 3.17, Figure 3.20, Figure 3.23, Figure 3.26, Figure 3.29

and Figure 3.32, represent SRs for an ideal step input, and are provided for the purpose

of developing an appreciation for the nature of the 2nd-order model in the time domain.

In comparison to the SR plots for non-zero rise times, better agreement can be seen

between the 2nd-order and TL models. The SRs with finite rise times can be used to

validate against the SRs obtained from measurements presented in Chapter 4.

3.4 Conclusions

The characterisation of SI in the frequency and time domain has been achieved. A 2nd-

order framework has been developed for the study of SI-RE. Approximate models for

the 2nd-order system can be utilised in terms of the TF and SR, and give us insight into

the roles of damping. Simple 2nd-order models have been deliberately chosen as they

capture the key signal parameters of the two damping systems.

For short length lines the developed 2nd-order models capture the essential TF and SR

characteristics, but for long lines the short line assumption 1 l breaks down unless

the source signal has low bandwidth. For an SR with a finite rise time input, the rise

time affects the frequency content of the input signal, thereby affecting the SI

characteristics. Furthermore, residual energy at the resonances in the exact TFs for SSD

and DPD are affected by the rise time. The SR with a finite rise time step input has

reduced ripples with increasing damping which is desirable for achieving a good signal

3.4 Conclusions

Chapter 3 57

quality at the receiver end of the TL. Hence, we would expect to have better agreement

when compared with the SR measurement results presented in Chapter 4.

The results presented in this chapter illustrate the importance of using the 2nd-order

model in order to select an appropriate value of damping to achieve SI required for the

delay and to achieve incident-wave switching. It is found that the damping factor from

0.4 to 0.8 can provide a good compromise between the delay and excessive ringing [R-

3].

4.1 Introduction

Chapter 4 58

Chapter 4. SI Validation

4.1 Introduction

Low order models for a point-to-point interconnect suitable for the study of SI have

been developed in Chapter 3. The validation of the 2nd-order models developed in

Chapter 3 is one of the key contributions of the work presented in this thesis. At the core

of this chapter is the validation of the low order models developed in Chapter 3 and

their applicability for the characterisation of the SI of point-to-point PCB interconnects

based on SSD and approximate DPD damping schemes.

The finite source impedance of the driving source has to be taken into consideration in

the experimental design. High frequency sources typically have an output impedance of

50 . This impedance typically does not correspond to the required value of the source

resistance to achieve the desired damping in SSD. An impedance transformation

network needs to be used to transform the source to an equivalent source with the

required resistance. In the case of DPD damping, it is not possible to reduce the source

impedance to zero. It is possible to reduce the source impedance to a sufficiently low

value so that the key features of DPD are still evident. The appropriate 2nd-order model

is the SDD model already presented in Chapter 3.

Another key contribution on validation is the design and setup of the experimental

system. The setup basically consists of a fast edge pulse generator driving the

experimental PCBs in which the SRs are measured with a digitising oscilloscope using a

low capacitance probe. The detailed design considerations of the PCB interconnects and

the system used to obtain the experimental measurements are provided in Appendix D.

With careful modelling and design of the experiment, we are able to obtain repeatable

measurements required for comparison with results predicted by the 2nd-order models

developed in Chapter 3.

This chapter is organised into two sections. The validation results for the SRs are

presented in section 4.2 with relevant discussion. Some conclusions are offered in

section 4.3.

4.2 SI-SR Validation

Chapter 4 59


This section consolidates all the SR validation results for the 70 CR microstrip. The

results compare the SRs from the 2nd-order SR model obtained from OrCAD

simulations and the experiment. A roadmap of the 21 test scenarios is as given in Figure

4.1. SR measurements have been conducted for various microstrip lengths, ,l with

varying damping factor, , and load capacitance, .LC A damping value of 0.5 has

also been included between the low value of 0.2 and the high value of 0.7 to

show an intermediate effect. We also see the data set for the 0.5 (far right), only for

the SSD in Figure 4.1. Hence, the SRs due to a systematic increase in the damping

factors 0.2, 0.5, 0.7 can be compared.

Figure 4.1 A hierarchical tree diagram showing the number of SR measurement data sets.

SR data from the measurements will be obtained for a step input measured to have a rise

time of 662 psrt (see also Figure D.12, p. 141). The same rise time will be used to

generate SRs from the simple 2nd-order model for the validation.

SR Measurement Data

5 cm

0.7 0.2 0.7 0.2 0.5 0.5

10 cm 15 cm

20 pF 10 pF 20 pF 10 pF 20 pF 10 pF 10 pF

SSD SSD DPD SSD SSD

l l l

LC LC LC LC LC LC LC

SDD DPD

SDD DPD

SDD


Chapter 4 60

As will be seen on the plots, the legend entries have self-explanatory annotations. For

example, “Meas” means a measurement curve. Some of the legend labels will indicate

“Scaled” in line with the text description to mean the curve has been scaled using (D.3)

in appendix subsection D.1.2. The reason for the scaling is intentional as will become

apparent in the next subsection.

4.2.1 Validation Results

The experimental validation for the DPD is based on the SDD with the source

impedance designed to be as low as practically possible. Given that high-speed

generators have an impedance of 50 , a high level of reduction of the impedance with

external pads would result in a very small signal hence the impedance cannot be

reduced indefinitely.

The SDD design used in the experimental validation can be considered as an

approximate DPD hence will be referred also as the approximate-DPD. The signal at

the destination measured for the SDD is scaled to allow for the attenuation introduced in

achieving the specified low source impedance. This scaling has been done to simplify

the comparison of the SRs for SSD and the approximate-DPD. Only for Figure 4.2 will

the scaled version and non-scaled version of the measured SR for the approximate-DPD

be shown. The approximate-DPD measured SR waveforms thereafter will show the

scaled version for the validation plots.

The comparisons are broken into several categories, enabling us to see the various

effects, for the following:

4‐A1 Comparison of SSD and Approximate-DPD: The SRs for the SSD and

approximate-DPD are shown in Figure 4.2 to Figure 4.11 for the various line

lengths, damping factors and load capacitances shown in Figure 4.1.

4‐A2 Effect of Load Capacitance: The SRs due to variations in LC are shown in

Figure 4.12 to Figure 4.13 only for the 10 cm line and for a damping factor of 0.5.

4‐A3 Effect of Damping Factor: The SRs due to variations in are shown in

Figure 4.14 only for the 10 cm line and for a load capacitance of 10 pF.

Note that the plots in each category described above are grouped under headings that

allow the group to be easily identified. Figure caption with red marks indicate the

parameter changes. A discussion of the validation results is presented after all the plots.


Chapter 4 61

Comparison: SSD and Approximate-DPD

Figure 4.2 2nd-order and experimental SR validation: SSD and approximate-DPD comparison with

measured step input rise time of 662 ps , 70 , ,5 .cm 10 pF 0.2Lr Cl Ct R


measured step input rise time of 662 ps 5 cm, 70 , 10 pF, .0.7r C Lt l R C

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)

2nd-Order: tr = 662 ps

SSD (Meas)Approximate-DPD (Meas)Approximate-DPD Scaled (Meas)

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)


SSD (Meas)Approximate-DPD Scaled (Meas)


Chapter 4 62


measured step input rise time of 662 ps 5 cm, 7 20 pF 0.0 , , 2 .Lr C Ct l R



0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)



0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)




Chapter 4 63


measured step input rise time of 662 ps , 70 , ,15 cm 10 pF 0.2 .Lr Cl Ct R



0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)



0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)




Chapter 4 64


measured step input rise time of 662 ps 15 cm, 7 20 pF 0.0 , , 2 .Lr C Ct l R



0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)



0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)




Chapter 4 65


measured step input rise time of 662 ps , 70 , ,10 cm 10 pF 0.5 .Lr Cl Ct R


measured step input rise time of 662 ps 10 cm, 7 20 pF0 , , 0.5 .Lr C Ct l R

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)



0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)




Chapter 4 66

Comparison: Load Capacitance Variations

Figure 4.12 2nd-order and experimental SR validation: SSD comparison with measured step input rise

time of 662 ps 10 cm, 70 10, , , 0.5 .20 pFr C Lt l R C

Figure 4.13 2nd-order and experimental SR validation: Approximate-DPD comparison with measured

step input rise time of 662 ps 10 cm, 70 , 10, 20 pF, 0.5 .r C Lt l R C

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)

2nd-Order: tr = 662 ps, C

L = 10 pF


L = 20 pF

Approximate-DPD Scaled (Meas): CL = 10 pF

Approximate-DPD Scaled (Meas): CL = 20 pF

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)


L = 10 pF


L = 20 pF

SSD (Meas): CL = 10 pF

SSD (Meas): CL = 20 pF


Chapter 4 67

Comparison: Damping Factor Variations

Figure 4.14 2nd-order and experimental SR validation: SSD comparison with measured step input rise

time of 662 ps , 70 , 15 cm 10 pF 0.2, 0.5, 0., .7r C LRl Ct

Discussion: Figure 4.2 to Figure 4.14

The SRs from the simple 2nd-order model can be seen to capture the essential

characteristics of the measured SRs. This observation is also seen to be consistent with

the simulation results presented in subsection 3.3.3 on the effect of finite rise/fall times

on the quality of the 2nd-order approximation.

The effects of damping can also be seen in the SR validation results. This confirms the

damping equations given in Table 3.1 and Table 3.2.

As expected, there are also discrepancies between the 2nd-order model and

measurements. Apart from the effects due to the use of a very low order rational TF

model, discrepancies between the model and experimental SR results may also be

attributable to combinations of the following:

4‐B1 Non-linear behaviour of the voltage step input from the pulse generator.

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time t (ns)

Vol

tage

SR

(V

)

2nd-Order: tr = 662 ps, = 0.2

2nd-Order: tr = 662 ps, = 0.5

2nd-Order: tr = 662 ps, = 0.7

SSD (Meas): = 0.2SSD (Meas): = 0.5SSD (Meas): = 0.7


Chapter 4 68

4‐B2 The parasitics as described in subsection 2.4.2, for example, the connecting

route traces and vias of the actual PCB layout unaccounted for in the model.

4‐B3 Tolerances of the SMD component values, PCB manufacturing and

measurement system.

We also see the differences in the shift in the oscillations comparing the SRs. The shift

is likely due to the unaccounted-for short connecting traces as shown in Figure 2.9 on

the PCB layout that can be considered as additional parasitics to the microstrip trace.

From the figures, the SR for the DPD and SDD are approximately the same, which

shows that the SDD can be used to predict the behaviour of the ideal DPD termination

scheme. The SI performance comparisons between the SSD and DPD, can hence be

made.

Also, there is a better agreement between the SR results comparing the model to the

measurements for short TL lengths because the 1l assumption is better satisfied.

We see that for the longer lines, for example 15 cm, the short line assumption begins to

break down.

The discussions given above are general observations. For the various plot categories,

more specific observations can be made for the following:

4‐C1 Figure 4.2 to Figure 4.11: The comparison for the 5 cm SRs for the model

and experiment shows good agreement. However, for 15 cm, the model assumption

begins to break down. Comparing SSD and approximate-DPD shows that both

termination schemes have been designed with approximately equal damping factors.

We also see the effect of the damping on the SRs causing a reduction in the ringing

amplitude. With increasing damping the high frequency deviations seen on the SRs

are reduced. This observation is also evident for the approximate-DPD for the long

line of 15 cm. For the SSD, the reduced deviations can be seen from the envelope-

bound in section 3.2.

4‐C2 Figure 4.12 to Figure 4.13: As the load capacitance increases, the rise time

also increases. The slowing down in the transition is captured by the 2nd-order

model and experiment.

4.3 Conclusion

Chapter 4 69

4‐C3 Figure 4.14: We see the effect of the various damping factors from 0.2 to

0.7. We see that increasing the damping reduces the ringing. The high frequency

effects causing the non-linear behaviour are also reduced. As damping increases, the

SR waveforms resemble a decaying sinusoid settling to a steady-state value. Also,

note the reasonable agreement between the model and experiment around the first

voltage peak. Although the SR validation for the 15 cm is inferior to the 5 cm line,

the role of the damping terminations to improve SI is still applicable for long lines.

It is clear from the SR results that the 2nd-order model framework is indeed very useful

to study the effects of damping. Under approximately equal SR for a fixed damping

factor for the SSD and DPD, we are now able to undertake a legitimate RE performance

characterisation in Chapter 5 and RE validation in Chapter 6.

4.3 Conclusion

The simple 2nd-order model developed in Chapter 3 has been validated by experimental

results. The model and measurements exhibit good SR agreement, in the context of

capturing the essential waveform behaviour. Thus, the 2nd-order models can be used to

design point-to-point interconnects that achieve desired SI characteristics by controlling

the damping for a given line characteristics and capacitive load.

5.1 Introduction

Chapter 5 70

Chapter 5. RE Modelling

5.1 Introduction

The modelling and validation for SI characterisation, which constitute contributions of

this thesis, has been presented in Chapter 3 and Chapter 4 respectively. This chapter is

concerned with the development of an RE model that is shown to be very useful for the

characterisation and prediction of the RE performance of SSD and DPD under

approximately equal SI conditions. In this chapter, the RE model referred to henceforth

as the RE-approximation model is compared to FEKO modelling based on the method

of moments (MoM). The important validation of the RE-approximation model against

experimental measurements is presented in Chapter 6.

A number of approaches can be used to obtain the RE for a microstrip point-to-point

interconnect. The RE for the microstrip can be computed using the full-wave method,

analytical method, circuit method, and the electromagnetic topology method based on

tensor analysis of the network and the co-modelling of electromagnetic circuits [39]. In

this thesis, an analytical method has been chosen to develop the RE-approximation

model for the electric far-field region of a microstrip interconnect. The RE model is

computationally efficient as well as suitable for RE analysis for the SSD and DPD.

Elements of the work presented in this chapter on RE modelling have been published by

the author in [R-1] and [R-3]. The analytical model based on TL currents presented by

the author in [R-1] is used to predict the RE from the two damping schemes of specific

interest in this thesis, namely SSD and DPD. The analytical model developed can also

be used to study more readily the effect of interconnect losses compared to other known

methods presented in [39], [40], [42]–[43] and references therein.

Out of the approaches referenced in [39], the two analytical approaches described in

[40] and [43] have been found to be most relevant for the study of the impact of

damping on RE. However, the RE models arising from these approaches have been

found to be suitable only for practical line length of interest provided that the losses,

such as that due to the skin effect and dielectric are not significant. Results published by

the author in [R-1]–[R-2] shows that for a 10 cm line, the dielectric loss cannot be

neglected. The RE-approximation model has been developed in this thesis for the

5.2 RE-Approximation Modelling

Chapter 5 71

consideration of loss mechanisms on REs.

Several test cases are provided in this chapter for the study of the RE performance of

SSD and DPD. The cases include microstrip interconnects driven by a trapezoidal pulse

with finite rise/fall times in order to determine the impact of finite rise and fall times on

RE.

This chapter is organised into three main sections. Section 5.2 formulates the modelling

of the RE for microstrip interconnects, and summarises the key assumptions and the

resulting model equations for the RE. The detailed derivations are provided in Appendix

E. Section 5.3 presents the FEKO modelling and RE results compared to the RE model.

Section 5.4 presents several RE performance plots for comparing the two damping

schemes with a trapezoidal excitation. Some conclusions are offered in section 5.5.


In order to characterise the RE performance of the damping schemes for a range of

interconnect lengths, damping, source and line parameters, an RE model for the

microstrip structure illustrated in Figure 5.1 has been developed.

Figure 5.1 PCB microstrip trace model for the RE modelling.

Figure 5.1 shows both the physical system and electrical system for the RE formulation.

The physical system is the microstrip with physical parameters such as the trace width,

,w dielectric height, h and dielectric relative permittivity, .r The electrical system

representation for the microstrip is modelled as a TL with electrical parameters

described in subsection 2.3.1. Hence, the microstrip TL will be a function of the

z

x, CZ

SZ

SV

E 0 0 0 0, , ,c

r

O

w

h

l

r

lossyI

LZ


Chapter 5 72

physical parameters defined by the characteristic impedance, ,CZ and propagation

constant, . In free-space, permittivity, 0 , and permeability, 0 , defines the wave

number, 0 0= 2 ,f c in which 0 0 0=1c [14]. The electric field, ˆ ,E is a function

of the physical and electrical parameters as well the spatial parameters defined by the

spherical coordinate system, , , ,r in Figure 5.1.

5.2.1 Modelling Approach

To obtain the RE for a microstrip PCB, several factors such as currents, losses,

parasitics and source spectrum, need to be considered.

The modelling approach to obtain the RE for the microstrip structure shown in Figure

5.1 can be based on the TL currents presented in subsection 2.4.3. Once the current

distribution lossyI is known, the RE can be obtained since the electric field is a function

of the currents.

The current-to-field contributions due to the microstrip, assuming the quasi-TEM mode

propagation, can be illustrated as shown in Figure 5.2.

Figure 5.2 Current-to-field contributions.

Obtaining the field from the differential and end currents is a matter of using Hertzian

dipoles [14]. For the polarisation currents, the waves in the dielectric medium have a

different propagation constant compared to the free-space wave 0. It is possible to

obtain ˆ PE using the result for transforming the polarisation current, polˆ ,I from the

dielectric to free-space, which is given by the relation (2.12). Hence, the total electric

far-field can be found for the microstrip with field contributions from the dielectric, and

not just from the current loop, which would be inadequate for RE prediction.

Polarisation Currents Differential Currents

lossyI x

lossyˆI x

End Currents

lossyˆ 0I lossyI l

polI x

ˆ LE ˆ EE ˆ PE


Chapter 5 73

Apart from the modelling of the current-to-field contributions, losses on the microstrip

and parasitics have to be considered to achieve good RE prediction. For short microstrip

interconnections of TL lengths satisfying the condition 1,l the TL losses can often

be regarded as small. While short TL losses have low impact on SI, disregarding

dominant microstrip loss contributions can severely impact the RE prediction as has

been found in [R-1]–[R-2]. In addition, when comparing with the FEKO model, the port

parasitics cannot be neglected and must be taken into account in the modelling. These

port parasitics can be modelled as a series inductance as shown in Figure 2.11.

The development of an RE model that works well for a digital signal transferred over

the interconnect is an important consideration in the modelling. The digital signal can be

modelled as a periodic trapezoidal pulse with finite rise/fall times. This model gives us

insight into the behaviour of the RE due to a more realistic digital input signal, for

example, a clock signal with finite rise and fall times, and hence finite bandwidth.

It is also important to be able to gauge the maximum RE due the input signal. For the

microstrip shown in Figure 5.1, the maximum field is located at 2 and 0,

[40]. Note that the maximum field only applies to the 1l assumption which is also

used to develop the TF approximations for SI. For a more accurate prediction, one

would scan the upper half space with an algorithm to locate the maximum fields. It

should be noted that further investigations have been conducted to obtain an analytical

expression for the maximum electric far-field [6], [10]. At this juncture, no simple

expression can yet be found other than the expression presented in [40] for matched

terminations. For the study on damping, we rely on the field points given in [40] to

estimate the maximum field in the RE-approximation model.

5.2.2 Assumptions and Limitations

Several key assumptions are required for the derivation of the RE-approximation model

presented in Appendix E. These assumptions are shown below:

5‐A1 The microstrip is assumed to have zero trace thickness with cross-sectional

dimensions considered as small in comparison to the wavelength, for example,

0 1h and 0 1.w Hence TL currents given by (2.11a) can be used. Moreover,

the approximation given by (2.12) assumes that the polarisation current is mainly

concentrated within a few trace widths and may be modelled as a Hertzian dipole


Chapter 5 74

moment [41].

5‐A2 Only the 1 r terms for the Hertzian dipole equations in [14] are used in the

far-field 0 1 .r

5‐A3 Parallel rays are assumed. For example, all rays going from current segments

on structure to observation point are assumed to be parallel for evaluating phase

retardation, and of the same length for obtaining amplitudes.

5‐A4 The microstrip’s reference plane also referred to as the ground plane is

assumed to be infinite so that the method of images theory can be applied [14]. The

ground plane is also assumed to be a perfect electric conductor (PEC) and is

synonymous with the classical Sommerfeld half-space problem for obtaining a

simplified RE model [17].

5‐A5 The microstrip satisfies the quasi-TEM assumption which has been used for

the TL model in subsection 2.3.1.

The assumptions stated above are in addition to the assumptions mentioned in Chapter

2. For the quasi-TEM assumption 5-A5, a practical frequency limit can be

approximated by ,statgf given in [40]–[44] as

6

,stat

21.3 10

2 1

g

r

fw h

. (3.18)

Equation (3.18) defines an approximate upper frequency limit before the RE-

approximation begins to break down. It has been found that the RE-approximation

model is a good RE predictor for the microstrip even beyond ,stat .gf

In general, the RE-approximation model is limited to interconnects with thin trace

dimensions and short dielectric height to several millimetres, for frequencies of practical

interest.

5.2.3 Derivation of Results

The detailed derivation of the RE model referred to as the RE-approximation can be

found in Appendix E using the assumptions 5-A1–5-A5. The author’s work on RE

modelling [2], [9], [R-1] and [P-2], has produced a number of different forms for the

model equations that predict the RE for microstrip interconnects. The equations that

result from the derivation in Appendix E are summarised in Table 5.1. These equations


Chapter 5 75

which are in terms of the reflection coefficients at source and destination ends of the TL

using the compact notation ,S L have been proven to be useful for the analysis of the

RE performance of SSD and DPD.

Description RE-Approximation in the Reflection Coefficient Representation

End Segments Field

00 0

2

2

ˆsinˆ2 1

1 1 x

j rE

lS L

jk llL L

h IeE j

r e

e e

(5.1)

Polarisation Current Field

00 0

2

2

ˆsin 1ˆ 12 1

1 1x x

j rP

lr S L

jk l jk lj l

Lx x

h IeE j

r e

e ee

jk jk

(5.2)

00 0 0

2

2

ˆcos sin cos cosˆ2 1

1 1x x

j rL

lS L

jk l jk ll

Lx x

h IeE

r e

e ee

jk jk

(5.3a)

Differential Line Current Field

00 0 0

2

2

ˆsin cos sinˆ2 1

1 1x x

j rL

lS L

jk l jk lj l

Lx x

h IeE

r e

e ee

jk jk

(5.3b)

Source Current 0

ˆˆ S

S C

VI

Z Z

(5.4)

Voltage Reflection Coefficient

,,

,

S L CS L

S L C

Z Z

Z Z

(5.5)

00 0

2 f

c c

(5.6a)

eff0 r (5.6b)Wave Constants

0 sin cos xk (5.6c)

Total Field (Magnitude)

2 2ˆ ˆ ˆ ˆ ˆ , for 0 , 0 22 E P L LE E E E E (5.7)

Table 5.1 A summary of the RE model in the form using the reflection coefficients.

5.3 FEKO RE Modelling and Comparison

Chapter 5 76

The RE-approximation model can be compared with the RE model in [40], referred to

here as the “Leone RE” model. It is shown in appendix section E.3 that for a lossless

line, that is 0, and 0 1h both the RE-approximation model and Leone RE model

yield the same electric field.

An RE comparison plot is given as shown in Figure 5.3 using simulation parameters

taken from [40]. In order to make the comparison, the RE-approximation model must be

considered lossless since the Leone RE model has been derived from a lossless TL

model. The major difference between the two RE models described is that the RE-

approximation model have the capability to effectively study TL losses. As can be seen

from the figure, the curves from both models coincide. For practical traces, either model

can be used but when the loss mechanisms dominate such as those due to the dielectric,

skin effect, etc, their effect have to be considered using the appropriate model.

Figure 5.3 RE model comparisons at , , 3 m, 0, 0o r oP A A A P

10.16 cm, 84 , 4.6 .C rl R


Many electromagnetics software tools and packages listed in appendix section A.6, and

such as described in [61]–[62] and [66], can be used to model the microstrip structure

0 100 200 300 400 500 600 700 800 900 1000-40

-20

0

20

40

60

80

Frequency f (MHz)

Ele

ctri

c F

ield

Mag

nitu

de |Ê

| (d

BV

/m)

RE-Approximation Model ( = 0)Leone RE Model


Chapter 5 77

shown in Figure 5.1 in order to study the RE from the two damping schemes. Each tool

will have its own modelling environment for the user to work with, such as a graphical

user interface, libraries, electromagnetic-engine, etc. The 3D-electromagnetic graphical

modelling software package FEKO, based on the MoM code, has been chosen for the

work in this thesis.

A number of microstrip models have been developed in FEKO. Only the simplest

model, as shown in Figure 5.4, is chosen to simulate the RE for comparison with results

from the RE-approximation model.

Figure 5.4 The FEKO model.

Upper Air-Filled Half Space

Added Symmetry Plane to Speed up

Computation

3D Pattern from Hemisphere Shell

FR-4 4.5, tan 0.02r Infinite Substrate with PEC Ground

0max

max

Meshing at 2 GHz 15

dd

r

cf

f

PEC Trace Length l

Source Port

Load Port Load Termination

Substrate Height h

Source Voltage Source Termination

Trace Width w


Chapter 5 78

Some important factors encountered in the FEKO modelling are as follows:

5‐B1 The MoM meshing affects the computational time as well as the accuracy of

the solution generation. With the FEKO model, various types of meshing, from

coarse to very fine, have been investigated. A meshing size of 15d has been

chosen given the maximum frequency of interest max .f This meshing size gives fast

computational speed and the required accuracy.

5‐B2 The source and load end ports of the microstrip are defined to be wire ports.

Voltage excitation and terminal networks are attached to the respective ports. The

wire ports are assumed to approximate the vias of the actual microstrip PCBs. Note

that the port definition can sometimes be ill-defined in FEKO. For the microstrip

structure, wire ports are assumed which is adequate for use in the modelling.

5‐B3 The FEKO model allows for the CAD-drawn structure to be defined in terms

of variables that can be used to change the microstrip’s trace dimensions, dielectric

height, terminal networks, etc. This is very useful so that the various parameter

changes can be conducted readily without having to recreate a new FEKO model.

Comparison of RE-Approximation Model and FEKO Simulation

Three plots are given below for comparing between the RE-approximation and the

FEKO model which would also include losses. RE comparison plots will be given to

show the effect with and without the addition of losses in the RE-approximation model.

A forward transmission gain, 21 ,S is shown in Figure 5.5 to gain confidence in the

developed FEKO model. The forward transmission gain is for the source end and load

end of the TL terminated with a matched characteristic impedance

70 .C S L CZ Z Z R It is clear that 21S can be considered reasonably flat

over the frequency range of interest and the TL has the desired characteristic impedance

designed to be approximately 70 .CR Figure 5.6 to Figure 5.9 are chosen test cases

for the RE comparison between the RE model and the FEKO model. The field

conversion given in appendix section B.5 is particularly useful for converting FEKO

data for the RE comparison plots.


Chapter 5 79

Figure 5.5 21S forward transmission gain with ports matched to 70 . S L CZ Z R

The simulation parameters for Figure 5.6 to Figure 5.9 are shown on the figure

descriptions. Simulations have been conducted for a microstrip with 10 cml and a

one-way TL delay of 0.6 nsdT [R-1]. For the simulation, the damping resistances

SSD 14, 48.9 R and DPD 162, 46.3 R can be computed from (3.4)–(3.5) for

0.2, 0.7 . Given that the FEKO model has wire ports, the inductance

wire 0.4 nHsL is added in series to the source and also to the load end termination of the

RE-approximation model to account for the port parasitics [R-1]–[R-2]. Furthermore,

the observation point is chosen to be at an arbitrary spatial location

, , 3 m, 0, 0 ,o r oP A A A P which is close to the theoretical direction of maximum

field.

It is clear from Figure 5.6 to Figure 5.9 that there is strong agreement between the

FEKO and the RE models. The agreement occurs when the dielectric loss and the wire

inductances due to the FEKO ports have been considered in the RE-approximation

modelling. Note that the curves represented by Lossless TL as indicated on the legend

text refer to the RE-approximation with 0. Curves represented by Lossless TL refer

to the RE-approximation with loss that is 0. Further, note that the microstrip trace

in the FEKO model shown in Figure 5.4 is PEC (i.e. infinite conductivity) which means

that there is no skin effect loss included.

30 100 1000 20000.9

0.92

0.94

0.96

0.98

1

1.02

1.04

1.06

1.08

1.1

Frequency (f/MHz)

Gai

n M

agni

tude

| S 21

| (-)

Matched: IdealMatched: FEKO


Chapter 5 80

Figure 5.6 RE-approximation and FEKO RE comparison: SSD comparisons with a source excitation of

ˆ 1 V 10 cm, 70 , 10 pF, 0.2 . S C LV l R C

Figure 5.7 RE-approximation and FEKO RE comparison: DPD comparisons with a source excitation of

ˆ 1 V 10 cm, 70 , 10 pF, 0.2 . S C LV l R C

30 100 1000 20000

10

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Frequency ( f/MHz)

Ele

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Mag

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RE-Approximation (DPD): Lossless TLRE-Approximation (DPD): Lossy TLFEKO (DPD)

30 100 1000 20000

10

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/m)

RE-Approximation (SSD): Lossless TLRE-Approximation (SSD): Lossy TLFEKO (SSD)


Chapter 5 81

Figure 5.8 RE-approximation and FEKO RE comparison: SSD comparisons with a source excitation of

ˆ 1 V 10 cm, 70 , 10 pF, 0.7 . S C LV l R C

Figure 5.9 RE-approximation and FEKO RE comparison: DPD comparisons with a source excitation of

ˆ 1 V 10 cm, 70 , 10 pF, 0.7 . S C LV l R C

30 100 1000 20000

10

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Frequency ( f/MHz)

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/m)

RE-Approximation (DPD): Lossless TLRE-Approximation (DPD): Lossy TLFEKO (DPD)

30 100 1000 20000

10

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RE-Approximation (SSD): Lossless TLRE-Approximation (SSD): Lossy TLFEKO (SSD)

5.4 Characterisation of RE with Finite Bandwidth Source

Chapter 5 82

When we have a microstrip structure of large extent, then it is important to not neglect

the dielectric loss. The traces, usually made of copper, have losses that can be neglected

but only when the microstrip PCB structure is small compared to the wavelength. At

frequencies well into the GHz range, more loss mechanisms such as those due to skin

effect, dispersion, radiation losses, etc have to be taken into consideration in the

modelling. Moreover, the modelling of the loss shows us the versatility of using an

analytically based approach in which we are able to integrate various sub-models to

study key parameters of interest in the RE model.


An important consideration in the characterisation is the RE due to a trapezoidal pulse

train excitation to approximately model a more realistic digital signal in practice. We

are able to see the effects of the envelope-bound due to the rise/fall times and pulse

duration on the RE. The method for characterising the RE performance presented in [R-

3] is described in this section.

A periodic trapezoidal pulse oscillating at a frequency oscf with period T will have an

envelope spectrum with two break points at 1 and 1 rt as shown in Figure

5.10. The pulse width is defined at 50 % of the amplitude SV A and rt is the rise

time which is also equal to the fall time .ft The envelope spectrum from the pulse train

exhibits -20 dB dec at 1 and -40 dB dec beyond 1 .rt In the dB scale for the

amplitude, the envelope is used to scale the magnitude of the RE transfer characteristic

over a specified frequency range of interest.

Figure 5.10 Trapezoidal pulse train and its envelope spectrum.

Trt ft

A

2A

t

SV t

f1

1

rt

0 dB dec

20 dB dec

40 dB dec

A


Chapter 5 83

A legitimate comparison of the RE performance comparison of SSD and DPD can be

made under the condition that both have the same 2nd-order model and hence SI

performance. Further, the assumption of a trapezoidal source with finite rise/fall time

makes the comparison more practically useful.

5.4.1 Results: RE Performance Studies for the SSD and DPD

The RE results generated are for the microstrip with characteristic impedance

70 ,C CZ R lengths 5, 15 cm,l damping factors 0.2, 0.7 and load

capacitance 10 pF.LC Note that the choice of performance study test cases is only a

subset of that studied in [9]. Here, we only compare the RE performance due to a low

damping factor and high damping factor value for the choice of TL lengths.

The RE case studies for the trapezoidal pulse also considers the 0.67 nsr ft t

scenario which represents the maximum rise time from the generator for the SR

experiment. We are able to gain some insights into the RE from the SR validation.

For the RE performance comparison between the SSD and DPD termination schemes,

the RE-approximation model is used to predict the REs. The prediction model is

considered to be lossless 0 so that the maximum REs can be predicted using field

locations from [40].

Furthermore, the amplitude of the trapezoidal pulse train is assumed to have amplitude

1 V,A a frequency of osc 250 MHzf (i.e. 61 250 10 ) and equal rise/fall

times 0.1, 0.67 ns.r ft t The frequency range of interest is taken from

30, 2000 MHz.f Also, the observation point is taken at an observation in spherical

coordinates , , 3 m, 2, 0o r oP A A A P in which the maximum field is located.

The RE results are plotted as shown in Figure 5.11 to Figure 5.14, below.


Chapter 5 84

Figure 5.11 RE performance case study: SSD and DPD comparison with a trapezoidal pulse oscillating

at osc 250 MHz 5 cm, 70 , 10 pF, 0.2 . C Lf l R C



30 100 1000 20000

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Frequency (f/MHz)

Ele

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Mag

nitu

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| (d

BV

/m)

SSD: UnweightedSSD: t

r = t

f = 0.1 ns

SSD: tr = t

f = 0.67 ns

DPD: UnweightedDPD: t

r = t

f = 0.1 ns

DPD: tr = t

f = 0.67 ns

-20 dB/dec: 1/()-40 dB/dec: 1/(t

r)

30 100 1000 20000

20

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60

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100

120

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Ele

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Mag

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/m)


r = t

f = 0.1 ns

SSD: tr = t

f = 0.67 ns


r = t

f = 0.1 ns

DPD: tr = t

f = 0.67 ns

-20 dB/dec: 1/()-40 dB/dec: 1/(t

r)


Chapter 5 85





30 100 1000 20000

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Ele

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Mag

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| (d

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/m)


r = t

f = 0.1 ns

SSD: tr = t

f = 0.67 ns


r = t

f = 0.1 ns

DPD: tr = t

f = 0.67 ns

-20 dB/dec: 1/()-40 dB/dec: 1/(t

r)

30 100 1000 20000

20

40

60

80

100

120

Frequency (f/MHz)

Ele

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c F

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Mag

nitu

de |Ê

| (d

BV

/m)


r = t

f = 0.1 ns

SSD: tr = t

f = 0.67 ns


r = t

f = 0.1 ns

DPD: tr = t

f = 0.67 ns

-20 dB/dec: 1/()-40 dB/dec: 1/(t

r)

5.5 Conclusion

Chapter 5 86

5.4.2 Discussion

From the plots, the following are also observed:

5‐C1 The RE results plotted in Figure 5.11 to Figure 5.14 shows that the RE for the

SSD, in general, outperforms the RE for the DPD. This observation is no surprise

because the current for the DPD is higher than the SSD. Since the electric field is

proportional to the current, one would expect a higher RE for the DPD.

5‐C2 At the resonances, the REs for the SSD are significantly lower than the DPD

under approximately equal SI conditions. Indeed, for a range of practically useful

damping factors, SSD shows virtually no resonance peaks in the RE curves. At the

resonances, the DPD scheme has peaks higher than the SSD because the SSD’s TF

is bounded by the envelope which naturally reduces the high order peaks.

5‐C3 From Figure 5.11 to Figure 5.14, there are frequency ranges in which the RE

for the DPD outperforms the SSD. In the low frequency range, the RE for the SSD

may be higher than the RE for the DPD for low damping values. It is interesting to

note that introducing loss (damping) in low frequency systems with low-loss lines

can achieve lower RE as seen from the DPD curves. At low frequencies using the

DPD scheme, which can support high capacitive loading, is beneficial.

5‐C4 Controlling the high frequency REs from a trapezoidal pulse is a function of

the pulse period and transition times rt and .ft A smaller rise/fall time pulse will

have higher frequency content. Hence, the RE is not reduced as much from the

1 rt break point onwards. Nevertheless, the RE for the SSD scheme is relatively

insensitive to the interconnect length. For the DPD scheme, the smaller the rise/fall

time is the higher the peak values of RE are.

5.5 Conclusion

Numerical simulations indicate a very strong agreement between the RE-approximation

model with added dielectric loss and the FEKO model with PEC conductors.

Additionally, the agreement is also attributed to modelling of the wire ports of the

FEKO model in the RE-approximation model.

5.5 Conclusion

Chapter 5 87

The RE performance evaluation for low 0.2 and high 0.7 damping factors

for short 5 cml and long 15 cml lines shows that the SSD generally

outperforms the DPD. Although the RE performance of the SSD is seen to be the better

than the DPD, at frequencies where the REs are comparable, either termination scheme

can be used, provided that the SI requirements are met in the design of high-speed

digital systems.

6.1 Introduction

Chapter 6 88

Chapter 6. RE Validation

6.1 Introduction

An analytically based RE model and a FEKO simulation model have been developed in

Chapter 5. The experimental RE validation presented in this chapter forms the final

component of the research work on SI-RE. The key contributions of this chapter are the

design of RE validation experiments, their execution and the critical evaluation of the

experimental results obtained.

Conducting RE measurements of the electric field requires at least the same attention to

the detailed design of the experimental setup as for the SI measurements. Simulation

models using the FEKO software package and the experience from experimental work

conducted for the author’s Master’s thesis, [P-1], provided insights to improve the

quality of the results that can be obtained from RE experiments on interconnects that

use SSD and DPD.

Another key consideration in the RE validation experiments is the calibration procedure.

Calibration of the spectrum analyser and all cables used has to be considered. The effect

of the antenna factor also needs to be considered in the calibration procedure. All details

of the experimental setup and the calibration procedure can be found in Appendix F.

This chapter is organised into two sections. The validation results for the REs are

presented in section 6.2 including a critical evaluation of the experimental results and

their relation to the results predict by the RE-approximation model. Some conclusions

are offered in section 6.3.

6.2 RE Validation

Similar to the SI validation, this section serves to consolidate all the RE validation

results for the 70 CR microstrip. The results compare the REs from the RE model

obtained from Table 5.1 and the experiment. A roadmap of the 21 test scenarios is

shown in Figure 6.1. RE measurements have been conducted for various microstrip

lengths, ,l with varying damping factor, , and load capacitance, .LC A damping value

of 0.5 has also been included between the low value of 0.2 and the high value

of 0.7 to show an intermediate effect. Again we also see the data set for the

6.2 RE Validation

Chapter 6 89

0.5 (far right), only for the SSD in Figure 6.1. Hence, the REs due to a systematic

increase in the damping factors 0.2, 0.5, 0.7 can be compared.

Figure 6.1 A hierarchical tree diagram showing the number of RE measurement data sets.

As will be seen on the plots, the legend entries have self-explanatory annotations.

“Comp Meas” means a compensated measurement curve. It means that the RE

validation results obtained from the experiment have been compensated (comp) by the

loop calibration from the test setup as documented in appendix subsection F.2.3.

6.2.1 Validation Results

Electric field validation results have been taken for the vertical field ˆzE because the

receiving antenna for the measurement is in the vertical polarisation. In the horizontal

polarisation, the electric field is small and hence may be neglected. Moreover,

measurement of only the larger vertical field has been done to speed up the

measurement process given the number of microstrip boards to be measured.

The same microstrip test boards have been used for both the RE and SI validation

RE Measurement Data

5 cm

0.7 0.2 0.7 0.2 0.5 0.5

10 cm 15 cm

20 pF 10 pF 20 pF 10 pF 20 pF 10 pF 10 pF

SSD SSD DPD SSD SSD

l l l

LC LC LC LC LC LC LC

SDD DPD

SDD DPD

SDD

6.2 RE Validation

Chapter 6 90

experiments. This means that, as for the SI validation experiments, the DPD boards are

approximate-DPDs, since the source has a very small but finite impedance.

The comparisons are broken into several categories, enabling us to see a variety of

effects:

6‐A1 Comparison of SSD and Approximate-DPD: The REs for the approximate-

DPD as shown in Figure 6.2 to Figure 6.11 for the various line lengths, damping

factors and load capacitances shown in Figure 4.1.

6‐A2 Effect of Load Capacitance: The REs due to variations in LC as shown in

Figure 6.12 to Figure 6.13 only for the 10 cm line and for a damping factor of 0.5.

6‐A3 Effect of Damping Factor: The REs due to variations in as shown in

Figure 6.14 only for the 10 cm line and for a load capacitance of 10 pF.

Note that the plots in each category described above are grouped under headings that

allow the group to be easily identified. Figure caption with red marks indicate the

parameter changes. A discussion of the validation results is presented after all the plots.

Comparison: SSD and Approximate-DPD

Figure 6.2 RE-approximation and experimental RE validation: SSD and approximate-DPD comparison

at observation 5, , 2.6, 0, 1.5 m , 70 , , cm .10 pF 0.2o o C Lx y zP A A A P CRl

0 100 200 300 400 500 600 700 800 9000

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|Êz| (

dBV

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RE-Approximation (SSD)RE-Approximation (Approximate-DPD)SSD (Comp Meas)Approximate-DPD (Comp Meas)

6.2 RE Validation

Chapter 6 91


at observation , , 2.6, 0, 1.5 m 5 cm, 70 , 10 pF 0.7, .o x y z o C LP A A A P l R C


at observation , , 2.6, 0, 1.5 m 5 cm, 70 20 pF 0.2, , .o x y z o C LP A A A P l R C

0 100 200 300 400 500 600 700 800 9000

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6.2 RE Validation

Chapter 6 92


at observation , , 2.6, 0, 1.5 m 5 cm, 70 , 20 pF 0.7, .o x y z o C LP A A A P l R C


at observation 15, , 2.6, 0, 1.5 m cm 10 , 70 , pF 0.2, .o Lx y z o ClP A A A CP R

0 100 200 300 400 500 600 700 800 9000

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6.2 RE Validation

Chapter 6 93


at observation , , 2.6, 0, 1.5 m 15 cm, 70 , 10 pF, . .0 7o x y z o C LP A A A P l R C


at observation , , 2.6, 0, 1.5 m 15 cm, 70 20 pF 0.2, , .o x y o Lz CP A A A P l R C

0 100 200 300 400 500 600 700 800 9000

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6.2 RE Validation

Chapter 6 94


at observation , , 2.6, 0, 1.5 m 15 cm, 70 , 20 pF, . .0 7o x y z o C LP A A A P l R C


at observation 10, , 2.6, 0, 1.5 m cm 10 , 70 , pF 0.5, .o Lx y z o ClP A A A CP R

0 100 200 300 400 500 600 700 800 9000

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6.2 RE Validation

Chapter 6 95


at observation , , 2.6, 0, 1.5 m 10 cm, 70 20 , , 0.5 .pFo x y o Lz CP A A A P l R C

Comparison: Load Capacitance Variations

Figure 6.12 RE-approximation and experimental RE validation: SSD comparison at observation

, , 2.6, 0, 1.5 m 10 cm, 70 , 10, p 2 F, 0.5 .0o x o Ly z C CP A A A P l R

0 100 200 300 400 500 600 700 800 9000

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RE-Approximation (SSD): CL = 10 pF

RE-Approximation (SSD): CL = 20 pF

SSD (Comp Meas): CL = 10 pF

SSD (Comp Meas): CL = 20 pF

0 100 200 300 400 500 600 700 800 9000

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6.2 RE Validation

Chapter 6 96

Figure 6.13 RE-approximation and experimental RE validation: Approximate-DPD comparison at

observation , , 2.6, 0, 1.5 m 10 cm, 70 , 10, 20 pF, 0.5 .o x y z o C LP A A A P l R C

Comparison: Damping Factor Variations

Figure 6.14 RE-approximation and experimental RE validation: SSD comparison at observation

, , 2.6, 0, 1.5 m , 70 , , .15 cm 10 pF 0.2, 0.5, 0.7o x y z o C LP A A A lP R C

0 100 200 300 400 500 600 700 800 9000

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RE-Approximation (Approximate-DPD): CL = 10 pF

RE-Approximation (Approximate-DPD): CL = 20 pF

Approximate-DPD (Comp Meas): CL = 10 pF

Approximate-DPD (Comp Meas): CL = 20 pF

0 100 200 300 400 500 600 700 800 9000

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RE-Approximation (SSD): = 0.2RE-Approximation (SSD): = 0.5RE-Approximation (SSD): = 0.7SSD (Comp Meas): = 0.2SSD (Comp Meas): = 0.5SSD (Comp Meas): = 0.7

6.2 RE Validation

Chapter 6 97

Discussion: Figure 6.2 to Figure 6.14

The REs from the RE model can be seen to capture the essential characteristics of the

measured REs. This observation confirms that the experimental setup is valid for

yielding good repeatable results. Moreover, the calibration routine presented in

appendix section F.2 can be considered to be a reliable method for reducing the

measurement uncertainties.

The effects of damping can also be seen in the RE validation results. This not only

confirms that the damping resistors have been correctly realised on the microstrip test

boards but that the RE for the SSD and DPD is a function proportional to the current

distribution. Since the peak transient current for the DPD is greater than the SSD (see

also subsection 3.3.1, pp. 130–31), in general, we see the lower RE for SSD compared

to the DPD.

Also, from the RE validation results, we see that the REs give strong agreement

between the model and the measurements, even for the longer line length of 15 cm.

Unlike the SI validation results, more effects have been considered in the RE modelling

such as the TL current model to include loss contributions from the dielectric.

As expected there are also discrepancies between the RE model and measurements. The

discrepancies between the model and experimental RE results may also be attributable

to combinations of the following:

6‐B1 Connecting route traces and vias of the actual PCB layout unaccounted for in

the RE modelling as additional parasitics.

6‐B2 The dispersive nature and high order modes/effects from the actual microstrip

PCB board that is unaccounted for in the model.

6‐B3 The RE model is only concerned with the RE from differential-mode currents

while common-mode current effects may not be fully excluded from the

experimental setup.

6‐B4 The RE model is only concerned with the far-field 0 1r but neglects the

near-field contributions from the Hertzian dipole modelling elements.

6‐B5 The fields being measures are very small which may be affected by unwanted

sources of interference unaccounted for in the measurement setup.

6.3 Conclusion

Chapter 6 98

6‐B6 The chamber’s performance may be poor at low frequencies.

The discussions given above are general observations. For the various plot categories,

more specific observations can be made for the following:

6‐C1 Figure 6.2 to Figure 6.11: The comparison of the REs from the model and

experiment shows good agreement. At the high damping factor of 0.7, the RE

for the SSD is lower at low frequencies and also at the resonances in comparison to

the RE for the DPD. In general, the RE for the SSD is lower compared to the RE for

the DPD for the various test cases. It is also interesting to note that for the 5 cm

line, we see better agreement at high frequencies compared to the 15 cm line. At

low frequency, the 15 cm line gives better agreement between the model and

experiment when compared to the 5 cm line.

6‐C2 Figure 6.12 to Figure 6.13: At low frequencies, the RE for 10 pFLC is

lower than the RE for 20 pFLC because of the higher currents. At high

frequencies, the capacitor behaves like an inductor so we see the opposite effect.

6‐C3 Figure 6.14: We see the effect of the various damping factors from 0.2 to

0.7. We see that increasing the damping reduces the RE especially at the

resonances. This observation can be explained using Figure 3.4. The resonance

peaks of the SSD TF is bounded by the expression given by (3.10).

It is clear from the results that the RE model is indeed a very good predictor for the

electric far-field. We are able to study the effects of damping on RE which are key to

the thesis. Performance characterisation of the RE between the SSD and DPD is

possible under approximately equal SI conditions. In general, the RE from the SSD

outperforms the RE for the DPD for a fixed damping factor.

6.3 Conclusion

We have seen from the validation of the REs that there is excellent agreement between

the RE model and experiment. The RE results also shows us that, in general, the SSD

termination scheme will generally outperform the DPD scheme under equivalent SI

conditions. It is also found that for short lines, the RE for the SSD is almost always

better than the DPD over the frequency range of interest.

7.1 Conclusion

Chapter 7 99

Chapter 7. Conclusion and Future Work

7.1 Conclusion

The work presented in this thesis is concerned with the Signal Integrity and Radiated

Emissions of Printed Circuit Board Microstrips in Digital Switching. The work consists

of two major components:

7‐A1 The development of low order analytical models and computer models suitable

for the evaluation of the SI and RE performance of two schemes for damping PCB

interconnects, namely, SSD and DPD.

7‐A2 The design and execution of experiments to provide measurements based on

practical PCB microstrip interconnects of various lengths, and with various damping

and capacitive loads for the validation of the analytical models.

A key objective of the work reported here is the development of 2nd-order models for

short to medium length PCB interconnects which allows us to determine quantitatively

the effect of interconnect parameters on SI . The 2nd-order model developed in Chapter

3 is sufficiently simple to allow simple design equations for achieving the required SI

performance of interconnects based on SSD and DPD. Furthermore, the 2nd-order

model enables a quantitative comparison of the relative merits of SSD and DPD. A key

result of the 2nd-order modelling is that it is possible to identify the parameters for

which an interconnect of a given length and capacitive load has approximately the same

SI performance for both SSD and DPD. It is then possible under this practically useful

SI equivalence to evaluate the relative merits of SSD and DPD with respect to other

performance parameters identified in Chapter 3, such as peak transient currents, power

dissipation and RE behaviour. The RE performance can be predicted using the

computationally efficient RE-approximation model developed in Chapter 5.

The experimental validation of the 2nd-order TF model for an interconnect based on

SSD or DPD has been presented in Chapter 4. The experimental results are based on the

measurement of the SR of a number of PCB interconnects of different length and

different capacitive loading for both SSD and an approximation to DPD. The results

show that for short lines there is very good agreement for the predicted and actual SR

for both SSD and DPD. The experimental results also confirm that, as predicted, the

7.2 Future Work

Chapter 7 100

agreement between the actual and 2nd-order SR deteriorates as the length of the

interconnect increases. The experimental results also show that the predicted SR based

on the 2nd-order model is much better for SSD than DPD even for longer lines. This is

consistent with the higher damping of high frequency resonances achieved with SSD

that was put in, evident from the TF bound developed in Chapter 3.

Experimental validation of the RE-approximation model has been presented in Chapter

6. The experimental results of the RE from the same set of PCBs used for the SI

validation show very good agreement with the RE predicted by the RE-approximation

model. The experimental results confirm that, as predicted with the models developed,

SSD has generally lower peak RE for approximately the same SI performance as DPD.

Although this thesis is concerned almost exclusively with the SSD and DPD termination

schemes, the methodology of developing simple 2nd-order models to allow quantitative

evaluation of the SI performance, which has proved so valuable for the study of SSD

and DPD, can be extended to other damping schemes and to the use of higher order

models. The analytical modelling backed up by experimental results, reveals that for

point-to-point PCB interconnects, SSD offers advantages over DPD from the

perspective of SI and RE performance, as well as for other considerations such as peak

transient currents and power dissipation.

7.2 Future Work

Some interesting avenues for future work in the area of SI-RE related to the SSD and

DPD termination schemes are listed below:

7‐B1 Develop more realistic SR models for the SSD and DPD for a step input with

finite rise or fall time. A suggested aid may be to use the method presented in [47].

7‐B2 Investigate multipole TF representations for the SSD and DPD which can

enable higher order damping modes to be studied. Preliminary work has been

undertaken as documented in [3]–[5] and [7].

7‐B3 Develop electric near-field RE approximations for the study on damping.

7‐B4 Include the effects of common-mode currents in the RE modelling.

7‐B5 Integrate other loss models into the RE model to study their effects on

damping.

7.2 Future Work

Chapter 7 101

7‐B6 Investigate further the effect of losses on damping, especially due to radiation

and surface waves.

7‐B7 Improve on the idealised SSD loading of LC to include a finite input resistance

of the receiver.

7‐B8 Improve the SI models by including the effects of parasitics.

7‐B9 Use the methodologies used in this thesis can be applied to the study of other

termination schemes such as Thévenin, RC/AC and diode terminations [24].

Appendix A. Glossary and Reference Guide

Appendix A 102


This appendix serves as a quick reference guide to the many repeated acronyms,

symbols and terminology used throughout the thesis.

A.1 Mathematical Conventions

Variables are usually italicised.

Vectors are assigned in boldface and non-italicised.

Variable representing constants may be italicised or non-italicised subject to the

context within the text.

Variables and vectors with subscript or superscript may be non-italic subject to the context

within the text. Subscripts and/or superscripts annotations may also used as a

modifier to the meaning of the symbolic quantity. For example, the symbol is

used to designate a permittivity quantity and r represents the relative permittivity

which is dimensionless.

Variables representing time domain quantities, for example ,v t are usually

denoted in the lowercase and the corresponding frequency domain quantities are

denoted in the uppercase, for example .V f

Variables with a caret notation ^ represent phasor quantities that are time-harmonic

dependent, denoted with 2j fte that are suppressed for convenience. Examples of

such variables using the caret notation include the forced voltage and current

functions/variables. The caret notation can also be used with unit direction vectors.

Certain symbolic variables may have multiple definitions, within the mathematical

construct which they belong. For example, the variable k can mean a constant

factor or a phase constant. A comprehensive list is given in A.3.

Squiggly brackets are used to represent a function/variable transformation, for

example, L represents a Laplace transform. The brackets are also used to

represent a set which are normally used in set notation.


Appendix A 103

Square brackets are used to represent matrices, for example 1 2 .a a a

Angled brackets are used to represent vector components, for example

1, 0, 0p is the vector oriented one unit in the x direction assuming a Cartesian

coordinate system.

A.2 Common Unit Symbols/Abbreviations

Ampere A

decibel (dimensionless) dB

Farad F

Henry H

Hertz Hz

metre m

Neper (dimensionless) Np

Ohm

Ounce oz

radian (dimensionless) rad or (none)

Siemens 1S or or

thousandth of an inch mil

time s

Volt V

Watt W


Appendix A 104

A.3 Definition of Symbols

Conventional Symbol Definition Units

C Capacitance F

d Distance m

E Electric Field V m

f Frequency Hz

h Height, Time Domain TF m,

H Frequency Domain TF

, i I Current A

J Current Density 2A m

G Conductance

k Phase Constant, System Residue rad m, rad s

l Length m

L Inductance H

R Resistance

s Laplace Domain Variable rad s

t Time s

P Power W

Q Charge C

T Interconnection Delay, Period 1s, s

, v V Voltage potential V

w Width m

Z Impedance


Appendix A 105

Greek Symbol Definition Units

Attenuation Constant Np m

Phase Constant rad m

Complex Propagation Constant 1m

Loss Angle m

Permittivity F m

Wavelength m

Permeability H m

Reflection Coefficient

Conductivity S m

Delay, Settling Time, Time Constant s, s, s

Velocity m s

Angular Frequency rad s

Damping Factor

Coordinate Symbol Definition Units

O Origin

, , P r Spatial Spherical Point m, rad, rad

, , P x y z Spatial Cartesian Point m, m, m

A.4 Physical Constants

80 2.99792458 10c Speed of light in free space m s

12o 8.854187817 10 Permittivity in free space F m

60 1.256637061 10 Permeability in free space H m


Appendix A 106

4.5, 4.8r FR-4 dielectric relative permittivity

tan 0.02 FR-4 dielectric loss tangent

0.9999906r Copper Cu relative permeability

8Cu 1.673 10 Bulk copper resistivity m

typ 7Cu 5.8 10 Typical copper conductivity m

A.5 Abbreviations and Acronyms

Note that the letter ‘s’ may be attached to the abbreviation or acronym listed to

represent the plural form.

2nd Text Literal: Second

3D 3-Dimensional

AC Alternating Current

CAD Computer-Aided Design

CMOS Complementary Metal Oxide Semiconductor

Comp Compensated

DC Direct Current

FR-4 Flame Retardant-4 (Printed Circuit Board Dielectric)

Meas Measurement

Par Parallel

PSPICE Personal Computer Simulation Program with Integrated Circuit Emphasis

Pu per-unit-length

RC RC Circuit

Recv Receiver

RF Radio Frequency

SMD Surface Mount Device


Appendix A 107

TDR Time Domain Reflectometer

TG Tracking Generator

A.6 Software Packages

Brief descriptions of the names of the software packages encountered in the text are

listed below.

Software

Agilent VEE

(see also [60])

Note: Graphical dataflow software package developed by Agilent Technologies, Inc.

ANSYS

(see also [61])

Swanson ANalysis SYStems

Note: Engineering simulation software package developed by ANSYS, Inc.

FEKO

(see also [62])

FEldberechnung für Körper mit beliebiger Oberfläche

Field Calculations for Bodies with Arbitrary Surface

Note: Computational electromagnetic software package developed by EM Software & Systems-S.A. Pty. Ltd.

Mathematica

(see also [63])

Note: Mathematical software package developed by Wolfram Research, Inc.

MATLAB

(see also [64])

MATrix LABoratory

Note: Technical computing software package developed by The MathsWorks, Inc.

OrCAD

(see also [65])

Note: Electronic design automation software package developed by Cadence Design Systems, Inc.

Sonnet

(see also [66])

Note: 3D planar electromagnetic software package developed by Sonnet Software, Inc.

Appendix B. Useful Conversion Formulae

Appendix B 108


Conversion formulae that are useful and have been used in this thesis are presented in

this appendix. Some of the formulas are relevant to PCB design and others are relevant

to power conversions in 50 systems, FEKO data conversions, etc.

B.1 Decibel to Neper Conversion

Taken from [P-1], the decibel to neper conversion is given by

dBNp

20log

e. (B.1)

This conversion is often used to convert loss mechanisms specified in industry

datasheets as decibels to nepers that are used in analytical models. An example is the

propagation constant.

B.2 Metric to Mils Conversion

Taken from [76], the metric to mils conversion is given by

mil 0.254 m . (B.2)

This conversion is normally used with PCB design and footprint.

B.3 Ounces to Mils Conversion

Taken from [77], the ounces to mils conversion is given by

ozmils

1.378 . (B.3)

This conversion is normally used with PCB rated in ounces.

B.4 dBm to Voltage Conversion in 50 Systems

From the power definition for dBm, the conversion from dBm to V can be derived and

is given by

dBm

310V 50 10

. (B.4)


Appendix B 109

This conversion is normally used to convert RF power to a voltage for further analysis.

B.5 dBV Far Field Conversion in FEKO

The far field results generated by FEKO (full-3D electromagnetic solver) suppresses the

factor jkre r (see also [78]). Generating the magnitude of the far field results in FEKO

as a dB quantity requires the following correct conversion to a desired dBV at a

distance d

FEKO

dBμV dB 120 20log d . (B.5)

The conversion (B.5) is frequently encountered in the generation of RE results from

FEKO n comparison to the RE experimental validation results.

B.6 Electric Far Field Vertical Polarisation Conversion

The conversion of the electric field components listed in Table 5.1 to its vertical

component in the Cartesian system from the spherical system only requires the ˆE

component. The required transformation can be obtained from [14] and is given by

ˆ ˆ sin zE E . (B.6)

Appendix C. Derivations and Results for Chapter 3

Appendix C 110


This appendix presents derivations directly relevant to the results presented in Chapter

3. The development of the TFs for the simple 2nd-order model for the SSD, DPD and

approximate-DPD is presented in section C.1. The derivation for the envelope-bound

for the SSD is provided in section C.2. The SRs, delay, peak and steady-state currents

due to a step input are presented in section C.3, section C.4, section C.5 and section C.6

respectively.

C.1 2nd-Order Voltage TF Approximations for the Damping

Termination Schemes

This section presents the derivation of 2nd-order approximations, via the Taylor

truncation method, from the exact voltage TF for the lossless TL model. The TF

approximation arising from this approach is referred to as the 2nd-order TF model.

The voltage TF for a lossless TL is given by (2.2) is repeated here for convenience and

using the substitution 2 dl fT may be written as

exactlossless 2cos sin

C L

C S L C S L

Z ZH

Z Z Z l j Z Z Z l

. (C.1)

A Taylor series expansion of the transcendental functions in (C.1) are given by [57]

2

0

1cos

2 !

n n

n

ll n

n

, (C.2.a)

2 1

0

1sin

2 1 !

n n

n

ll n

n

. (C.2.b)

The small angle approximations 1l for 0n results in

cos 1l , (C.3.a)

sin l l . (C.3.b)


Appendix C 111

Substituting (C.3.a)–(C.3.b) into (C.1) and with some rearranging yield

exactlossless 1

exact LFlossless

1

C

lC C

S CL L

ZH

Z ZZ j l Z j l

Z Z

H

. (C.4)

Given that 2 dl fT obtained from (2.3) and for C CZ R defined as a real

resistance, (C.4) may be written as

exact LFlossless

2 1 2

C

C CS d C d

L L

RH f

R RZ j fT R j fT

Z Z

. (C.5)

C.1.1 2nd-Order Voltage TF Approximation for the SSD Termination

Scheme

Given the SSD termination scheme as illustrated in Figure 2.1,

SSDSZ R , (C.6.a)

1

2LL CL

Z Zj f C

. (C.6.b)

Substituting (C.6.a)–(C.6.b) into (C.5) and then rearranging yield the 2nd-order TF

approximation for SSD defined as 2ndSSDH which is given by

2ndSSD

2SSD

1

1 2 2C L d C L dC

H fR

j f R C T j f R C TR

. (C.7)

By equating the like terms of (C.7) and (3.2) solves for the unknowns in (3.2) such that

SSDSSD

1

2C L d

C C L d

R R C T

R R C T

, (C.8.a)

1

n

C L dR C T . (C.8.b)

Note that (C.8.a) and (C.8.b) are the damping factor and system natural frequency

respectively for a 2nd-order system for the SSD termination scheme for the lossless TL.


Appendix C 112

C.1.2 2nd-Order Voltage TF Approximation for the DPD Termination

Scheme

Given the DPD termination scheme as illustrated in Figure 2.2,

0SZ , (C.9.a)

DPDDPD DPD

DPD

1

2 1 2LL CL L

RZ R Z R

j f C j f R C

. (C.9.b)


approximation defined as 2ndDPDH which is given by

2ndDPD

2o

DPD

1

1 2 2dC L d

H fT R

j f j f R C TR

. (C.10)

By equating the like terms of (C.10) and (3.2) solves for the unknowns in (3.2) such that

DPDDPD

1

2C d

C L

R T

R R C , (C.11.a)

1

n

C L dR C T . (C.11.b)

Note that (C.11.a) and (C.11.b) are the damping factor and system natural frequency

respectively for a 2nd-order system for the DPD termination scheme for the lossless TL.

C.1.3 2nd-Order Voltage TF Approximation for the SDD Termination

Scheme

Given the SDD termination scheme as illustrated in Figure 2.3,

SDSZ R , (C.12.a)

DDDD DD

DD

1

2 1 2LL CL L

RZ R Z R

j f C j f R C

. (C.12.b)


Appendix C 113


approximation defined as 2ndSDDH which is given by

DD

2nd SD DDSDD 2

2SD DD DD

SD DD SD DD

1 2 2C L d C d C L d

C

R

R RH f

R R R C T R T R R C Tj f j f

R R R R R

. (C.13)

Given a 2nd-order system, the TF for the SDD may also be represented by the following

form given by

SDD

SDD SDD

2SDD2nd

SDD 2 2

22

n

n n s j f

KH f

s s

, (C.14)

in which SDDK is the gain scaling factor. Equating the like terms of (C.13) and (C.14)

solves for the unknowns in (C.14) yields the following

DDSDD

SD DD

RK

R R

, (C.15.a)

SDSD

1

2C L d

C C L d

R R C T

R R C T

, (C.15.b)

DDDD

1

2C d

C L

R T

R R C , (C.15.c)

SDD SDD SD DDK , (C.15.d)

SDD

SDD

1 C L dn

R C T

K . (C.15.e)

(C.15.d) and (C.15.e) are the damping factor and system natural frequency respectively

for a 2nd-order system for the SDD termination scheme for the lossless TL. Note that

(C.15.b) and (C.15.c) look very similar to (C.8.a) and (C.11.a) respectively, but are for a

different 2nd-order system. As such, the subscript designators SD and DD are used for

the SDD termination scheme rather than SSD and DPD respectively to avoid any

ambiguities that may arise from the meaning of the damping resistances.


Appendix C 114

C.2 Envelope-Bound Approximations of the Exact Lossless

Voltage TF for the Damping Termination Schemes

This section presents the derivations of the envelope-bound for the exact lossless

voltage TF for the SSD and DPD termination schemes. The approach relies on the

application of the worst case analysis to obtain the approximate envelope-bounds. It is

shown that a useful upper bound can be obtained for the SSD.

To develop envelope-bound for the exact lossless voltage TF (2.2) is repeated here for

convenience

exactlossless 2cos 2 sin 2

C L

C S L d C S L d

R ZH f

R Z Z fT j R Z Z fT

. (C.16)

To obtain the magnitude of (C.16) for the SSD and DPD termination schemes, the

complex number representation can be used to yield [57]

exactlossless C LN f R Z , (C.17.a)

exact 2lossless cos 2 sin 2C S L d C S L dD f R Z Z fT j R Z Z fT , (C.17.b)

exact exactlossless lossless

exactlossless exact exact

lossless lossless

=N D

H fD D

. (C.17.c)

Note that exactlosslessD represents the complex conjugate of exact

lossless.D

The notation for supremum and the notation for infimum (see also [58]–[59])

adopted for the upper and lower envelope-bounds respectively for exactlossless ,H f thus

exact exactlossless losslessUpper envelope-bound of H f H f , (C.18.a)

exact exactlossless losslessLower envelope-bound of H f H f . (C.18.b)


Appendix C 115

C.2.1 Envelope-Bound Approximations of the Exact SSD Termination

Scheme

For the SSD termination scheme as illustrated in Figure 2.1,

SSDSZ R , (C.19.a)

1

2LL CL

Z Zj f C

. (C.19.b)

Substituting (C.19.a)–(C.19.b) into (C.17.c) and after some rearranging yields the

magnitude of the exact TF for SSD which is given by

exactSSD 22

22SSD

cos 2 2 sin 2

2 cos 2 sin 2

C

C d C L d

C L d d

RH f

R fT f R C fT

R f R C fT fT

. (C.20)

From an analysis point of view, the envelope-bounds for (C.20) is taken under the

assumption that the transcendental terms in the denominator of (C.20) oscillates to a

maximum value of 1 or minimum value of 1.

The maximum and minimum bound represented by exactSSDH f is approximately

exactSSD 2 22 2

SSD

22 2SSD

1 2 1 2 1 1

worst case analysis1 2

C

C C L C L

C

C C L

RH f

R f R C R f R C

R

R R f R C

. (C.21)

Note that from (C.21), an upper or lower bound is contained within each other. Equation

(C.21) can further be simplified as a new approximation for the condition

2 1.C Lf R C To an approximation, (C.21) after applying the condition 2 1C Lf R C

becomes

exactSSD 2 22 1

SSD

1

2C Lf R CL C

H ff C R R

. (C.22)


Appendix C 116

A closer inspection of (C.22) reveals that the upper and lower bounds are dependent on

CR and SSD.R There exist two extremes by which SSDCR R and SSD ,CR R the

envelope-bounds (C.22) becomes

SSD

exactSSD

2 1,

1

2C L Cf R C R R L C

H ff C R

, (C.23.a)

SSD

exactSSD

2 1, SSD

1

2C L Cf R C R R L

H ff C R

. (C.23.b)

It is seen from (C.23.a)–(C.23.b) that the envelope-bounds carry the form 1 2 L xf C R

depending on whether xR is approximately CR dominant or SSDR dominant. Equations

(C.23.a)–(C.23.b) may be combined into one equation with the use of some set notation

SSD SSD SSD

exactSSD 2 1

: :

1

2C L

x C C C

f R CL xR R R R R R R

H ff C R

. (C.24)

Note for the purpose of SI studies, only the upper bound is of interest.

From (C.24), the function is a reciprocal type function and is largest when the

denominator is smallest. Now consider variables f and LC to be fixed constants, the

upper envelope-bound of (C.24) is an approximate upper envelope-bound to (C.20)

when SSDCR R or when SSD.CR R Mathematically, this is equivalent to writing

SSD

exactSSD

2 1min ,

1

2C Lx C

f R C L x R R R

H ff C R

. (C.25)

Note that (C.25) is the approximate upper envelope-bound for (C.20), for the SSD

termination scheme.

C.3 2nd-Order Voltage SRs

The time domain SR of a 2nd-order system for various conditions of damping is

summarised in Table C.1 [52]–[56].


Appendix C 117

Responses 2nd-Order Unit SRs 2ndSRV t

Underdamped 0 1 2nd 2 1

SR 2 21 cos 1 tan

1 1

nt

n

eV t t

(C.26)

Undamped 0 2ndSR 1 cos sinn nV t t t (C.27)

Critically Damped 1 2nd

SR 1 cos 1ntnV t e t (C.28)

Overdamped 0

2 2

2ndSR 2

2

1 cosh 1

1sinh 1

1

n

nt

n

t

V t et

(C.29)

Table C.1 2nd-order SRs.

The derivation of some of the responses given in Table C.1 can be found in [53]–[54].

Additional resources on the Laplace transforms useful in the derivations of (C.26)–

(C.29) can also be found, for example, in [79]–[81].

C.4 Delay Approximation for a 2nd-Order Step

This section presents the key derivation steps for obtaining the delay approximation due

to a 2nd-order step input.

Consider the general 2nd-order TF for a linear time invariant system given by [55]–[56],

2

2 2

22

n

n n s j f

H fs s

. (C.30)

The voltage SR denoted by SRv t for the underdamped condition 0 1 can be

represented as given by [52]–[53], [55]–[56]

SR 1 cos sin

1 sin

n

n

t

x x n xx

tn

xx

ev t t t

et

, (C.31.a)

21x n , (C.31.b)

1cos . (C.31.c)


Appendix C 118

Note that the right hand side of (C.31.a) can be simplified using the equivalent single

sine expression, which is left as an exercise.

From the definition of the Taylor series of a function f at a is given by [57], [58]–[59]

2

0 !,

!

kk

k

mm

f ax a f a f a x a f a x a

kk m

f ax a

m

. (C.32)

Next, is to take a first-order Taylor series expansion of SRv t at xb as a first-

order approximation, denoted by T1stSR , ,v t b such that

T1stSR SR SR,

x x x

v t b v v tb b b

. (C.33)

For 1, cosxA t B and given (C.31.b), SRv t can be written as

2 2

SR sin cos sinn nt t

n x nx x x

x n x

e ev t t t t

. (C.34)

Then at ,xt b the following

SR 1 cos sin

n

xb

x nx x

ev

b b b

, (C.35.a)

2

SR sin

n

xbn

x x

ev

b b

, (C.35.b)

can be obtained.

Now, evaluating (C.33) defined as thldV , at st to represent the rising edge setting

time delay, via (C.35.a)–(C.35.b) and (C.34) yields

T1stthld SR SR SR,s s

x x x

V v b v vb b b

. (C.36)


Appendix C 119

Rearranging (C.36) to solve for s explicitly yields the delay approximation for the

rising edge to reach to a threshold thldV or a fraction of the steady-state value of the SR,

given by

thld SR

SR

xs

x

x

V vb

bv

b

. (C.37)

It has been shown in [12], and will not be provided here, that choosing 2b provides a

useful delay approximation, and thus (C.37) with expanding out x using (C.31.b) and

some rearranging, evaluates to

2

2

2 2 1

thld 2 22 1

111

1 2 1s

n

eV

e

. (C.38)

C.5 Initial Current Transient Approximations for a Step Input

using Reflection Coefficients

This section presents the key derivation steps for the initial current transient

approximation due to a step input. For the step input on a lossless TL, a bounce or

lattice diagram (via reflection coefficients) may be used to characterise the response, as

a piecewise response, at either end or at some observable point ,x t along the TL for

either a fixed position x or time .t The scenario for a fixed position, at the beginning of

the TL, will be used to obtain the initial current, as an approximation, after the first

travelling wave reflection. Some preliminary work for the bounce diagram will be

introduced to quantify the current transients for the damping schemes. The key steps are

to determine the current reflection coefficients, develop the bounce diagram and then

apply to the termination schemes to obtain the current approximations.


Appendix C 120

To determine the current reflection coefficients for a lossless TL, consider the source

and load voltage reflection coefficients that are defined as follows [14],

v S CS

S C

Z ZV

V Z Z

, (C.39.a)

v L CL

L C

Z ZV

V Z Z

. (C.39.b)

Note that the superscript v in (C.39.a)–(C.39.b) is referenced the forward travelling

voltage V and backward travelling voltage .V

The relationship between the travelling voltages V and V are related to the travelling

currents I and I via the characteristic impedance given by [P-1]

C

VI

Z

, (C.40.a)

C

VI

Z

. (C.40.b)

From (C.40.a)–(C.40.b), the current reflection coefficients iS and i

L can be obtained

as given by

i vS CS S

S C

Z ZI

I Z Z

, (C.41.a)

i vL CL L

L C

Z ZI

I Z Z

. (C.41.b)

Also note that the superscript i in (C.41.a)–(C.41.b) is referenced to the current.

Given (C.41.a)–(C.41.b), the bounce diagram for the current waveform given the step

input voltage stepv t of range 00,V is defined as a piecewise function (related to the

unit step function [79]) given by

0step

0

0 , for 0

, for 02

, for 0

t

Vv t t

V t

. (C.42)


Appendix C 121

Given the definitions above, the bounce diagram can now be constructed as shown in

Figure C.1.

Figure C.1 Bounce diagram for the current waveform ,I x t for a lossless TL.

Note that 0I in the bounce diagram of Figure C.1 refers to the initial launch current

which is related to the amplitude 0V of the step input step.v The current transient

approximation on the TL is obtained by summing the values along the zigzag of the

bounce diagram that intercepts with a fictitious vertical line-cut extending across the

bounce diagram, for a fixed location x along the TL. The summing of values stops

when the desired time, represented by another fictitious horizontal line-cut extending

across the bounce diagram, is reached. This translates to reading off the ,x t

coordinate on the axes along the zigzag.

,d CT Z

lSZ

stepv t LZ

0x x l x

0I

0t

dt T

2 dt T

iS i

L

3 dt T

0iL I

0i iS L I

t t

,V x t

,I x t


Appendix C 122

C.5.1 SSD Current Transient Approximation of the Step Input using

Reflection Coefficients

For example, for the SSD termination, the current at 0x for the times 0t and

2 dt T will be obtained. Given the following terminations for the SSD scheme

SSDSZ R , (C.43.a)

C CZ R , (C.43.b)

LL CZ Z , (C.43.c)

the following current reflection coefficients are obtained

SSD SSD

SSD

i CS

C

R R

R R

, (C.44.a)

SSD 1d

iL t T

. (C.44.b)

The result of (C.44.a) is clear but for (C.44.b) is due to LZ being a momentary short

0LZ at dt T because LC is assumed to be initially unenergised.

The initial peak current SSD0I is

SSD 00 SSD

SSD

0,0C

VI I

R R

. (C.45)

The current at dt T is

SSD

SSD

SSD SSD SSD

0SSD

SSD

, 0,0 0,0

21 0,0

d

d

id L t T

iL t T

C

I l T I I

VI

R R

. (C.46)

At 2 ,dt T the current is

SSD SSD SSD

SSD SSD SSD

SSD SSD SSD SSD

SSD

SSD 0 SSD 0

SSD SSD SSD SSD

0,2 0,0 0,0 0,0

1 0,0

32

d d

d d

i i id L S Lt T t T

i i iL S Lt T t T

C C

C C C C

I T I I I

I

R R V R R V

R R R R R R R R

. (C.47)


Appendix C 123

By defining the initial peak current PI as

0P

C

VI

R , (C.48)

equation (C.47) may be written in terms of PI to obtain SSDi at 2 dt T given by

SSDSSD

SSD SSD

SSD 0

SSD SSD

22 3

3

Cd P P

C C

C

C C

R Ri T I I

R R R R

R R V

R R R R

. (C.49)

It is important to note that

SSD DPD2 2d di T i T (C.50)

because of the reduction of SSD SSD2 P CR I R R and also the additional factor of

SSDC CR R R in (C.49) in comparison to (C.56).

C.5.2 DPD Current Transient Approximation of the Step Input using

Reflection Coefficients

For example, for the DPD termination, the current at 0x for the times 0t and

2 dt T will be obtained. Given the following terminations for the DPD scheme

0SZ , (C.51.a)

C CZ R , (C.51.b)

DPD LL CZ R Z , (C.51.c)

the following current reflection coefficients are obtained

DPD 1iS , (C.52.a)

DPD 1d

iL t T

. (C.52.b)

The result of (C.52.a) is clear but for (C.52.b) is also due to LZ being a momentary

short 0LZ at dt T because LC is assumed to be initially unenergised.


Appendix C 124

The initial peak current DPD0I can be obtained and is given by (see also (C.48), p. 123)

DPD 00 DPD 0,0 P

C

VI I I

R

. (C.53)

The current at dt T is

DPD

0DPD

DPD DPD DPD

DPD

, 0,0 0,0

21 0,0

d

d

id L t T

iL t T

C

I l T I I

VI

R

. (C.54)

At 2 ,dt T the current is

DPD DPD DPD

0DPD DPD DPD

DPD DPD DPD DPD

DPD

0,2 0,0 0,0 0,0

31 0,0

d d

d d

i i id L S Lt T t T

i i iL S Lt T t T

C

I T I I I

VI

R

. (C.55)

Equation (C.55) can then be rewritten for the new current DPDi at 2 dt T given by

DPD DPD DPD

0

DPD 2 1

3d d

i i id L S L Pt T t T

C

i T I

V

R

. (C.56)

C.6 Steady-State Current for a Step Input

This section presents the derivations for the steady-state current due to a positive and

negative step input for the SSD and DPD termination schemes.

For the determination of the steady-state current for a step input of 00, ,V the SSD and

DPD circuits shown in Figure 2.1 and Figure 2.2 respectively can be considered at DC

for the steady-state condition .t

The equivalent circuits for the SSD and DPD at steady-state for a positive step are

represented as shown in Figure C.2 and Figure C.3 respectively.


Appendix C 125

Figure C.2 Equivalent steady-state circuit due to a positive step for SSD.

Figure C.3 Equivalent steady-state circuit due to a positive step for DPD.

The equivalent circuit shown in Figure C.2 is an open circuit. Hence, the steady-state

current, SSSSD ,I is given by

SSSSD 0I . (C.57)

The steady-state current, SSDPD ,I for the equivalent circuit shown in Figure C.3 is given

by

SS 0DPD

DPD

VI

R . (C.58)

For a negative step, the sources in Figure 2.1 and Figure 2.2 are replaced by 0 V, hence

the steady-state currents are both zero.

DPDR0V

SSDR

0V

Appendix D. Design of PCB Interconnects for the Validation Results Presented in Chapter 4

Appendix D 126

Appendix D. Design of PCB Interconnects for the

Validation Results Presented in Chapter 4

This appendix contains the detailed design considerations of the PCB interconnects used

to measure the experimental results presented in Chapter 4 for the validation of the 2nd-

order models developed in Chapter 3.

The design considerations of damping components for SSD and the approximate-DPD

(SDD) are presented in section D.1. The design of the microstrip PCBs for the

experiments are presented in section D.2. The SI experimental setup is presented in

section D.3.

D.1 Damping Design Considerations

This section presents considerations for the damping designs for the SSD and SDD

termination schemes to enable for the completion of the experimental test PCB board

damping designs given in subsection D.1.1. Additionally, the steady-state voltage for

the voltage SR is presented in subsection D.1.2 as it is a useful result for the scaling

used in the SI experimental validation.

D.1.1 Termination Scheme Damping Design Considerations

For the SSD, the damping resistance SSDR can be obtained from (3.4) given SSD .

From the point of view of the SDD termination scheme with a non-ideal voltage source,

the source impedance represented as SDR can be considered to be small in comparison

to the destination parallel damping resistance DD.R The approximation can be made on

(C.15.a)–(C.15.e) to yield

SD DD

SDD 1R R

K

, (D.1.a)

SD DD

SDD SD DDR R

, (D.1.b)

SDD

SD DDn nR R

. (D.1.c)


Appendix D 127

Note that in (D.1.b), SD and DD are functions of SDR and DDR respectively. Assuming

that it is possible to design the SDD and SSD termination schemes to have the same

damping factor SDD SSD , the damping resistances can be obtained for a given

, , ,C L dR C T via (C.15.b) and (C.15.c) such that

SDSD

2 C C L d

C L d

R R C TR

R C T

, (D.2.a)

DDDD2C d

C L

R TR

R C . (D.2.b)

From (D.2.a)–(D.2.b) there are no guidelines to allocate the percentage of the damping

factor SD and DD that adds up to SDD. A design guideline is available in [7] that

impose certain conditions for the design on the damping.

D.1.2 Steady-State Value of the Voltage Step Response

Obtaining the steady-state voltage value due to a voltage step is important to provide an

estimate to the final value. This is useful when one wants to verify the measured SR for

the SDD using scaling.

At steady-state, the transient component has diminished and the voltage approaches the

final value as .t This scenario is equivalent to a DC circuit problem. Consider

Figure 2.3 represented at DC. The load capacitance LC can be removed because the

reactance is infinite (open circuit) at DC. The equivalent DC circuit for the SDD is

shown in Figure D.1. Note that the DC source have an amplitude of 0V corresponding to

the step input of 00, .V Here, the steady-state for the SDD termination scheme is only

considered but for the trivial cases of the SSD and DPD schemes, the steady-state

voltage is simply 0.V

Figure D.1 Equivalent SDD circuit at DC.

DDR

SDR

0V

SSSDDV


Appendix D 128

From Figure D.1, the steady-state voltage SSSDDV can be obtained via the voltage divider

formed by SDR and DDR which is given by

SS DDSDD 0

SD DD

RV V

R R

. (D.3)

D.2 Test Microstrip PCB Designs

The design of the microstrip, for the purpose of the experimental validation, forms an

integral part of this thesis. For the design of the microstrip, microstrip equations are

used to synthesise the trace width. An attenuator has been incorporated into the design

to allow for the realisation of an approximately equivalent DPD termination scheme.

This section presents the design methodology and equations used for microstrip design.

A background on the microstrip design is presented in subsection D.2.1. Subsection

D.2.2 presents the attenuator design followed by the damping resistances design in

subsection D.2.3.

D.2.1 Background on the Microstrip Design

A microstrip consists of a trace over a ground plane usually made up of copper and is a

widely as interconnections on many PCB designs. Figure D.2 shows the cross-section of

a microstrip structure. The microstrip design used for the experimental validation

assumes a homogeneous dielectric with the trace having a uniform cross-section.

Figure D.2 Microstrip cross-section.

There are many microstrip design equations in the literature ranging from simplified to

very complex models that can account for frequency dependent characteristic

impedance, dispersion effects, conductor surface roughness, etc. An excellent treatment

on the design of the microstrip can be found in [44]. A simple but yet effective

microstrip design model which takes into account of the trace thickness t is given by

the models presented in Table D.1 [6], [R-3].

, tanr

t

h

w

Ground Plane

Dielectric

Trace


Appendix D 129

Description Simple Microstrip Equations 1 r

Definitions

eff

eff

11 ln 4 , for 01.25 2

2 11 ln , for

2

w h

w h wtt h hw w h

rh h w

t h h

(D.4)

eff

1 1 1

2 4.6102 1

r r rr

t h

w hw h

(D.5.a)

Effective Permittivity and Characteristic Impedance

eff

effeff

eff eff eff

60 8ln , for 0 1

4

120 1, for 1

1.393 0.667 ln 1.444

w h

w hr

C

r w h w h

r w

r hZ

w

hr r

(D.5.b)

Table D.1 Summary of a simple microstrip model based on a modified Schneider approximation [41].

For the case when 0,t the microstrip model presented in Table D.1 yields

simplification to the effective permittivity and characteristic impedance presented in

Table D.2

Description Simple Microstrip Equations , 1 0 r t

eff

1 1

2 102 1

r rr

w h

(D.6.a)

Effective Permittivity and Characteristic Impedance

eff

8ln , for 0 1

460

2, for 1

1.393 0.667 ln 1.444

C

r

w h w

w h h

Z w

hw w

h h

(D.6.b)

Table D.2 Simple microstrip model based on a modified Schneider approximation for trace thickness 0.t

Note that the models presented in Table D.1 and Table D.2 are one of the many variants

of the original Schneider microstrip model [44], [67]. Depending on the level of

approximation and accuracy required, further improvements can be made to the

microstrip models presented. Improvements such as taking into account the effective

parameters, frequency dependent parameters, incorporating empirical results (hybrid

model), etc can also help to provide insights on their effects on microstrip interconnects.


Appendix D 130

For the microstrip synthesis to obtain the cross-sectional width of the microstrip trace,

the tool [68] is used which has been tested to be reliable. For the FR-4 material used for

the PCB board, the permittivity of 4.5 r is used. For a dielectric height of

1.5 mm,h the synthesised trace width is 1.452 mm.w

Given the synthesis parameters, the microstrip can be CAD routed in the design process.

The software package Protel 99 SE is used for the CAD routing which have been

superseded by Altium Designer [69]. The standard CAD files in the format known as

Gerber files are sent off to the manufacturer for the microstrip PCB fabrication. Note

that the Protel 99 SE package is one of many PCB layout tools and in addition, there are

also open-source/free versions available on the web such as FreePCB [70]. Furthermore,

the conversions presented in appendix section B.2 and appendix section B.3 are helpful

for the design of the PCBs.

An example of a routed trace design is shown in Figure D.3. The terminal circuit

component pads are routed on the opposite side (indicated by the green overlay). Proper

design of the microstrip is required to ensure the boards can be used for the SI-RE

experimental validations.

Figure D.3 An example of the 10 cm microstrip showing the trace.

D.2.2 Attenuator Design

As part of the microstrip design, the attenuator circuit have to present fixed low input

impedance as seen by the input port of the microstrip trace. The reason for a low input

impedance specification is to be able to use the fabricated microstrip boards for the

10 cml

1.452 mmw Via Via

30 cm

15 cm Source End Destination End


Appendix D 131

production of the approximately DPD scheme via the SDD scheme for the experiment.

This is best illustrated in Figure D.4.

Figure D.4 Approximate DPD example of the attenuator incorporated into the microstrip design.

Another criterion of the attenuator design is the ability to be able to produce a high

output voltage while maintaining the low output impedance, over a specified frequency

band. The desired specification of a higher output voltage will result in better RE

measurements as the signal-to-noise ratio is improved. The higher signal will make the

RE field easier to measure and improve the dynamic range.

The driving source as shown in Figure D.4 represents an RF source having an output

impedance, typically, of 50 so that 1 50 .Z By choosing the output impedance of

the attenuator to be one tenth of the input, 2 5 ,Z hence attenmin_dB 15.78 dB.K The

value of attendB 16 dBK have been chosen as part of the design specification so that more

signal voltage can be present at the attenuator’s output while maintaining a low

impedance.

Given the specifications 1 50 ,Z 2 5 Z and attendB 16 dB,K the resistances 1,R

2R and 3R can be computed via [71]–[72]

atten

attenatten

Input Power

Output Poweri

o

PK

P

, (D.7.a)

atten attendB 10logK K , (D.7.b)

1 2

1

2 1

1

1 2

K Z ZR

K Z KZ

, (D.7.c)

DPD SDD

Source Attenuator

Microstrip Trace

Load Network

1Z 2Z


Appendix D 132

2 1

2

1 2

1

1 2

K Z ZR

K Z KZ

, (D.7.d)

1 23

1

2

Z ZKR

K

, (D.7.e)

in order to yield the results as summarised in Table D.3. The resistances for the

attenuator design can also be evaluated using available tools given by the links listed in

[73]–[74].

Attenuator Parameter Attenuator Parameter Value

Attenuation attendB 16 dBK

Input Impedance 1 50 Z

Output Impedance 2 5 Z

Ideal Approximation E96 ±1 % Resistor Series

Shunt In Resistance 1 2143.12 R par1 4320 549000 4320 549000 R

Shunt Out Resistance 2 5.27 R par2 12.7 62 12.7 62 R

Series Resistance 3 48.63 R par3 48.7 33200 R

Table D.3 Attenuator design.

In Table D.3, the resistances closest to the ideal approximations have been selected

using E96 ±1 % resistor series. Note that the selection of E96 resistor values can be

obtain by using the tool such as that given by the link in [75].

The parallel (par) combinations of resistor stackups par1 ,R par

2R and par3R have been

which has the advantage over series combinations. Furthermore, by utilising 0603

surface mount device (SMD) resistors; the lead inductance can further be reduced. Also

note that par1R and par

2R are two symmetrical pairs stackup whereas par3R is only a pair

stackup. More on this configuration is provided in [7].

D.2.3 Damping Resistances Design

This subsection presents very brief steps for the design of the damping resistances for

the SSD and SDD (approximate-DPD) termination schemes given the equivalent


Appendix D 133

impedance atten2 5 .SZ R Further detailed designs for the damping resistances is

also available in [7]. Furthermore, the damping factors of 0.2, 0.5, 0.7 have been

chosen for the SI-RE experimental validation to accommodate a low, intermediate and

high damping factor scenarios. In addition, a choice of microstrip length

5, 10, 15 cml will be experimented upon, corresponding to the approximate delays

of 0.3, 0.6, 0.9 nsdT for the designed 70 CR microstrip PCB test boards.

The circuit design for required damping terminations for the experimental setup is as

shown in Figure D.5.

Figure D.5 SSD and SDD (approximate-DPD) equivalent experimental circuit.

The corresponding equations for the SSD used for the resistance design are given by [7]

SSD

2 C C L d

C L d

R R C TR

R C T

, (D.8.a)

attenasd SSD SR R R . (D.8.b)

For the SDD, the resistance design equations are given by [7]

atten

SD

1

2

S C L d

C C L d

R R C T

R R C T, (D.9.a)

5, 10, 15 cm

0.3, 0.6, 0.9 nsd

l

T

70 CR

70 CR parDDR

atten 5 SR

attenSV 10, 20 pFLC

10, 20 pFLC

parasdR

atten 5 SR

attenSV

parasd 0 R

attenSSD asdSR R R

attenSD SR R

SSD

SDD

Experimental Test Scenarios: 0.2, 0.5, 0.7


Appendix D 134

DD SD , (D.9.b)

DDDD

1

2C d

C L

R TR

R C . (D.9.c)

D.3 SI Experimental Setup

Validation of the theoretical models with experimentation can be achieved through

careful design of all aspects relating to all SI-RE validation test setup.

A set of microstrip PCB boards will be used for the SI validation as well as the RE

validation in section 5.4, therefore PCB layout for both SI and RE have to be considered

at the design phase. For the study of the SSD and DPD termination schemes, the

microstrip PCB boards have to work with 50 measurement systems. For example, at

the source end, the 50 output loading from an RF source have to be taken into

account for the two damping schemes.

Figure D.6 SSD and SDD (approximate-DPD) experimental circuit design.

50 RF Source

Attenuator Network

attenSV

attenS SZ R

, dT l

CR

CR DDR

attenSR

attenSV LC

LC

asdR

attenSR

attenSV

asd 0 R

attenasd SSDSR R R

attenSDSR R

SSD

SDD


Appendix D 135

To be able to achieve a PCB design that will allow for the SSD or approximate-DPD, an

attenuator network has been introduced into the design. The attenuator forms equivalent

low impedance with the 50 source represented by attenSR as shown in Figure D.6 for

the SSD and approximate-DPD schemes. Also, note that Figure D.6 does not show

modelling of the inductances from the various interconnections in the form of

connectors and connecting traces. These interconnections are considered short

compared to the microstrip trace and can be neglected as shown in Figure D.7.

Figure D.7 Example of the SR experimental setup.

The loading from the measurement system is in the form of a high impedance loading

(probe) have to be considered for the SI experimental setup. It is necessary to have a

low capacitance probe to minimally disturb the actual LC of the termination scheme

under test. Note that the 1158A 4 GHz Active Probe with low capacitance have been

used [85].

Signal Source

Fast Digitising Oscilloscope

PCB Test Board

Short Connections

Fast Edge Trigger Reference

Test Board Step Response Low Capacitance Probe

Measurement


Appendix D 136

The SI experimental test setup has two basic components. First, the characteristic

impedance, attenuator circuit, damping resistances and loading networks needs to be

verified for a particular test board before conducting the actual measurement. Second,

the SR response measurements are conducted as shown with an example in Figure D.7.

In Figure D.7, we note that a fast positive edge from the signal source device have been

used as a reference trigger to the fast digitising oscilloscope. The reference trigger

waveform is used to trigger on the step input signal as well on the SRs. This method

captures the delay information between the step input and the SR at the destination end

of the interconnect under test. For this method to work, the reference trigger must have

a faster transition time in comparison to the step input. Furthermore, the fast digitising

oscilloscope must have fast triggering specifications to accommodate for the fastest

transition pulse.

In this section, some important aspects key to the success of the SR results presented in

Chapter 4 is presented next. These aspects are the validation/checks for different parts

of the SI experimental setup such as the microstrip, attenuator, step generation, damping

resistances and SPICE modelling presented in subsection D.3.1.

D.3.1 SI Experimental Setup Validation

For the experimental validation work, microstrip boards have been designed to exhibit a

characteristic impedance of 70 CZ as a chosen static value. The value of CZ

chosen represent impedances typically found on PCBs which have microstrips. In a real

microstrip, CZ will be a function of frequency but under the quasi-static assumption and

also for frequencies below ,stat ,gf C CZ R [18], [40].

For the purpose of the RE validation work, the microstrip board had been chosen to

have a moderate planar extent (15 cm in board width and 30 cm in board length). The

reason for the moderate board dimension is to approximately satisfy the infinite ground

plane assumption used for the RE modelling. Ideally, a large PCB board is desired but

this will raise the manufacturing cost due to more materials being used, setup costs, etc

so a compromise had been made to design the experimental boards that is cost effective

and will work for the experiments.


Appendix D 137

This subsection is further broken into four sub-subsections. Next, aspects of the

microstrip synthesis validation are presented. Sub-subsection D.3.1.2 presents important

aspects concerning the attenuator network validation. Sub-subsection D.3.1.3 presents

important aspects concerning the pulse generator’s step generation. Sub-subsection

D.3.1.4 presents important aspects concerning the damping resistances. Note the

emphasis here is mainly focus on the aspects of validation/checks of the designed

microstrip PCBs for used in the SI experiments.

D.3.1.1 Microstrip Synthesis Validation Aspects

An important consideration in the synthesis of a microstrip, for example in Figure D.8,

is the trace width to dielectric height ratio in order to achieve a trace characteristic

impedance of 70 .C CZ R A trace width of 1.452 mmw and dielectric height of

1.5 mm,h which yields the ratio 0.968w h is required to achieve the desired .CZ

Figure D.8 Example of a fabricated 10 cm microstrip PCB board.

70 Microstrip Trace

Source End Destination End

ViaVia

10 cm Trace


Appendix D 138

During the manufacturing of the microstrip boards, a request for controlled impedance

ensures better characteristic impedance uniformity between the various PCB boards.

Note that there is no solder resist mask on the trace as shown in Figure D.8 because any

additional mask acts as a dielectric material over the trace which will affect the

characteristic impedance. The trace is only bare copper. The key idea for realising the

microstrip is to keep them simple for the purpose of experimental validation. The

addition of complexity put into the experimental boards will make the measurement

results difficult to track for the study of damping.

The validation of the characteristic impedance of the trace can be conducted using a

time domain reflectometer (TDR) as shown in Figure D.9. The value of 70 CR is

hence used in the theoretical calculations. It is important to note that calibration of the

TDR is crucial to be able to obtain correct impedance measurement results. Further

details on achieving precision TDR measurement can be found, for example, in [82]–

[83].

Figure D.9 Validation of the characteristic impedance via the TDR measurement.

D.3.1.2 Attenuator Network Validation Aspects

Given the chosen microstrip specification of 70 CR that will be fabricated on a

moderate planar PCB, the design of an attenuator network is required to be incorporated

into the microstrip termination scheme. Note that the typical role of an attenuator is

10 cm Microstrip Trace


Appendix D 139

used to minimise the mismatch between the input and output impedances.

The attenuator design and realisation is shown in Figure D.10. Note that the green

overlay text annotations R1a, R1b , R2a, R2b and R3 are resistors that form the

attenuator network. For example, R1a, R1b forms the 1R of the attenuator and so

on.

Figure D.10 Passive Pi ( ) network attenuator layout at source end.

The key design features for the attenuator are:

D‐A1 To present an attenuation of about a tenth of the input voltage source and

present a low output impedance.

D‐A2 To reduce component and trace parasitics by stacking up the SMD components

and having short interconnecting traces to reduce parasitic inductances.

D‐A3 To have a symmetrical layout as shown in Figure D.10.

In order to achieve an experimental design that will have a high percentage of success

for the validation is to design the experiment that closely resembles the theoretical

models. This means minimising the parasitics.

Via Via Via

Attenuator R1a, R1b, R2a, R2b, R3

Example of SMD Stackup

Component Footprints Component Routing Part of Actual PCB


Appendix D 140

Validation of the attenuator section of the microstrip may be checked via OrCAD

simulations as shown in Figure D.11 or from direct measurement of a test circuit.

Figure D.11 Attenuator design validation through OrCAD circuit simulator.

It has been confirmed from the OrCAD circuit simulator that the output steady-state

voltage with an input of pulse amplitude of ViH 10 V taken at R2atten is

approximately 0.5 V. The voltage at the output of the attenuator can be calculated to be

about one tenth of the input voltage as required given that 1 Rs 50 Z and

2 Rs R1atten R2atten R3atten 5 Ω.Z

D.3.1.3 Pulse Generator’s Step Generation Validation Aspects

The HP 8130A 300 MHz pulse generator is used as the driving input into the

microstrip PCB test boards [84]. The fastest allowable rise time of the HP 8130A is

670 psrt from which 662 ps has been measured. The difference in the rise time

value is attributed to the accuracy of the generator as well as parasitics that may be

introduced from the measurement. Obtaining the actual rise time can be done by

estimating the measured slope region of the rise time defined by the 10 % to 90 % of the

final steady-state value. A line of best fit can be used to approximate the rising slope

and hence an estimate of the actual rise time obtained. Given the definition for the rise

time and with the pulse generator set to an open circuit voltage ViH 10 V for the step,

the voltage at the output of the attenuator is atten 0.5 VSV as shown in Figure D.12.

Furthermore, the value of 662 psrt is used in the simulation models in Chapter 4.


Appendix D 141

Figure D.12 Measured step input and piecewise approximation for a rise time of 662 ps.rt

D.3.1.4 Damping Resistances Validation Aspects

The design of the damping resistances for the SSD and approximate-DPD termination

schemes can be achieved using equations presented in subsection D.2.3. One important

factor for the computation of the damping resistances is the determination of the one-

way TL delay for the choice of TL lengths 5, 10, 15 cm.l A technique have been

developed using the TDR by intentionally adding capacitance at the start and end points

of the microstrip trace which causes a dip on the TDR waveform. This is shown in

Figure D.13.

From the TDR measurements, the one-way delay for 5, 10, 15 cml is

0.2995, 0.5989, 0.8984 ns by which 0.3, 0.6, 0.9 nsdT are used for the

determination of the damping resistances, given 70 CR and 0.2, 0.5, 0.7 .

Note that the delay dT is also verified using microstrip analytical models. The key factor

for the design of the damping resistances is to keep the methodology for obtaining the

resistances consistent. If one chooses to use approximations from the microstrip models,

or from measurements such as that obtained from the TDR, then the dT will be in the

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Time t (ns)

Vol

tage

Ste

p I

np

ut

(V)

Piecewise Step Input: tr = 662 ps

Step Input (Meas): tr = 662 ps


Appendix D 142

correct ballpark range.

Figure D.13 Determination of the one-way TL delay.

Added finger capacitance point of contact

Driver End: Introduced Capacitance

Receiver End: Introduced Capacitance

One-Way TL Delay

Appendix E. Derivations and Results for Chapter 5

Appendix E 143


This appendix presents derivations of analytic formulas for the radiated far-field that

ultimately will result in the RE-approximation model presented in Table 5.1.

As a starting point, the microstrip modelled with TL currents will be derived for the

simple case on a defined xz-plane given in section E.1. This simplifies the derivation for

the RE of the more general case for 3D spatial field points in section E.2. Also,

provided in section E.3 is the comparison between the newly developed RE model and

the RE model given in [40].

E.1 Microstrip RE Planar Model

Consider a microstrip modelled as a TL with characteristic impedance CZ and

propagation constant satisfying 5-A1 and 5-A5, as shown in Figure E.1.

Figure E.1 Model of the microstrip TL defined on the xz-plane.

According to the TL theory, the current distribution along the line can be written as (see

also chapter subsection 2.4.3, p. 20)

lossylossy

ˆˆ cosh sinh S

C L

VI x Z l x Z l x

D, (E.1.a)

2lossy cosh sinh C S L C S LD Z Z Z l Z Z Z l . (E.1.b)

Observation Point

0x x l

h

h

lossyˆI x

lossyI x

SV

SZ LZ

polˆJ

ˆE

z

y x

r


Appendix E 144

The total electric field is composed of contributions form the two end segments, the line

currents and the polarisation currents. The RE model for the radiated electric far-field

will be derived for observation points in the xz-plane of the model shown in Figure E.1

using the assumptions in subsection 5.2.2.

E.1.1 RE Contributions from End Currents

The far-field from a vertically oriented Hertzian using 5-A2 dipole can be written as

0

0 lossyˆ ˆ sin

4

j re

dE j I dzr

. (E.2)

Using the parallel ray assumption 5-A3, the field from the two end currents as shown

in Figure E.2 is given by

00

0

0

sin0lossy lossy

sin0

lossy

(2 )sinˆ ˆ ˆ04

ˆsincosh sinh

2

j r lj rE

j rj lS

C L

hE j I e I l e

r

h V ej Z l e Z l

D r

. (E.3)

Figure E.2 RE fields from end currents.

lossyˆ 0I lossy

ˆI l

2h

sin l

r

oP

sin r l

z

x


Appendix E 145

E.1.2 RE Contributions from Polarisation Currents

The polarisation current density moment or current intensity is related to the derivative

of the line current given by (see also (2.12), p. 21)

lossypol,

lossy

ˆ ( )1ˆ 1

ˆ11 sinh cosh 0

zr

SC L

r

dI xJ dy

dx

VZ l x Z l x x l

D

. (E.4)

Equation (E.4) written in terms of the polarisation current is given by lossyI

pol lossyˆ ˆ( ) ( )1

1r

dI x dI x

dx dx

, (E.5)

or

lossypol

ˆ ( )1ˆ ( ) 1r

dI xh dI x h dx

dx

. (E.6)

The far-field from one differential polarisation current element moment, and with

application of the image theory (addition of a factor of two), yields

0

0

0

( sin )

'0 pol

sin0

ˆ ˆ2 ( ) sin4

sinhˆsin 11

2 cosh

j r xP

j rCj xS

r L

edE j h dI x

r

Z l xh Vej e dx

r D Z l x

. (E.7)

Let

0 sin( ) sinh cosh j xPC LF x e Z l x Z l x . (E.8)

Then the total far-field produced by the polarisation currents is

00

0

ˆ ˆ

ˆsin 11 ( )

2

P P

j rl PS

r

E dE

h Vej F x dx

r D

. (E.9)


Appendix E 146

Using the Mathematica solver (see also [63]) as an aide to check the integration results,

0

0

0 0

sin0

2 2 20

( )

sin cosh sin sinh

sin

sin

lP P

C L L C

j lC L

I F x dx

Z j Z l Z j Z l

Z j Z e. (E.10)

Therefore,

0

0

0

sin

002 2 2

lossy 0

sin

cosh

ˆ sin sinhsin 1ˆ 12 sin

C L

j l

j rL CP S

r

Z j Z

l e

Z j Z lh VeE j

r D

. (E.11)

E.1.3 RE Contributions from Line Currents

From 5-A4, consider two horizontal dipoles spaced by 2h of equal and opposite

currents representing the line currents as shown in Figure E.3.

Figure E.3 RE fields generated by horizontal line dipoles.

cos h

lossyˆ (0)I

2h sin x

lossyˆ (0)I

lossyˆ ( )I x

lossyˆ ( )I x

h

h

0x x

r

oP


Appendix E 147

The electric far-field due to a small section, dx of line current at the 0x

superscripted 0L is

0 0

0

0

cos cos0

lossy

00 lossy

cosˆ ˆ (0)4

cos ˆsin cos (0)2

j r h j r hL

j r

e edE j I dx

r r

eh I dx

r

. (E.12)

Note that the differential element defined in (E.2) is rotated clockwise by 2 hence

sin 2 becomes cos and the negative sign comes about because the unit

direction vector ˆa becomes ˆ ,a when the dipole is orientated as given in Figure E.3.

The far-field due to due to a small section, ,dx of line current at x is

o

0

0

sin0

0 lossy

0 0

lossy

sin

cosˆ ˆsin cos ( )2

ˆcos sin cos

2

cosh sinh

j r xL

j rS

j xC L

edE h I x dx

r

h Ve

r D

e Z l x Z l x dx

. (E.13)

Let

0 sin( ) cosh sinh j xLC LF x e Z l x Z l x . (E.14)

Again using the Mathematica solver,

0

0

0 0

sin0

2 2 20

( )

sin cosh sin sinh

sin

sin

lL L

L C C L

j lL C

I F x dx

Z j Z l Z j Z l

Z j Z e. (E.15)

The total field due to the line currents is

0

0

0

sin

00 0

2 2 2lossy 0

sin

cosh

ˆ sin sinhcos sin cosˆ2 sin

L C

j l

j rC LL S

Z j Z

l e

Z j Z lh VeE

r D. (E.16)


Appendix E 148

E.2 Complete Microstrip RE Model

This section presents derivations for the electric far-field from a microstrip TL. It is an

extension to the results developed for the planar case 0. For convenience those

derived results are presented here. Also for convenience, some equations in previous

sections are presented here as reference with newly allocated equation designators.

Description Microstrip RE Planar Model

End Segments Field

0

0'0

lossy

ˆˆ cosh sinh

2

j rj lE S

C L

h VeE j Z l e Z l

r D

sinsin (E.17)


0

0

0

lossy

0

0

2 20

ˆ1ˆ 12

sin cosh

sin sinh

j rP S

r

j lC L

L C

h VeE j

r D

Z j Z l e

Z j Z l

sin

2

sin

sin

(E.18)

Differential Line Currents

0

0

'0 0

lossy

0

0

2 20

ˆsin cosˆ2

sin cosh

sin sinh

sin

2

cos

sin

j rL S

j lL C

C L

h VeE

r D

Z j Z l e

Z j Z l

(E.19)

Total Field ˆ ˆ ˆ ˆ , for - , 02 2 T E P LE E E E (E.20)

Table E.1 Summary of the microstrip RE planar field contributions.

E.2.1 Planar Model Extension

It is now convenient to extend the model presented in Table E.1 for an arbitrary

observation point oP located in the top hemisphere that is above the xy-plane. There is

no necessity to apply a full derivation to obtain the new equations but rather work out

the new phase retardation and apply them to the electric field components in Table E.1.

This subsection presents the necessary modifications to the RE equations in Table E.1 to

arrive at the complete microstrip RE model.


Appendix E 149

E.2.1.1 Vertical Dipoles

Consider a vertical dipole along the x axis at location .xd The new phase retardation

contribution is now given by sin cos xd as shown in Figure E.4. Hence, the

transformation to the phase due to the end segments and polarisation currents given in

Table E.1 is to replace sin marked red by sin cos or written as

sin cos . sin Note that the symbol is used to indicate a replacement.

As it is observed from the derivations for the planar model and Figure E.4 that the

sin (shown as bold, i.e. sin in Table E.1, p. 148) of the electric far-field does

not need the transformation as it unaffected by the phase.

Figure E.4 Phase retardation contribution of a vertical dipole at an arbitrary location in the top

hemisphere.

The modifications to the planar RE contributions due the end currents can be

summarised below.

End Currents

sin sin

sin cos sin

0

0 sin cos0

lossy

ˆsinˆ cosh sinh2

j rj lE S

C L

h VeE j Z l e Z l

r D

. (E.21)

cos xd

xd

r

oP sin cos xd

x

z

y oP


Appendix E 150

Similarly, the modifications to the planar RE contributions due the polarisation currents

can be summarised below.

Polarisation Currents

sin sin

sin cos sin

0

0

0

sin cos

0

02 2 2 2

lossy 0

sin cos

cosh

sin cos

ˆ sinhsin 1ˆ 12 sin cos

C L

j l

L C

j rP S

r

Z j Z

l e

Z j Z

lh VeE j

r D. (E.22)

E.2.1.2 Horizontal Dipoles

Obtaining the new phase retardation for the horizontal dipoles is similar to that

presented for the case for the vertical dipoles. The phase retardation for the differential

line currents given in Table E.1 requires the sin cos sin substitution. For

the ,cos will also have to be substituted as the horizontal dipoles are perpendicular

to the normally vertical orientation definition as given in many textbooks. Suitable

coordinate transformations are necessary to obtain the new substitution.

Consider the electric field for the Hertzian dipole equation in an arbitrary orientation in

space is given written as [14], [45]

0

20 0

3 20

1 1ˆ ˆ ˆ ˆ3

4

E r p r r r p p j rj e

r r r, (E.23)

in which r is the unit direction vector of distance r and p vector representing the

dipole moment. In the far-field (FF), by ignoring the near-field terms 31 r and 21 ,r

(E.23) becomes

0

2FF 0

0

1ˆ ˆ

4

E r p r j rer

. (E.24)


Appendix E 151

For an electric dipole, the dipole moment can be defined as [14]

p dQ , (E.25)

in which d represents the dipole length given by

ˆd a xd . (E.26)

Note that (E.26) defines the horizontal dipole in the ax direction because our dipoles

shown in Figure E.3 is oriented in the direction of the x axis.

Furthermore, the r location vector may be defined as

ˆ ˆr a r . (E.27)

Hence, the concerning vector ˆ ˆ ˆ a a ar x r regarding the vector orientation only needs to

be evaluated. It is easier to express vector ar in terms of Cartesian components for the

evaluation and then transform back to spherical coordinates via vector projection to

yield simpler expressions.

The vector transformation from Cartesian components is given by

ˆ sin cos , sin sin , cos ar , (E.28.a)

ˆ 1, 0, 0ax , (E.28.b)

noting that a vertical Hertzian dipole given in classical electromagnetics is directed

along the +z-axis and a horizontal orientation by convention would be along the +x-axis

where 0 reference starts. Therefore, evaluation using Mathematica generated

2 2 2

2

cos sin sin ,

ˆ ˆ ˆ -cos sin sin ,

-cos cos sin

a a ar x r . (E.29)

The coordinate transformation from Cartesian to spherical in matrix form as given in

[14] is

sin cos sin sin cos

cos cos cos sin sin

sin cos 0

r x

y

z

E E

E E

E E

. (E.30)


Appendix E 152

Contribution from the horizontal dipole comes not only from the component but from

the component as contribution from the r component is zero. The transformation is

done by projections or using dot products of each spherical component given by (E.30)

with the vector ˆ ˆ ˆ . a a ar x r Hence,

ˆ ˆ ˆ ˆ 0 a a a ar x r r , (E.31.a)

ˆ ˆ ˆ ˆ cos cos a a a ar x r , (E.31.b)

ˆ ˆ ˆ ˆ sin a a a ar x r , (E.31.c)

where ˆ ,ar ˆa and ˆa are given by [14]

ˆ sin cos , sin sin , cos ar , (E.32.a)

ˆ cos cos , cos sin , sin a , (E.32.b)

ˆ sin , cos , 0 a . (E.32.c)

Equations (E.31.a) and (E.31.b) gives the required transformation substitution for

.cos

The modifications to the planar RE contributions due the line currents can be

summarised below.

Line Currents

sin cos sin Phasing along the line

cos cos h h Phase delay between opposite dipoles

cos cos , component

sin , component

cos Horizontal dipole

0

0

0 0

lossy

sin cos0

0

2 2 2 20

ˆcos cos sin cosˆ2

sin cos cosh

sin cos sinh

sin cos

j rL S

j lL C

C L

h VeE

r D

Z j Z l e

Z j Z l

, (E.33.a)


Appendix E 153

0

0

0 0

lossy

sin cos0

0

2 2 2 20

ˆsin sin cosˆ2

sin cos cosh

sin cos sinh

sin cos

j rL S

j lL C

C L

h VeE

r D

Z j Z l e

Z j Z l

. (E.33.b)

E.2.1.3 Summary of Derivations

Table E.2 presents a summary of the RE field contributions for any arbitrary

observation point in the upper hemisphere.

Description Complete Microstrip RE Model (RE-Approximation Model)

End Segments Field

00

sin cos

0

lossy

ˆ coshsinˆ2 sinh

j lj rCE S

L

Z l eh VeE j

r D Z l

(E.34)

00

2 2 2 2lossy 0

ˆsin 1ˆ 12 sin cos

j r PP S

r

h Ve FE j

r D (E.35.a)


0 sin cos0

0

sin cos cosh

sin cos sinh

j lPC L

L C

F Z j Z l e

Z j Z l (E.35.b)

00 0

2 2 2 2lossy 0

ˆcos sin cos cosˆ2 sin cos

j r LL S

h Ve FE

r D

(E.36.a)

00 0

2 2 2 2lossy 0

ˆsin cos sinˆ2 sin cos

j r LL S

h Ve FE

r D

(E.36.b)Differential

Line Currents

0 sin cos0

0

sin cos cosh

sin cos sinh

j lLL C

C L

F Z j Z l e

Z j Z l (E.36.c)

00 0

2 f

c c

(E.37.a)

eff0 r (E.37.b)Wave Constants

j (E.37.c)

lossyD Term 2lossy cosh sinh C S L C S LD Z Z Z l Z Z Z l (E.38)


2 2ˆ ˆ ˆ ˆ ˆ , for 0 , 0 22 E P L LE E E E E (E.39)

Table E.2 Summary of the microstrip RE field contributions.


Appendix E 154

E.3 Comparison of RE Model to Other Results

The approach used to develop RE from a microstrip used in [40] differs from the

approach presented in the previous section. The expressions for the fields obtained in

[40] are summarised in Table E.3.

Description Complete Microstrip RE Model in [40] (Leone RE Model)

Vertical Field

00

2

2

ˆsin 1 1ˆ2 1

1 1 x

j rv S

j lr S C S L

j k lj lL L

h VeE j

r Z Z e

e e

(E.40)

02

0 0

2

2

ˆcos sin 1ˆ 12 1

1 1x x

j rh S

j lr S C S L

j k l j k lj l

Lx x

h VeE j

r Z Z e

e ee

k k

(E.41.a)

Horizontal Fields

00 0

2

2

ˆcos sin 1ˆ2 1

1 1x x

j rh S

j lS C S L

j k l j k lj l

Lx x

h VeE j

r Z Z e

e ee

k k

(E.41.b)

Voltage Reflection Coefficient

,,

,

S L CS L

S L C

Z Z

Z Z

(E.42)

00 0

2 f

c c

(E.43.a)

eff0 r (E.43.b)Wave Constants

0 sin cos xk (E.43.c)


2 2ˆ ˆ ˆ ˆ , for 0 , 0 22 v h h

fE E E E (E.44)

Table E.3 Summary of the microstrip RE model in [40].

The expression for the fields in Table E.2 and Table E.3 are in general different.

However, it has been possible to show that for a lossless TL, i.e. 0, and 0 1h

the corresponding field expression in the two tables are identical. The key steps in the

derivation of this result are follows:

E‐A1 Assuming that 0 1,h find the lossless 0 RE model for Table E.2 in

order to have the same assumptions as the RE model presented in Table E.3.


Appendix E 155

E‐A2 Represent field component in Table E.3 to have a similar non-reflection

coefficient form as in Table E.2.

E‐A3 Obtain the vector sum of the component from step E-A1.

E‐A4 Obtain the vector sum of the component from step E-A2.

E‐A5 Compare the component from step E-A1 with the component from step

E-A2.

E‐A6 Compare the component from step E-A1 with the component from step

E-A2.

The results from step E-A1 are summarised in Table E.4 [2].

Description Field Components of RE-Approximation Model 0 1 and 0h

End Segments Field

00

sin cos

0

lossless

ˆ cossinˆ2 sin

j lj rCE S

L

Z l eh VeE j

r D jZ l

(E.45)

00

2 2 2 2lossless 0

ˆsin 1ˆ 12 sin cos

j r PP S

r

h Ve FE j

r D

(E.46.a)


0 sin cos0

0

sin cos cos

sin cos sin

j lPC L

L C

F Z Z l e

j Z Z l

(E.46.b)

02

0 0

2 2 2 2lossless 0

ˆsin 1 cosˆ

2 sin cos

j r LL S

h Ve FE j

r D

(E.47.a)

00 0

2 2 2 2lossless 0

ˆcos sinˆ2 sin cos

j r LL S

h Ve FE j

r D

(E.47.b)Differential

Line Currents

0 sin cos0

0

sin cos cos

sin cos sin

j lLL C

C L

F Z Z l e

j Z Z l

(E.47.c)

losslessD Term 2lossless cos sinC S L C S LD Z Z Z l j Z Z Z l (E.48)

Table E.4 Summary of the field components from Table E.2 under the conditions 0 1h and 0.


Appendix E 156

The results from step E-A2 are summarised in Table E.5 [2].

Description Field Components of Leone RE Model (Non-Reflection Coefficient Form)

Vertical Field

0

0

0

lossless

sin cos

ˆsin 1ˆ2

cos sin

j rv S

r

j lC L

h VeE j

r D

Z l e jZ l

(E.49)

02

0 0

2 2 2 2lossless 0

ˆcos sinˆ 12 sin cos

j r Lh S

r

h Ve FE j

r D

(E.50.a)

00 0

2 2 2 2lossless 0

ˆcos sinˆ2 sin cos

j r Lh S

h Ve FE j

r D

(E.50.b)Horizontal

Fields

0 sin cos0

0

sin cos cos

sin cos sin

j lLL C

C L

F Z Z l e

j Z Z l

(E.50.c)

losslessD Term 2lossless cos sinC S L C S LD Z Z Z l j Z Z Z l (E.51)

Table E.5 Summary of the field components from Table E.3 in the non-reflection coefficient form.

Under the conditions 0 1h and 0, it follows directly from the expressions for

the component of the electric field given in Table E.4 and Table E.5 that

ˆ ˆ L hE E . (E.52)

For the component, the following results can be obtained from the expressions in

Table E.4 and Table E.5

ˆ ˆ ˆE v EPE E E , (E.53.a)

ˆ ˆ ˆL h LPE E E , (E.53.b)

0

0

0

lossless

sin cos

ˆsin 1ˆ 12

cos sin

j rEP S

r

j lC L

h VeE j

r D

Z l e jZ l

, (E.54.a)

020 0

lossless

2 2 2 20

ˆsin cos 1ˆ 12

sin cos

j rLP S

r

L

h VeE j

r D

F

, (E.54.b)


Appendix E 157

in which

ˆ ˆ ˆEP LP PE E E . (E.55)

From (E.53.a)–(E.55) we can show that

ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ

ˆ ˆ ˆ ˆ

ˆ ˆ

E L P v h EP LP P

v h P P

v h

E E E E E E E E

E E E E

E E

. (E.56)

Equation (E.56) confirms that the sum of the component for Table E.4 as well as

Table E.5 is the same.

Appendix F. Experimental Details for Chapter 6

Appendix F 158


This appendix present details on the RE experimental setup referred to in Chapter 6.

Additional details are also available as documented by the author in [9].

Obtaining the RE field through measurement requires a careful design and setup of the

experiment to be able to yield consistent and repeatable results. An illustration of a

basic RE experimental test setup is shown in Figure F.1. There are three main

components to the RE setup, excluding the PCB, which consists of the chamber,

antenna and spectrum analyser.

Figure F.1 An example for the basic RE experimental test setup.

The semi-anechoic chamber is a standard ETS-Lindgren FACT 3 with

4 dB performance that can support up to a maximum frequency of 18 GHz, [86]. Note

that an uncertainty of greater than 4 dB may be expected in the RE measurements due

to additional uncertainties arising from the equipment, connecting cables, etc.

Improvements have been made to the chamber especially on the ground plane to be able

to obtain the measurements shown in Figure 6.2 to Figure 6.14. The addition of floor

ferrite panels around the antenna region improves the semi-anechoic chamber’s

performance. Unwanted multipath REs near the vicinity of the receiving antenna are

absorbed by the additional ferrite panels.

Spectrum Analyser

TG

Recv

Conduit

Turntable Slots

Turntable Conduit

Cut Hole

Conduit

PCB

Attenuator

Cut Holes

Absorbers

Antenna

Antenna Mast

Panel

Observation oP

Semi-Anechoic Chamber

x y

z Ground Floor

Cavity


Appendix F 159

The antenna is a bilog x-wing type with a frequency range of 30 MHz to 2 GHz, [87].

The spectrum analyser is a HP 8595E with a frequency range of 9 kHz to 6.5 GHz,

[88]. The spectrum analyser has an inbuilt tracking generator (TG) and together with the

receiver (Recv) input, the RE for a specified band can be measured. Measurements with

the spectrum analyser has been conducted with an intermediate frequency bandwidth

and an average bandwidth of 30 kHz as a compromise between sweep time and

measurement accuracy.

Due to the inbuilt attenuator on the microstrip PCB test boards, a wideband RF

amplifier HP 8447F is used to amplify the TG signals from the spectrum analyser to

achieve sufficient dynamic range for the RE measurements [89]. The amplifier works in

the range of 100 kHz to 1.3 GHz and RE measurement bandwidth is chosen to be from

30 MHz to 900 MHz in order to work within the frequency limits of the equipment.

Tests have been conducted to ensure that the chosen band also yield RE measurements

in the linear operating region of the equipment.

It should be noted that simulation models were created in FEKO to assist in the

evaluation of the feasibility of introducing the RF amplifier in the measurement system

shown in Figure F.1. In addition, since there are many measurement sets to be obtained

for the RE, some automation is introduced to aide with the data collection using the

Agilent VEE software, [60], was introduced to aide in the data collection.

This appendix consists of three sections. Section F.1 presents the preparation of the

PCB microstrip boards for the RE measurement. Section F.2 presents the calibration

procedure. Section F.3 presents the actual RE experimental setup, additional to

discussions above.

F.1 Microstrip Board Preparations

Figure F.2 shows an example of the preparation of the back side of a populated

microstrip PCB for use in the RE measurement. Insulation tape is attached over the

SMDs before the application of the copper tape. Additional solder joints have been

made between the copper tape and the ground reference plane for better connectivity.

The use of the copper tape is to provide shielding from any unmodelled electromagnetic

sources that may couple into the circuit to affect the RE measurement. Furthermore, the

copper tape also helps to improve the ground reference plane integrity.


Appendix F 160

Figure F.2 A microstrip board setup for the RE measurement.

F.2 Calibration

The calibration routines are important procedures in the RE experimental setup. All test

equipment used has to be calibrated according to the standard operating instruction in

the operation manuals [86]–[89]. For example, the spectrum analyser has to be warmed

up for at least half an hour prior to the measurement and also with calibration performed

[88]. The HP 8595E spectrum analyser used has an internal built-in oven-controlled

crystal oscillator for a precision frequency reference so that better measurements can be

achieved [88]. Another aspect of the calibration is the loop calibration a term coined

following the experimental work conducted for the author’s Master’s thesis [P-1]. The

loop calibration method used for the Master’s has been superseded with a new loop

calibration method presented in this thesis. The new loop calibration method has two

parts, first, the calibration of the cables and RF amplifier and, second, using a 50

characteristic microstrip matched at the ports with 50 as a test standard radiator. The

first part will be referred as the conducted loop calibration and the second referred to as

the test standard loop calibration.

This section presents the procedures for the new loop calibration in subsection F.2.1 and

subsection F.2.2. Examples for the calibration factors and verification with a test

monopole for the new loop calibration are presented in subsection F.2.3.

Insulation Tape

Copper Tape

Solder Points for Better Connection and to Provide Shielding

Exposed Ground Reference Plane


Appendix F 161

F.2.1 Conducted Loop Calibration

The conducted loop calibration forms part of the new loop calibration which can be set

up as shown in Figure F.3. The setup is only an example, but the method can be applied

to a similar configuration.

Figure F.3 Conducted loop calibration setup.

The conducted loop calibration, in general terms, is defined to be the frequency

characterisation of all connecting cables and interconnecting systems in the path of the

tracking generator (TG) to the receiver (Recv) used in the final RE setup. Note that the

interconnecting systems can include amplifiers, attenuators, etc. Specific to Figure F.3,

the conducted loop calibration, ,CL can be modelled as

dB All Cables dB RF Amplifier dBCL . (F.1)

Spectrum Analyser

RF Amplifier TG

Recv Inside

Chamber Outside

Chamber

Copper Wool in Between Gaps

All Cables are 50 Quality Shielded Cables

Ferrite Choke on Feed Cable

Mating Connector


Appendix F 162

The following steps outline some important considerations in the conducted loop

calibration procedure:

F‐A1 Use ferrite chokes along the path of the interconnecting cables to minimise

common-mode currents that may couple onto the cables.

F‐A2 Where possible, seal off or shield any unused conduits feeding into the

chamber and keep the chamber door close to prevent coupling from any external

sources of interference. This step is a function of the electromagnetic environment

which may or may not be a necessary step.

The basic idea to steps F-A1–F-A2 is to conduct the conducted loop calibration in

its intended electromagnetic environment for RE measurements with the least

disturbance from the final setup and to prevent any potential external coupling into the

system.

F.2.2 Test Standard Loop Calibration

The test standard loop calibration forms part of the new loop calibration which can be

setup as shown in Figure F.4.

Figure F.4 Test standard loop calibration setup.

The test standard loop calibration is the procedure used to obtain the RE difference in

dB between the test standard and a theoretical model. In general, the RE differences

DV can be defined as

model stddB dB V m dB V mDV E E (F.2)

Spectrum Analyser

RF Amplifier TG

Recv Inside

Chamber Outside

Chamber

All Cables are 50 Quality Shielded Cables

Test Standard

Antenna

Optional Attenuator Radiated

Emissions


Appendix F 163

in which modelE and stdE are the electric fields from the model and test standard

respectively.

Note that in (F.2), the stdE is an RE measurement so it is a function of the antenna

factor, ,AF and the conducted loop calibration factor, ,CL which is given by

std stddB V m dB V dB m dBE V AF CL , (F.3)

in which stdV is the uncompensated measurement for the test standard.

The following steps outline some important considerations from the test standard loop

calibration procedure:

F‐B1 Follow the steps F-A1–F-A2 but with the test standard connected as

shown in Figure F.4.

F‐B2 Optional attenuators can be added into the system to reduce impedance

mismatch between interconnecting systems, provided the desired dynamic range is

maintained. Note that the factors from the attenuators have to taken into account in

(F.3)

The selection of an appropriate test standard radiator is important. In this thesis, a

microstrip with a characteristic impedance of 50 and with its input and output ports

also matched to 50 has been chosen to obtain std .E The 50 test standard has been

chosen because the RF equipment used are all referenced to the 50 standard,

therefore the various interconnecting systems are all matched to 50 (i.e. no signal

reflections, maximum power transfer, etc).

F.2.3 Calibration Factors and Verification

The calibration factors from the new loop calibration and their verification are presented

in this subsection.

F.2.3.1 Test 50 Standard and Monopole Specifications

Table F.1 presents specifications for the 50 microstrip used as a test standard and the

test monopole as shown for the verification of (F.2). In the table, the superscript of

50 and mono are used on the variables referenced 50 microstrip and monopole

respectively.


Appendix F 164

50 Microstrip Monopole

Microstrip Length 50 204 mml Monopole Length mono 5 mml

Microstrip Width 50 2.5 mmw Monopole Radius mono 2.4 mma

Dielectric Height 50 1.5 mmh Monopole Feed Gap mono 1 mmd

Permittivity 50 4.8r Optional Attenuation mono

ext 12 dBK

Loss Tangent 50tan 0.0224

GND PCB Dimensions 250 mm 50 mm GND Sheet Dimensions 300 mm 300 mm

Table F.1 50 test standard and monopole test specifications.

For the microstrip model, the microstrip is assumed to have zero trace thickness and

assumed to have a typical conductivity of typ 7Cu 5.8 10 m for the calculations of

the skin depth loss contribution using the analytical approach [7], [R-1]. Also note that

additional details on the analytical models for the 50 microstrip and the monopole

are available in [P-2].

F.2.3.2 Calibration Results

The RF amplifier HP 8447F used has a 25 dB gain maintained over the frequency

range of interest with the maximum chosen to be 900 MHz for the RE measurements

[89]. For the conducted loop calibration, the TG is set to a power of 10 dBm. The

characteristics for the cables and RF amplifier minus the 25 dB gain is shown in

Figure F.5.

50w

50h

50l monol

monod

monoa


Appendix F 165

Figure F.5 Conducted loop calibration capturing the characteristics of all cables and the RF amplifier.

Figure F.6 show the bilog antenna factor for used in the compensation of the RE results.

Figure F.6 Bilog antenna factor obtained from the manufacturer for the actual antenna used.

0 100 200 300 400 500 600 700 800 9000

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Frequency (MHz)

Com

pen

sati

on (

dB

)

CL

0 100 200 300 400 500 600 700 800 9000

2.5

5

7.5

10

12.5

15

17.5

20

22.5

25

Frequency (MHz)

Com

pen

sati

on (

dB

/m)

AF


Appendix F 166

Figure F.7 shows the RE for the 50 microstrip test standard. The raw RE

measurement has been compensated with the conducted loop calibration as shown in

Figure F.5 and also the bilog antenna factor AF as shown in Figure F.6. It should be

noted that the RE sample point is taken at the spatial location

, , 2.6 m, 0, 1.5 mo x y z oP A A A P which is consistent with the oP of the 70

microstrip PCB test setup. Also, the TG is set to a power of 10 dBm without any

attenuator introduced into the setup since the microstrip test standard is well matched to

the external 50 system. Hence, there is little to no mismatch for the RE loop

calibration setup. Figure F.7 is used to generate the additional compensation that are

applied to all the RE measurements shown in Figure 6.2 to Figure 6.14.

Figure F.7 RE vertical polarisation: The RE of the 50 microstrip test standard.

0 100 200 300 400 500 600 700 800 9000

10

20

30

40

50

60

70

80

90

Frequency (MHz)

Ele

ctri

c F

ield

Mag

nit

ude

(dBV

/m)

Analytical ModelMeasurement


Appendix F 167

The RE loop calibration/compensation result is shown in Figure F.8.

Figure F.8 Test standard loop calibration: Difference of Figure F.7 curves.

From the compensation factors shown in Figure F.5, Figure F.6 and Figure F.8, the

compensated electric field measurement E given a test radiating source V can be

obtained as,

dB V m dB V dB m dB dBE V AF CL DV . (F.4)

To show that the method is reliable, the compensation defined in (F.4) has been applied

to the monopole radiator. Good agreement between the predicted field and compensated

field measurement is clear from Figure F.9. The comparisons with the FEKO curve

were generated with the FEKO monopole model shown in Figure F.10. The RE sample

point is taken at the spatial location , , 2.6 m, 0, 1.5 mo x y z oP A A A P as for the

50 microstrip test radiator.

0 100 200 300 400 500 600 700 800 900-10

-8

-6

-4

-2

0

2

4

6

8

10

Frequency (MHz)

Com

pen

sati

on (

dB

)

DV


Appendix F 168

Figure F.9 RE vertical polarisation: Effect of the test standard loop calibration on the monopole radiator.

Figure F.10 FEKO monopole model.

F.3 RE Experimental Setup

This section presents important considerations relating to the actual experimental setup

for the RE experiment. The key considerations help to ensure that repeatable as well as

reliable measurements can be achieved.

This section is composed of three subsections. Subsection F.3.1 describes the antenna

positioning for the observation point in the measurements setup. Subsection F.3.2

0 100 200 300 400 500 600 700 800 9000

10

20

30

40

50

60

70

80

90

100

Frequency (MHz)

Ele

ctri

c F

ield

Mag

nit

ude

(dBV

/m)

FEKOMeasurement: Without DVMeasurement: With DV


Appendix F 169

describes the test board interface to the reference plane. Subsection F.3.3 describes the

external chamber setup.

F.3.1 Antenna Positioning for the Observation Point

Figure F.11 shows the approximate location of the RE field sample/observation point.

Figure F.11 Actual ferrite floor tiles setup.

Some antenna will provide marking as shown above to aide in the setup of the antenna

positioning. If in doubt with the effective field observation location of the antenna, one

may consult with the antenna manufacturer. Furthermore, Figure F.11 shows a right

angle triangle in the plane of the coordinate origin O and the observation point .oP The

distances to setup the location of the bilog antenna is given from the geometry of the

right angle triangle 2 2 .r x zA A A For the RE test measurement setup, 2.6 mxx A

Test Board

Antenna

Approximate Coordinate Origin O

Observation Point oP

xA

zA

O

oP

rA

xDirection

xDirection


Appendix F 170

and 1.5 mzz A to yield 3 mrr A which has been used to compute the RE in the

theory. Also note that the bilog antenna is positioned in the vertical polarisation to

measure the largest field component from the RE test setup.

F.3.2 Test Board Interface to the Reference Plane

Figure F.12 shows the setup of the interface/jig for the various types of test

boards/radiators for the RE measurement setup.

Figure F.12 Test board interface to the reference plane.

The interface is constructed using copper shim which can accommodate the microstrip

test boards and the monopole radiator even for the calibration procedure. The primary

copper shim has copper tape on the inner and outer perimeter. On the inner perimeter,

the copper tape has the sticky side exposed as shown in partial view in Figure F.12. The

sticky side is to couple with the metallic surface from a test board/radiator. The purpose

of a secondary copper shim is used to further extend the primary copper shim when

Copper Tape Around

Perimeter

Primary Copper Shim

Test Board Feed Cable

Copper Tape Over Gaps

Secondary Copper Shim

Sticky Side of Copper Tape

Strip Back Paint


Appendix F 171

interfacing with a special 50 characteristic microstrip board since its local reference

plane is unable to make proper full-perimeter contact with the primary copper shim.

Note that the painted surface on the turntable has been stripped back to allow for better

copper tape adhesion between the primary copper shim and chamber ground. The

design of the interface considers the aspects of good connectivity of the various

reference planes as well as easy changeover of the various test boards for experimental

productivity.

Figure F.13 shows examples for the interfacing of the various test radiators. In some

instances, some masking tape has been used to provide supplemental adhesion between

a test board and the copper shim. Thus, better connection between the local reference

plane on the test board and copper shim can be ensured.

Figure F.13 Examples of interfacing various test radiators.

Monopole

50 Characteristic

Microstrip

Masking Tape 70 Characteristic

Microstrip PCB Test Board


Appendix F 172

Each type of test radiator shown in Figure F.13 consists of a local reference plane. For

example, for the 50 characteristic microstrip, the PCB has its reference plane

extended using copper shim by direct soldering on the underside. For the 70

characteristic microstrip investigated in this thesis, it is not practical to employ the

method used for the 50 characteristic microstrip of attaching the reference plane. The

method of using the primary and/or secondary copper shim coupled with the exposed

copper strip around the perimeter of each microstrip test board as shown in Figure F.14

has been used.

Figure F.14 The copper strip around the 70 characteristic microstrip PCB test board.

F.3.3 External Chamber Setup

Figure F.15 shows a picture of the actual setup external to the chamber. Good low-loss

cables are used for connection between the various equipment and chamber. Where

possible, the shortest available cables are used. Any access ports for cable connections

to the chamber have been terminated with 50 to leave nothing floating. In addition,

which is not shown in Figure F.15 any exposed conduits that are unused have been

sealed to prevent electromagnetic field coupling into the ground floor cavity as shown

in Figure F.1.

Copper Strip Perimeter


Appendix F 173

Figure F.15 External chamber setup.

Low-Loss 50 Cables Used

Spectrum Analyser

RF Amplifier

TG

Recv

Unused Access Ports Terminated With 50

Conduit

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