SH-3 WinCE engine Semester Thesis WS 98/99beutel/pub/19990205_wince_report.pdf · runden Sie diesen...

SH-3 WinCE engineSemester Thesis WS 98/99

Zurich¨Electronics Laboratory (IfE)

Jan Beutel, Tobias BöschElectronics Laboratory, ETH Zürich

Phone: +41-1-632 51 44FAX: +41-1-632 12 10

e-mail: [email protected]

5th February 1999

Contents

Introduction vii

1: Overview on PDA Systems 1

2: Hitachi Super-H Architecture 3

3: WinCE Engine Concept 73.1 WinCE Engine Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . 73.2 WinCE Engine Hardware Set-Up . . . . . . . . . . . . . . . . . . . . . . 93.3 Comparison to other PDA systems . . . . . . . . . . . . . . . . . . . . . 10

4: Components and Advanced Packaging 134.1 Availability and Marketsituation . . . . . . . . . . . . . . . . . . . . . . 134.2 Chip Scale Packaged Semiconductors for the WinCE Engine . . . . . . 144.3 Oszillators and Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.4 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5: Substrate Technology 19

6: The µ-blox GPS-MS1 23

A: Appendix Project Description 25

B: Appendix WinCE Engine System Specification 33

C: Appendix Hardware 45C.1 WinCE Engine Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . 46C.2 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

D: Appendix Software 53D.1 WindowsCE Development using EBX7709 . . . . . . . . . . . . . . . . . 53

i

Contents

D.1.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53D.1.2 How to compile a Windows CE development system . . . . . . . 54D.1.3 How to compile a Windows CE image . . . . . . . . . . . . . . . 54D.1.4 Adapting Windows CE . . . . . . . . . . . . . . . . . . . . . . . . 55D.1.5 How to transfer a Windows CE image to the EBX7709 . . . . . 55D.1.6 Debuging the image . . . . . . . . . . . . . . . . . . . . . . . . . . 56D.1.7 Connecting a WindowsCE device to a host computer . . . . . . . 56D.1.8 Lookup-tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

E: Additional Documentation 59

F: Contacts 61

ii

Tables

4-1 Size Comparison for Processor and Companion . . . . . . . . . . . . . . 144-2 Miniature oszillators and crystals . . . . . . . . . . . . . . . . . . . . . . 164-3 High density board-to-board connectors . . . . . . . . . . . . . . . . . . 17

5-1 DYCOstrate possible feature sizes . . . . . . . . . . . . . . . . . . . . . 205-2 WinCE Engine Design Features. . . . . . . . . . . . . . . . . . . . . . . 21

D-1 EBX7709 Serial Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 56D-2 DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57D-3 DB9 null modem pin out (two DTEs) . . . . . . . . . . . . . . . . . . . . 57

iii

Tables

iv

Figures

1-1 A GPS navigation system running proprietary software . . . . . . . . . 11-2 A WindowsCE PDA with PCMCIA video camera . . . . . . . . . . . . . 2

2-1 SH-3 capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2 HD64461 capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3-1 WinCE engine capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 73-2 Block Diagram of the WinCE Engine . . . . . . . . . . . . . . . . . . . . 83-3 Top View of the WinCE Engine with Components . . . . . . . . . . . . 93-4 The system board of a HP 620LX PDA (19 x 9 cm, twosided with mem-

ory daughtercard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103-5 The WinCE Engine form factor (96 x 35 mm, height 7,45 mm (left), 1,7

mm (right)) compared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4-1 Crossection of BLP and µBGA Packages . . . . . . . . . . . . . . . . . . 13

5-1 Crossection of a Rigid-Flex Substrate . . . . . . . . . . . . . . . . . . . . 205-2 Top View of the WinCE Engine Substrate . . . . . . . . . . . . . . . . . 215-3 Crossection of a bent Rigid-Flex Substrate with piggyback GPS-MS1

mounted over SMT Components . . . . . . . . . . . . . . . . . . . . . . 22

6-1 Piggybacked GPS-MS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236-2 GPS-MS1 integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

C-1 WinCE Engine schematic page 1 . . . . . . . . . . . . . . . . . . . . . . 46C-2 WinCE Engine schematic page 2 . . . . . . . . . . . . . . . . . . . . . . 47C-3 WinCE Engine schematic page 3 . . . . . . . . . . . . . . . . . . . . . . 48C-4 WinCE Engine schematic page 4 . . . . . . . . . . . . . . . . . . . . . . 49C-5 WinCE Engine schematic page 5 . . . . . . . . . . . . . . . . . . . . . . 50

v

Figures

vi

Zurich¨Technische HochschuleEidgenossische¨

Swiss Federal Institute of Technology ZurichPolitecnico federale di ZurigoEcole polytechnique federale de Zurich´ ´

Departement Elektrotechnik Institut für Elektronik

Wintersemester 1998/99

SEMESTERARBEIT

fürJan Beutel und Tobias Bösch

Betreuer: Andreas Thiel, ETZ H97Stellvertreter: Daniel Ammann, ETZ H97

Ausgabe: 19. Oktober 1998Abgabe: 5. Februar 1999

WinCE Engine

EinleitungDie Firma Hitachi bietet mit dem Prozessortyp SH-3 einen leistungsfähigen Prozes-sor mit geringer Leistungsaufnahme an. Im dazu angebotenen Companion-ChipHD64461 sind weiterhin eine Vielzahl von Peripherie-Funktionen wie z.B. LCD-, IrDA-, PCMCIA- und Analog Modem Interface integriert. Damit stellt dieser 2-Chip Chipsatz eine ideale Basis für einen High-Performance PDA (Personal DigitalAssistant) dar. Ziel dieser Arbeit ist das Design eines Miniatur-Moduls basierendauf MCM-Technologie, welches alle Kernfunktionen eines PDAs enthält. Durch diekleine Baugrösse des Moduls können im weiteren Verlauf der Entwicklung auchnoch Zusatzfunktionen wie z.B. GPS-Receiver und/oder eine Mobilfunkmodul (GSM,IS-95, etc.) in den PDA integriert werden, ohne dass eine Vergrösserung des PDAGehäuses notwendig würde.

Im Hardware Teil dieser Arbeit soll das Modul entworfen und designed werden.Falls es die leider recht langen Fertigungszeiten für MCM-Substrate zulassen, solldas Modul möglichst auch in Betrieb genommen werden.

Für den Hitachi SH-3 wird das Betriebssystem Windows CE der Firma Microsoftfavorisiert. Da dieser Prozessor bereits in einer grösseren Anzahl von Geräten amMarkt erhältlich ist, bestehen bereits umfangreiche Entwicklungsumgebungen.

Introduction

Da das am IfE entwickelte GPS-System ebenfalls einen Prozessor der Hitachi-SHSerie enthält, drängt sich die Frage auf, ob sich durch eine engere Integration beiderSysteme Baugrösse und Kosten verringern lassen.

Im Software Teil der Arbeit ist zunächst die Möglichkeit der Integration von Wind-wos CE und GPS-Applikation abzuklären. Anschliessend ist eine Entwicklungs-und Testumgebung für das Modul aufzubauen. Die Implementierung der ver-schiedenen Softwarekomponenten auf der Zielplattform stellt den Hauptteil der Ar-beit dar.

Aufgabenstellung Hardware Teil� Stellen Sie einen Zeitplan für Ihren Teil der Arbeit auf.

� Berichten Sie in einem kurzen Vortrag über Ihr Vorhaben (Termin siehe SADAWebseiten des IfE)

� Entwickeln Sie eine geeignete Partitionierung des Systems und bestimmen Siedie auf dem Modul zu integrierenden Komponenten.

� Entwerfen Sie das Schema des Moduls.

� Wählen Sie eine geeignete Substrattechnologie anhand der erforderlichen De-signrules aus.

� Erstellen Sie das Layout.

� Dokumentieren Sie Ihre Semesterarbeit mit einem ausführlichen Bericht undrunden Sie diesen mit einem kurzen Referat ab.

Aufgabenstellung Software Teil� Evaluieren Sie die Möglichkeit einer Integration von Windows CE und GPS-

Applikation auf demselben Prozessor. Berücksichtigen Sie insbesondere bere-its von der Firma SiRF geleistete Arbeiten auf diesem Gebiet.

� Stellen Sie einen Zeitplan für Ihren Teil der Arbeit auf. Bestimmen Sie denArbeitsablauf abhängig davon, ob eine Integration der GPS-Anwendung nachder vorausgehenden Abklärung vorgesehen ist.

� Berichten Sie in einem kurzen Vortrag über Ihr Vorhaben (Termin siehe SADAWebseiten des IfE)

� Stellen Sie eine Entwicklungsumgebung zusammen.

� Implementieren Sie die von Ihnen ausgewählten Software-Bausteine.

� Dokumentieren Sie Ihre Semesterarbeit mit einem ausführlichen Bericht undrunden Sie diesen mit einem kurzen Referat ab.

viii

Introduction

Durchführung der ArbeitAllgemeines

� In einer wöchentlich stattfindenden Sitzung soll der aktuelle Stand der Arbeit,die aufgetretenen Probleme sowie das weitere Vorgehen mit den Betreuernbesprochen werden.

� Im ETZ G66 steht ein Arbeitsplatz mit einer Sun-Workstation und einem PCzur Verfügung.

Abgabe� Geben Sie zwei unterschriebene Exemplare des Berichtes spätestens am

5. Februar 1999 dem betreuenden Assistenten oder seinem Stellvertreter ab.Diese Aufgabenstellung soll vorne im Bericht eingefügt werden (vgl. Beilage,Kap. 1.7 Bericht).

Beilagen� Wegleitung für Semester- und Diplomarbeiten am Institut für Elektronik,

ETH, tha 4/97.

ix

Introduction

x

Introduction

IntroductionThis report outlines a project that was done in cooperation with the Electronics Laband µ-blox AG. It was our goal to develop a prototype design for a WindowsCEcore system that could be used by OEM customers to integrate a PDA system fornavigation purposes. It was our intention to integrate a GPS functionality and to fitthis prototype into the existing product range of µ-blox AG.

For the moment beeing this is only a design study, but negotiations for a prototypeproduction as well as potential customers are underway. We wanted to demonstratethe benefits from modern high density integration for core systems that could beassembled much like building blocks by customers that have no or little knowledge ormeans of the technology involved. Apart from that, novel and emerging technologieswere to be used where available, applicable and last but not least cost efficient. Wetherefore set out to implement the design on a rigid-flexible multilayer board withmodern BGA and CSP packages were available, smallest form factor and energyconsumption.

The GPS-MS1 OEM receiver was integrated into the system by stacking this moduleover the other components on the same board.

During the work on this project numerous interested parties contacted us, or µ-bloxAG and we are well assured that in the future this will be more than only a mereprototype.

Zürich, 5th February 1999

Jan Beutel

Tobias Bösch

xi

Introduction

xii

1Overview on PDA Systems

Modern PDA systems range in price from a few hundred dollars to over 2000 dollarsand incorporate different functionality. Paging devices, short message services, dig-ital diaries with or without alarm systems, communication equipment, organizers,notepads, almost fullgrown office applications, specialized database access services,color graphics, video in and out and of course an evergrowing number of applicationsthat interface to the internet or other communication services are integrated intowristwatches, matchbox sized clip on gadgets up to almost notebooksize products.

Figure 1-1A GPS navigation system running proprietary software

The Windows CE operating system is showing evergrowing importance, since users

1

Chapter 1: Overview on PDA Systems

do not need to change their habits and ways of working when away from the office.

Figure 1-2A WindowsCE PDA with PCMCIA video camera

Up to now communication capabilities of PDA systems are limited to serial orinfrared links to host PC’s or connection to GSM datalinks with speeds of up to9600 baud. Most of these links require extra hardware either fit into connectioncable assemblies or PCMCIA cards. High datarates and easy to use plug and playinterfaces are not yet available, but are under development, such as the upcomingBluetooth (http://www.bluetooth.com) standard.

Many vendors are beginning to offer bundles of PDA, communication services andintegrated navigation solution. These packages usually consist of different hardwareparts (GSM phone or GSM PC-card, PDA, GPS receiver) as well as proprietarysoftware and databases. But the PDAs on the market today are either clumsy orlack the performance and memory needed to support ample navigation databases ordynamic upload via high speed communication links on demand. Services supplyingthese database services for DGPS, or regional navigational data of higher precisionthat can be incorporated on demand when precision is necessary are beginning togrow. One sample idea would be a transeuropean hotel guide that holds a databaseof major cities and can be updated either with time variant, regional updates to thedataset or incorporate more rural sites on demand. So the automatic booking andpayment via electronic datalinks is only a glimpse away.

The future will have more and more of these services available with the user beingable to chose from a variety of different types, price and qualities of services. Visionslike to emphasize that one device incorporating data, communication, speech, video,navigation and possibly others will be incorporated into one wearable device,available to everyone and everywhere.

2

2Hitachi Super-H Architecture

The Hitachi Super-H Architecture is a RISC system designed for use with theWindows CE system. It consists of the SH-3 and SH-4 RISC CPU families and theHD64461 companion chip. The SH-3 family operates at up to 133 MHz. The SH-4series at up to 200 MHz offering up to 360 MIPs. The SH-3 offers the followingfeatures:

� 32-bit internal data paths

� RISC type instruction set

– Instruction length 16 bit

– Load-store architecture

– Delayed branch instructions

� Instruction execution time: one instruction/cycle

� MMU allowing 4 GBytes of logical address space

� Physical address space divided into six areas, maximum 64 Mbyte addressspace each (area 7 is used for internal I/O, area 8 is reserved)

� Bus size 8/16/32 bits, can be set per area

� Number of wait cycles can be set per area

� SRAM, DRAM, SDRAM and burst ROM can be connected

� 8-kbyte cache memory, mixed instruction/data

� Real time clock: clock, calendar and alarm functions

� 3 serial communication interfaces

� DMA controller

3

Chapter 2: Hitachi Super-H Architecture

– 4 channels

– Burst mode and cycle-steel mode

� A/D converter

– 10 bits � 4 LSB, 8 channels

– Conversion time 10 �s

– Input range: 0 - Vcc

� D/A converter

– 8 bits 4 LSB, 2 channels

– Conversion time 10 �s

– Output range: 0 - Vcc

Figure 2-1SH-3 capabilities

The HD64461 offers most of the additional features nessecary to get a working PDA:

� LCD Controller

– 256 out of 256K colors maximum

4

– Display resolution max. 640 x 480

� PCMCIA controller

� IrDA interface

� UART controller

� AFE control signal processing

Figure 2-2HD64461 capabilities

5

Chapter 2: Hitachi Super-H Architecture

6

3WinCE Engine Concept

3.1 WinCE Engine CapabilitiesThe WinCE Engine is designed as small, but powerful core system for PDA’sand navigation systems running the Microsoft windows CE operating system. Themodule can easily be adapted to one’s needs by fitting a few external componentsand is capable of supporting the features illustrated in figure 3-1.

LCD & Touchscreen

PC-Slot

V.34bis Modem & Audio

Serial & IrDA

PDA

Global Positioning System

Figure 3-1WinCE engine capabilities

Navigation systems rely on maps to be useful. Other applications like tourist guides

7

Chapter 3: WinCE Engine Concept

need pictures, sounds and animations to make their printed counterparts obsolete.All these data needs a lot of space, even compressed.

The WinCE Engine offers 32 Mbyte of internal flash and 64 Mbyte of DRAM to holdsuch data and the operating system. If more space is needed more flash can be addedto the system on standard PCMCIA cards. This makes it possible to sell or rent localmaps on flash cards, which can be inserted into the system as needed. The data inthe flash should be compressed. The SH-3 running at 80 MHz internally is capableof decompressing it on the fly. Slide shows could also be decompressed to the RAMprior to start to make the processor resources otherwise used for decompressionavailable for fancy animations or sound effects.

SH770915x15mm

Flash 128M9,96x16,3mm

9,96x16,3mFlash 128M

SDRAM 256M

8x16mm FBGA11,8x22,3mm TSOP54

SDRAM 256M


HD6446117x17mm

11,8x21,04mmDRAM 64M

Reset

Clock

2x PCMCIA

Serial IO

IRDA Support

Analog Modem Frontend

Color 640x480 LCD

GPS MS1

Touchscreen

PeripheralsWinCE EngineFigure 3-2Block Diagram of the WinCE Engine

Mobile, leightweighted applications have to run on small batteries. Power consump-tion is therefore critical. The WinCE Engine runs on a single 3.3 V power supply,eliminating costly voltage transformations and enabling different low poer operationmodes.

The WinCE Engine offers accelerated color graphics with resolutions up to 640 by480 pixels. A maximum of 256 out of 256K colors can be displayed simultaneously.It supports LCDs only. A touchscreen can easily be fitted. It is possible to add amatrix-scan keyboard. However for the kind of application the module is designedfor, a keyboard is not a must. Although a few quickjump buttons can sure add toan effective userinterface. Most PDAs have no mouse or trackball although such adevice could be connected via serial or analog I/O.

A PDA that can not be synchronized with a networked workstation, running somesort of meeting maker tool, scheduler or project management software, is useless.

8

3.2. WinCE Engine Hardware Set-Up

Synchronization can be done in different ways, using serial cable connections orIrDA. A mobile user might want to use a modem and the PSTN or the internetto access his data or upload newly acquired geodata. A serial transceiver, anIrDA transceiver or an analog modem frontend (AFE) respectively are the onlycomponents needed externally to make this work.

Figure 3-3Top View of the WinCE Engine with Components

The module is small and integrated on a flexible carrier that can be adapted inform factor. It can be attached to the back of a LCD to form a minimum system,integrated onto a bigger pcb to form a feature rich system or sewed into a belt tomake it wearable.

Running Winodws CE makes a lot of software available for the PDA. This softwareoffers the same look and feel users are accustomed to from their desktop systems.

3.2 WinCE Engine Hardware Set-UpThe WinCE Engine was designed in close connection to the EBX7709 referenceplatform supplied by Hitachi. This would enable a fast end efficient process foroperating system adaption and debugging on the prototypes. A general overviewof the system components and interfaces available is given in figure 3-2. A moredetailed specification of the interface as well as pinouts and block diagrams of thefunctions incorporated is given in the appendix section.

As mentioned above the WinCE Engine is integrated on a flexible carrier. Tofacilitate production the components are mounted on the upper side only.

On the left (see figure 3-3) side the GPS-MS1 is mounted together with the SH-3processor and the flash memory devices. Due to their small height these threepackages can be placed under the GPS-MS1. On the right the companion chiptogether with the SDRAM, the graphics-memory and the connectors reside. The twosides are parted by a zone without any components, where the module stays flexibleand therefore can be bent.

9


The main clock is placed next to the SH-3. The clock signal of 25 MHz is distributedto the flash chips, the companion chip and the SDRAM. The companion chip hasgot two oscillators on its own, one to clock the graphics-DRAM and the other forthe serial driver and the analog modem frontend control unit. These two oscillatorswere placed as close as possible to the respective pins to enable good signal quality.

The 3.3V supply power is spread over various pins on the two connectors anddistributed via a ground and vcc plane.

3.3 Comparison to other PDA systemsA comparsion to an available Window CE PDA (HP 620LX) shows that an integrationwith chip sized and FBGA packages can reduce form factor by 1:5. Many MCMdesigns have shown a similar characteristic of downscaling by about a factor 4.

Figure 3-4The system board of a HP 620LX PDA (19 x 9 cm, twosided with memory daughtercard)

Figure 3-5The WinCE Engine form factor (96 x 35 mm, height 7,45 mm (left), 1,7 mm (right))compared

10

3.3. Comparison to other PDA systems

The fact that the WinCE Engine needs to be integrated into a further daughterboardwith at least power management, I/O interface converters and display power gener-ation can be taken into account since the WinCE Engine design mounts componentsonly on one side of it’s 96 x 35 mm form factor and not on both sides such as on the19 x 9 cm HP 620LX shown above.

11


12

4Components and Advanced

Packaging

4.1 Availability and MarketsituationNumerous hardware vendors and semiconductor companies are developing newpackaging technologies that try to minimise cost, size, weight and signal loss whilestill easy to assemble with standard SMT processes.

The direct use of bare dies is not yet well established due to problems in handlingof the unpackaged semiconductors, quality, test and the everchanging size andprocesses used. Only specialized companies that have the required know how andequipment can afford to implement designs with bare dies bonded on substrates forconsumer and mainstream products. The risk of not beeing able to receive so called‘‘Known Good Dies’’ (KGD) that are tested and the availability of the same dies overthe whole product lifetime pose yet unsolved problems. Typical product liefcycles formemories are only a few months before die shrinks take place and often these do notonly call for a new bonding process but also for a whole redesign of the substrates,the dies are mounted on.

Figure 4-1Crossection of BLP and µBGA Packages

13

Chapter 4: Components and Advanced Packaging

Semiconductors fit in different types of packages that are only slightly larger thanthe actual die and enable to use the whole area of the package for connections andnot only the peripherals show evergrowing popularity. They all feature connectionswith either metal leads or solder balls that can be assembled much like normalSMT components and soldered in a reflow process. Ball Grid Arrays, Chip SizedPackages (another name for the little brother of the BGA), Bottom Lead Packages(that have the leads under the die, but no solderballs) are all device types currenttoday. Pitches for the connections and/or solderballs range from milimeters to 0.5and 0.3 milimeter, similar to other fine pitch packages such as SSOP, LQFP andothers.

Most semiconductor companies have these advanced packages in their productportfolio, but it is very difficult to receive actual samples and the informationrequired for design. Slowly as the acceptance of these new devices is growing,companies such as Intel support customers with application notes, migration guidesand dedicated upgrade paths for their new products.

In general new packages are only applied to new products. This results in very longlead times from the development of new packages to the actual application in asystem design. Since the availability of these packages is not given on a broad basisthe acceptance of these packages is not very high.

4.2 Chip Scale Packaged Semiconductors for theWinCE Engine

� Hitachi SH7709 and Companion ChipThe Hitachi Super-H architecture SH7709 microprocessor and it’s HD64461companion chip are available in space saving FBGA or CSP packages. Forthese two devices different packaging technologies were chosen, that resultmainly in a different ballpitch (1mm vs. 0.5mm) and a larger package overheadfor the companion chip.

SH7709 HD64461Package T-FBGA1515-216(CSP216) LBGA208Package Dimension 15,0x15,0mm 17,0x17,0mmPackage Area 225mm2 289mm2

Lid Dimension 7,0x8,0mm 15,0x15,0mmLid Area 56mm2 225mm2

Die Dimension n.n. n.n.LQFP Dimension 30,0x30,0mm 30,0x30,0mmLQFP Area 900mm2 900mm2

Package Overhead 1:4 1:3

Table 4-1: Size Comparison for Processor and Companion

14

4.3. Oszillators and Crystals

� SDRAMNo SDRAM devices in CSP/BGA/BLP/BOC packages are available to date.Future devices like 256Mbit DRAMS, RAMBUS, etc. may be available inBLP, SHA, BOC or FBGA type packages from Q2/99 or Q3/99. Currentlyproduced DRAMs are not packaged in newly developed packages because ofthe nonexisting demand from the high volume customers (PC/workstationvendors) (quote: Micron, LGSemicon, Hitachi).

Currently available are 128 Mbit SDRAMS (available now) and 265MbitSDRAMS (Q2/99) in TSOP-II 54 pin packages (22,7 x 11,6 mm, 263mm2).

Micron may offer 256 Mbit SDRAMS in a BOC, FBGA or µ-BGA from mid of1999. Information on the new packages will be available from the beginning of1999 since actual die sizes for the 256 Mbit devices were not yet available.

� EDO-DRAMEDO-DRAMs are slowly fading out of the market. No new memory componentsare developed in this field. Future designs should only encorporate 64Mbit orlarger devices. These are available in TSOP-II 54 pin packages (22,7 x 11,6mm, 263mm2).

� Special Case for the HD64461 Companion Chip: Display MemoryThe 4Mbit of display memory that can be controlled by the HD64461 companionchip cannot be mapped into the main memory system of the SH-3 processor.SRAM in CSP or µ-BGA packages cannot be used because of timing constraints(60ns).

A future version of the chipset will be split into two components, one for I/Oand the other for the display with integrated memory. Information about thischipset will be available from Hitachi or ITE (the actual chipset developer) bythe end of the year.

Untill the display memory is integrated into the companion chip or a specialcustomer specific ASIC (only for high volume applications) is developed, anextra 64Mbit (for 256k x 16) EDO-DRAM must be used.

4.3 Oszillators and CrystalsA lineup of available Oszillators and Crystals for the desired frequency is given inthe following table. The system clock operates at a frequency of 26.7 Mhz and isdistributed to processor, companion chip and sdram devices. For the realtime clock,analog modem frontend and display controller additional crystals of 32kHz, 31MHzand 9,216Mhz were necessary.

For the frequencies necessary Epson and MicroCrystal products were most applica-ble due to the slim outline and low profile packages available.

15


Type fo [Mhz] X [mm] Y [mm] Z [mm] Area [mm2] Range [Mhz]

OszillatorsEpson SG-8002 CA PC/SC 26,6684 7,2 5,2 1,5 37,44 1-125 MhzEpson SG-710 ECK 7,5 5 1,5 37,5 1,8-67 MhzEpson SG-363 PCE 26,7 10,5 5,8 2,7 60,9Espon SG-8002 JC/PC 26,6684 10,5 5 2,7 52,5CrystalsEpson FA-365 6,2 3,7 1,4 22,94 14-41 MhzEpson MA-406 9,216 11,7 4,8 3,7 56,16Epson MA-406 31,0 11,7 4,8 3,7 56,16MicroCrystal CXAT 8,1 3,8 1,5 30,78 8-30 MhzMicroCrystal CX4V 32678 5 1,9 1 9,5Sunny SX-1 9,216 12,8 5 4,4 64Sunny SX-1 31,0 12,8 5 4,4 64Sunny SX-7 7,1 5,1 1,3 36,21 9,2-80 MhzSeiwa SCM309S 9,216 12,5 4,6 3,7 57,5Seiwa SCM309S 31,0 12,5 4,6 3,7 57,5

Table 4-2: Miniature oszillators and crystals

4.4 ConnectorsThe WinCE engine uses 200 pins I/O to distribute the system bus, all device I/O andthe PCMCIA interface to the outside. This large number of I/Os consumes quite alot of space, especially if distributed with one 200 pin connector only. Therefore itwas necessary to find a solution with ultra small fine pitch connectors.

When fine pitch connectors are used for such a high I/O count several problemsevolve.

� I/O count

� Lengthwise planarity of the connector

� Alignment of multiple connectors

� Area consumption vs. substrate size and cost

� Stacking height

� Routability

� Minimum pitch necessary for OEM daughterboard

� Availability

� Cost of connector assembly

Since the dual connector assemblies propagated by vendors such as Molex are onlya mere mounting bracket shipped with two single connectors (100x2) it is most

16

4.4. Connectors

Vendor Type Pins Pitch [mm] X [mm] Y [mm] Stack[mm] Area [mm2]

AMP 917734-1 100 0,50 28,8 4,2 120AMP 917734-1 100 0,80 39,20 6,0 234Molex 54137 100 0,50 28,9 5 1,5 144Molex 52991 80 0,50 23,80 5,3 3-4 129Molex 52760/53475 80 0,635 39,62 6,40 3-16 253Molex 54464 2x120 0,50 29,5 14 3 413JAE WR Series 80 0,50 21,5 4,2 4-9 90JAE WR Series 120 0,50 31,5 4,2 4-9 132JAE WR Series 2x100 0,50 29,1 15,2 4-9 442JAE IL-312 Series 100 0,50 26,7 4,25 2,5-3,5 113

Table 4-3: High density board-to-board connectors

feasible to mount the prototype boards with such a mounting bracket since 2x100dual assemblies are not available for the desired pincount.

The overall area used per pin doubles when considering 0,5 or 0,635 mm pitch. Sinceabout 2 years ago prices for the 0,5 mm pitch connectos have dropped from 200% toabout 120% over the next higher pitch (About 0,02-0,03 USD per pin).

17


18

5Substrate Technology

Modern high density substrates focus more and more on microvia technologies thatuse blind and buried vias and not throughole vias. They are not direct replacementsfor ordinary PCBs but offer greater possibilities in design. Flexible substrates canfit designs into different form factors and thus expanding the area of applicationdesignated.

The following points are primarily responsible for the cost of such a substrate:

� Primary:

– Size of the substrate (panel size, yield)

– Conductor width and gap

– Pad diameter

– Number of layers

– Multilayer build-up, support structure

� Secondary:

– Type of materials

– Special surface treatment, i.e. soldermask

– Number of mechanically drilled holes

– Mechanically machined cutouts

– Smallest I/O pitch, test, OEM application

Compared to drilled vias on conventional PCBs plasma etched vias do not add a pervia cost to the total cost since they are all formed in a single process step.

For this design a build-up technology using a DYCOstrate rigid-flex technology hasbeen chosen. These substrates are foil-like and can be adapted to specific factors

19

Chapter 5: Substrate Technology

Inner Layers typical [µm] limit [µm] leading edge [µm]

conductor spacing 80 70 50minimum via pad diameter 250 200 150minimum microvia hole diameter 90 70 50landing pad diameter 300 225 175Outer Layersminimum via pad diameter 300 250 200minimum microvia hole diameter 100 90 70Thicknesstotal thickness board 250 175–250 125–250dielectric separation layer 25–35 25–35 >15

Table 5-1: DYCOstrate possible feature sizes

(i.e. stiffness, vibration, heat, EMV) by layering with other materials such as metalor carbon based cores. The small feature sizes possible with this technology makesit possible to route such a dense design on two signal layers with single sidedassembly only. The outer metal layers are designed as planes, giving the substratestability, good thermal characteristics and distributing power and ground evenly toall components. Additionally these two planes (ground top, vcc bottom) act as anelectromagnetic shield for the signals distributed in the core.

4 Layer Rigidzone, BGA Components

Signal 1

1 Layer Flexzone 4 Layer Rigidzone, SMT Components

Plane 1

Signal 2

Plane 2

Figure 5-1Crossection of a Rigid-Flex Substrate

All components are mounted on the top side only and the pads necessary for thecomponents are surrounded by the ground-plane on this top metal layer (plane 1 infigure 5-1). No signals are routed on this outer metal layer, but all are submergeddirectly to signal layer 1 with a via buried in the middle of each smd pad (via-at-smd). This eliminates the use of a soldermask since the solder cannot flow awayfrom the copper pad during the reflow process.

Some core design features that were chosen among the designrules of DYCOstratesubstrates (see table 5-1) are listed in table 5-2. Out of the parameters given inthe ‘‘leading edge’’ column, only single values can be manufactured today, but

20

resulting in a strong increase in overall cost. Therefore it is close at hand to chosea technology that enables a successful routing on as few layers as possible, butlimiting the amount of leading edge design features.

Feature Value [µm]

line/space on signal layers 70outer layer vias 250inner layer vias 200min. ball/padpitch for components 500min. plane/pad clearance on top plane 250

Table 5-2: WinCE Engine Design Features.

All signals are routed on signal layers 1 and 2, ground and vcc pins are directlyrouted to either the bottom plane (vcc) using all three via types (top-layer1 layer1-layer2 layer2-bottom) in a staired or staggered manner or taken back up to the topplane (ground) using only two vias of type top-layer1 in a shot ‘‘U’’ type fashion.

Figure 5-2Top View of the WinCE Engine Substrate

To make the substrate fit into different form factors a flexible connection zone hasbeen placed in the middle allowing for a maximum 180 degree bend downwardsas illustrated in figure 5-2 and 5-3. This zone has only one conductor layer and adielectric carrier foil for stability purposes and cann be shortened up to a minimumbend radius of about 2 mm or enlongened to fit any other radius, and possiblysuch flat components as batteries or pc-card slots inbetween the two sections of thecircuit. Either a long and slim or a more square and cube sized form factor can beachieved.

The power is distributed from the right to the left section of the substrate on thesingle layer flex zone (the white middle part in figure 5-2) evenly spread betweenthe signal conductors, applying the necessary shield on the left and right of such

21

Chapter 5: Substrate Technology

Signal 2

Plane 2

Signal 1

Plane 1

Piggyback GPS

Figure 5-3Crossection of a bent Rigid-Flex Substrate with piggyback GPS-MS1 mounted over SMTComponents

signals as the system clock or data transmission lines. There are roughly 250 linescrossing this flexible section, about half of them are power lines.

22

6The µ-blox GPS-MS1

The GPS-MS1 can be piggyback mounted on the WinCE Engine. The SH7709’sserial port 1 is connected to the serial port 1 of the GPS-MS1. This allows theSH7709 to control all functions of the MS1 via serial I/O. The SH7709 does notcommunicate with the GSP1/LX DSP. It is not involved in positon calculationallowing for independent power down modes of the two devices.

The TEST_I pin of the MS1 is connected to a SH7709 GPIO. It can be driven highto download new firmware to the MS1 through the SH-3. It should be pulled low bythe SH-3 in normal operation.

Piggyback GPS-MS1

Figure 6-1Piggybacked GPS-MS1

Differential GPS Input can be provided at the RX_DGPS and TX_DGPS connectorpins. They are connected to the MS1’s serial port 0. The neccessary components toget the DGPS data must be provided externally.

The VBAT and 1PPS pins are presented on the connector. The VBAT allowsbackuping of the SRAM. The 1PPS can be used to make a LED blink.

23

Chapter 6: The µ-blox GPS-MS1

The GPS-MS1 can run in push-to-fix, trickle-power and standard mode. An OR-gateis included on the WinCE Engine. This enables the SH7709 to wake up the MS1. Inthis configuration it is possible to set the SH7709 in standby mode, while the MS1keeps track of the current position in push-to-fix mode. As soon as the SH-7709 iswoken up by the user, a position fix is available within 6 s.

SH7709 GPS MS1

TXD1

RXD1

RESET

TEST_I

WAKEUP_NR

X_D

GP

S

TX

_DG

PS

1PP

S

VB

AT

EXT_WAKEUP

Connector

Figure 6-2GPS-MS1 integration

The system is desinged to run with a passive antenna. It is however possible toconnect the VANT pin of the MS1 to the WinCE Engine’s Vcc net. This allows theuse of an 3.3 V active antenna.

24

AAppendix Project Description

25

Chapter A: Appendix Project Description

Hitachi SH-3 for Windows CEProject Description (Preliminary) –

Jan Beutel

6th November 1998

µ-blox agETZ/H97Gloriastrasse 35CH-8092 ZürichSwitzerlandhttp://www.u-blox.ch

1 Overview

The Hitachi SH-3 microprocessor features a 32-Bit RISC processor core, on-chip cache, mem-ory management unit and peripheral control. Together with the dedicated companion chipHD64461 it is designed to run the Windows CE operating system for handheld computingdevices. The extensive I/O capabilities of the companion chip with UART, IrDA, timer, in-terrupt controller, GPIO, PCMCIA interface, AFE (analog frontend for software modem) and640x480 color LCD simplify the integration of a whole system.

The SH-3 core has been available for quite some time and is well established for differenthandheld applications. The Hitachi-Microsoft alliance eases the evaluation through avail-ability of development tools and ready made software components.

The EBX7709 Reference Platform is a good foundation to start evaluating the performanceand capabilities of the SH7709, HD64461 twin components. The evaluation will includeoperating system specific requirements for a highly integrated processor module as well asapplication specific requirements for the I/O capabilities and on-board functionality as wellas the possiblities for external extensions.

An integration of the GPS-MS1 system, now running on a Hitachi SH-1 microprocessor, eitheras subsystem or fully integrated will be evaluated as well. There are numerous possibilitiesfor integrating the GPS-MS1 system into a mobile computing device: as daughterboardnext to a minimal microprocessor system based on SH-3/Windows CE and designed to serveonly the GPS functionality, as daughterboard on a more general SH-3/Windows CE systemwith capabilities for extension and upgrade (PCMCIA, GPIO, memory) or integrated into onemodule, possibly omitting the SH-1 microprocessor on the GPS-MS1 system.

2 Roadmap

The following steps and deadlines are rough guidelines.

1. System evaluation (from October 1998)26

Hitachi SH-3 for Windows CE (Preliminary) µ-blox AG, November 6, 1998 Page 2

� Functional system specification (October 1998)

� Evaluation of components and packaging (mid October 1998)

� Feasibility: cost, energy consumption, form factor (mid October 1998)

� Availability of components (end October 1998)

2. System design (November 1998)

� Block structure

� I/O and peripherals

3. Physical design (mid December 1998)

4. Prototype production (January 1998)

5. Test and demoapplications (February 1998)

3 Introduction to Ubiquitous Computing

Computing devices have contributed to extensive changes in professional as well as in ev-eryday life. Trends show, that the amount of devices is steadily growing with no end ofthe scale. Not only powerfull desktop computers, but also embedded systems and mobilecomputer systems are present everywhere. The market for small self contained systems ded-icated to special functions but able to comunicate interactively with other devices is evergrowing. Todays examples are mobile telephones (GSM), labtop and palmtop computers,pagers, mobile sales and remote control equipment, wristwatches with special functions,digital cameras and handheld navigation systems. Future products will be integrated into awhole, comprising several of the above mentioned functions into one device. With betterquality communication devices will not be in need to operate fully self contained but willuse offline and online services as well as network with other mobile devices to be remotelyaccessible at all times.

The focus for future application and devices lies on user interfaces, form factor, energyconsumption, the ability to communicate and thus to deploy external resources. Consumerdevices are getting more and more important and taking large market shares already, butthe prices for these devices are plunging. The component count as well as the form factorof components and systems are the most important factors.

4 System Specification

4.1 Hardware Specifications

The following lineup of hardware features is supposed to give a general overview of thecapabilities of the SH-3/HD64461 devices. It is for evaluation purposes and not meant tospecifiy the features of a future integrated device.

27



4.1.1 SH7709 32-bit microprocessor

� Features

– 32-bit RISC architecture

– 4 Gbyte logical address space

– 8 kbyte cache for mixed instruction/data

– Powersaving operating modes

– Bus and interrupt controller

– 2 Mhz timer

– Realtime clock

– Serial communication interfaces

– DMA controller

– 16 general purpose I/Os

– A/D and D/A converter

� Operation

– 3,3 Volt, 100 mA @80Mhz

– 15 µA in standby mode

– Sleep and Standby modes

� Form Factor

– Quad Flat Pack

– Ball Grid Array

– Chip Size Packaging

– Bonded Bare Dies

4.1.2 HD64461 companion chip

� Features

– SH7709 CPU interface

– Color LCD interface, 640x480

– CRT interface support

– EDO-DRAM 256kx16

– PCMCIA controller

– Analog frontend (AFE) for SGS Thompson modem

– General purpose I/O

– Timer

– IrDA support

– 16550 compatible UART

� Operation

– 3,3 Volt, 50 mA

– 35 µA in standby mode

28


– Standby mode with powermanagement of peripherals

� Form Factor

– Quad Flat Pack (208-pin LQFP)

– Ball Grid Array

– Chip Size Packaging

– Bonded Bare Dies

4.1.3 Other Devices

� Memory components

� Color display

� Touch screen input

� Communications I/O

� Audio I/O

� Power supply

4.2 Software Components

4.2.1 Windows CE Operating System

The Microsoft Windows CE operating System is designed to run on the SH-3, HD64461 pair,just like on the HP 620LX Plamtop PC. Various development systems and tools are available.

4.2.2 Peripheral Drivers

To be specified.

29



4.2.3 Software Modem

There are different possibilities to implement a software modem on the SH-3, HD64461analog frontend (AFE). One solution is offered by RAS Communication, called Native ModemTechnology. It features faxmodem capabilities with V.34/V.17 and eliminates the need forexternal components, reducing energy consumption for 600mW.

4.2.4 Application Software

Different vendors offer application software, ranging from simple tools like calculators,email, and notepads to Microsofts Word and Powerpoint as well as specialized navigationand handwriting recognition software. Porting software from the Windows 95 and NT plat-forms is simplified by using the Microsoft/Hitachi Toolchains.

4.3 Integration of Global Positioning System

The need for positioning information in handheld devices and miniature subsystems is ever-growing. The integration of GPS and mobile computing equipment is to be analyzed.

4.3.1 The GPS-MS1 System

The GPS-MS1 features full GPS functionality with various low power operation modes on aform factor of only 30x30mm. For operation only an external Antenna (active or passive)and a 3.3 Volt power supply are needed. The system is selfcontained and issues the GPSinformation via serial I/O. Several other general purpose I/Os can be defined for user specificpurposes.

4.3.2 GPS oriented Platform

In order to communicate with an enduser a consumer oriented navigation device needs ei-ther visual or acoustical I/O possibility, a database with navigation information (map) andcommunication abilities for updates, regional and time variant information. A GPS orientedsystem would comprise full navigation functionalities and database but only few other appli-cations (notes, SMS, email, calculator) or extension possibilities (PCMCIA, memory modules).Well established interfaces to link the device with a PC or network for updates and amplestorage capacity would make extension ports and hardware upgrades not necessary andtherefore bringing down the amount of I/Os and the form factor. A simple system would bemade of GPS, processor, memory, user interface and serial I/O.

4.3.3 Handheld Computing device with GPS functionality

The trend in mobile computing shows evergrowing CPU performance and memory capaci-ties. More and more operating systems and concepts are lookalikes of the normal desktopcomputers, but incorporate less functionality and only very limited communication links.Several well established handhelds like the Apple Newton, US Robotics PalmPilot and HP

30


620LX Palmtop PC feature very different concepts but offer basically a very small version ofa normal desktop office PC in hardware and software. To attach a GPS device to these sys-tems lessens the effort to only plugging in to an external port and installing the apropriatesoftware. An integrated device could hold a GPS-MS1 in one of these palmtops. The needfor a smaller form factor would mean to only integrate the palmtop system.

4.3.4 Fully Integrated Device

The smallest solution would be a GPS system and computing device integrated into a whole.As long as GPS chipset and code are still dependant on a simple external microcontroller thiswould mean to integrate a chain aof GPS-microcontroller-CPU-userinterface. Future GPSsystems might be able to reduce this chain to only GPS-CPU-userinterface. (A port of the GPSprogram code from SH-1 to SH-3 and Windows CE operating interface is beeing evaluated.)

5 System Integration

µ-blox ag is in contact with various suppliers of navigation equipment and software. Somecustomers already implement navigation equipment, mainly for automotive applications,using databases and software that are part of the system. Different systems offering onlinedata sources such as RDS traffic information, regional databases and locally restricted navi-gational aids, such as differential GPS and positioning within GSM cells are slowly becomingcommercial.

A survey of possible partners for the development of commercial software systems and anendconsumer device is being conducted.

6 Contacts

G. Plechinger, Hitachi MunichT +49-89-991 80 173F +49-89-991 80 272

Oelrich, Sales Manager, Hitachi MunichT +49-89-991 80 173F +49-89-991 80 272

David Lin, ITE USAE-mail: [email protected]

31


32

BAppendix WinCE Engine System

Specification

33

Chapter B: Appendix WinCE Engine System Specification

SH-3 WinCE EngineSystem Specification (Preliminary) –

Jan Beutel, Tobias Bösch

5th February 1999

µ-blox agETZ/H97Gloriastrasse 35CH-8092 ZürichSwitzerlandhttp://www.u-blox.ch

1 Overview

The SH-3 WinCE Engine is targeted for standalone operation of the Windows CE operatingsystem with a single 3.3V power supply. Clocking, system and display memory, I/O, colorLCD and touch screen interface are situated on the module. External memory can be eitherconnected via the available system bus or a PC-card interface. The necessary converters andbuffers for analog modem, serial I/O level shifters as well as the touch screen and displayspecific power generation can be fitted externally with only few external components.

SH770915x15mm

Flash 128M9,96x16,3mm

9,96x16,3mFlash 128M

SDRAM 256M


SDRAM 256M


HD6446117x17mm

11,8x21,04mmDRAM 64M

Reset

Clock

2x PCMCIA

Serial IO

IRDA Support

Analog Modem Frontend

Color 640x480 LCD

GPS MS1

Touchscreen

PeripheralsWinCE Engine

Figure 1: System Layout

The module is fitted with ample memory to support state of the art portable applicationslike communication, office, navigation and a userspecific database, i.e. for navigation.

34

SH-3 WinCE Engine µ-blox AG, February 5, 1999 Page 2

2 CPU Operation

2.1 Reset

A reset is realized by the Analog Devices ADM809 reset chip. An early power fail warningand batteryswitchover can be implemented using the externally available NMI signal andthe VCC_RTC of the SH7709processor.

The RESETP_N of the SH7709 can be pulled down externally for a manual reset.

2.2 Operating Modes

The configuration pins MD[0:2] and MD[5] are asserted high by default. The two pins forsetting the default bus width are userconfigurable and thus accessible externally so theycan be pulled low for initial programming via an external signal and set high for default32 Bit wide operation. The CPU operates in Mode 7, using an external clock oszillator. Thecurrent internal operating state is reported through the STATUS0 and STATUS1 pins accessibleexternally.

Configuration Pin Description Useraccessible DefaultMD0 Select clocking mode no Mode 7MD1 Select clocking mode no Mode 7MD2 Select clocking mode no Mode 7MD3 Access Width Area 0 yes 32 BitMD4 Access Width Area 0 yes 32 BitMD5 Set endian mode no Little Endian

Table 1: Configuration of the CPU

MD4 MD3 Memory Widthlow low Reserved (Do not set)low high 8 bithigh low 16 bithigh high 32 bit

Table 2: Area 0 Memory Width

STATUS1 STATUS0 Processor Operating Statuslow low Resetlow high Sleep modehigh low Standby modehigh high Normal operation

Table 3: Processor Operating Status

35



2.3 Clocking

A system clock of 26,7 MHz is generated via the main clock oszillator and distributed to CPUsCKIO input, companion chip and SDRAM memory. The CPU operates with a trippled internalCPU clock of 80 MHz generated by the PLL1.

Figure 2: Clock Generation on the SH7709

A crystal oszillator for the real time clock (32,768 kHz) is connected to the CPUs XTAL2 port.

The real time clock can be operated by only applying VCC_RTC and no other operatingvoltage externally for powersaving purposes.

2.4 General Purpose I/O

Port PTC is available externally and can be used to supply a matrix keyboard, or control I/O.PTC[0:2] control the reset, debug and trickle power mode function of the GPS-MS1.

2.5 Serial I/O

Three serial Ports are available on the SH7709. One serves the GPS-MS1 subsystem and thetwo others are accesible externally.

2.6 Analog I/O

The analog input pins AN[5:0] and the analog I/O pins AN[6:7] or DA[1:0] are available ex-ternally for user defined use. A touch screen interface can be connected simply via a 4 wireinterface to AN[3:0].

36


Figure 3: Realtime Clock on the SH7709

3 Main Memory Subsystem

The SH7709 processor is capable of handling different memory types in up to 6 different, 64Mbyte large areas. A variable buswidth from 8 bit to 32 bit can be specified. The HD64461companion chip is generally located in area 2 and uses the lower part of that address spacefor it’s registers and functions, and the upper part for a seperate EDO DRAM display memory.

Area Physical Addr. Supports CommentArea 0 H’00000000 Normal memory/burst ROM 32 Mbyte Flash MemoryArea 1 H’04000000 Internal I/O not usedArea 2 H’08000000 Normal memory/SDRAM,

DRAMnot used

Area 3 H’0C000000 Ordinary memory/SDRAM,DRAM

64 Mbyte SDRAM Memory

Area 4 H’10000000 Companion ChipArea 5 H’14000000 Normal memory/burst

ROM/PCMCIAThe PCMCIA interface is forthe memory card only

Area 6 H’18000000 Normal memory/burstROM/PCMCIA

The PCMCIA interface isshared by the memory and I/Ocard

Table 4: Memory Areas of the SH7709

37



3.1 SDRAM

A first prototpe design will contain two x16 SDRAM devices with 4 banks internally for full32 Bit access. In order to support future 128 Mbit and 256 Mbit devices an upgrade pathfrom currently available 64 Mbit devices is provided.

The 256 Mbit SDRAM will be available in a space saving 8x16 mm FBGA package in the nearfuture. The max. 64 Mbyte of onboard system SDRAM (2 x 256 Mbit) are situated in theArea 3 of the SH7709 and are selected simultaneously.

64 Mbit 128 Mbit 256 MbitConfig. 1Mbit x 16 x 4 banks 2Mbit x 16 x 4 banks 4Mbit x 16 x 4 banksRefresh Count 4k 4k 8kRow Addr. 4k(A0-A11) 4k(A0-A11) 8k(A0-A12)Bank Addr. 4(BA0,BA1) 4(BA0, BA1) 4(BA0, BA1)Column Addr. 256(A0-A7) 512(A0-A8) 512(A0-A8)

Table 5: Upgarde Path for SDRAM

The SDRAM devices are directly connected to the system clock CKIO signal.

3.2 Flash ROM

The design is specified for 2 x 128Mbit 0.25µ-next generation Intel StrataFlash devices oper-ating on a single 3.3V power supply. Up to four of these devices can be fitted into area 0 ofthe SH7709 processor.

Since these devices are not yet available, a dual design using current 64Mbit devices (28F640J5Intel Strata Flash) and an external 5V power supply as intermediate solution is approached.This configuration will allow for 2x8Mbyte onboard now and 2x16Mbyte with the next gen-eration.

The Erase/Program/Block Lock Enable input Vpen is accessible externally for user specificdefinition. It must be pulled low to secure memory contents.

4 Companion Chip

4.1 Connetion to the SH7709 CPU

The HD64461 companion chip is connected directly to the bus of the SH7709 processor. It isoperated in Mode 00, i.e. configured for 2x PCMCIA slots, IRDA, Timer, UART, AFE, LCD andGPIO.

4.2 Clocking

The system clock is also distributed to the companion chip and input to the CKIO pin.

38


The HD 64461 companion chip serves the LCD interface with a 31 MHz and the Analog ModemFrontend Interface and IRDA with a 9,216 MHz quarz. This enables the IRDA interface to runin HP-SIR mode.

4.3 LCD Interface

A 640 x 480 pixel color STN-LCD can be connected directly to the LCDM[7:0] bus, CL1 and CL2display clock and first line marker FLM, display on/off DON and multifunction pin M. In LCDmode 1 a total of 256 out of 256k colors can be displayed.

The HD64461 companion chip has it’s own display memory interface for 256k x 16 EDO DRAMthat are connected to a 4M x 16 EDO DRAM. A future companion chip will incorporate thisdeisplay memory, thus ommitting the necessary extra memory device.

4.4 PCMCIA Interface

The PCMCIA controller enables two slots of PC cards that are compliant with the specificationsPCMCIA Rev. 2.1/JEIDA Version 4.2. Area 6, which is referred as channel 0, supports both ofthe IC memory card interface, and I/O & Memory card interface. Area 5, which is referred aschannel 1, only supports IC memory card interface.

All signals are directly accessible externally.

Figure 4: Block diagram of the PCMCIA interface

4.5 General Purpose I/O

Ports PA and PB are available externally.

39



4.6 Analog Modem Frontend Interface

The HD64461 has built in interface to the STM ST7546 Analogue Front End (AFE). The STMST7546 is not included on the WinCE Engine. The interface signals are available on theconnector. The AFE interface features two 16 Bit wide buffers.

Figure 5: AFE Block Diagram

4.7 IRDA Support

The IRDA interface of the HD64461 supports HP-SIR mode with datarate of up to 4Mbit/secand can be attached directly to a normal infrared diode transceiver.

4.8 Serial I/O

When the IRDA interface is not used, the an extra serial port is available on the respectivepins.

5 Designated Userinterface

The user interface is designed for LCD screen, touch pad and/or keyboard matrix via GPIOpins. Only the pins supplied by the SH-3 system are available on the connector. A user wouldhave to supply amplification of the signals, reference voltages as well as display specificpower supplies on an external circuitry.

40


6 GPS Functionality

6.1 GPS-MS1 Connection to the WinCE Engine

Folding line in FlexcircuitSD

RAM

256

M

DRAM 64M

9,96

x16,

3mFl

ash

128M

Flas

h 12

8M9,

96x1

6,3m

m

8x16

mm

FBG

A11

,8x2

2,3m

m T

SOP5

4

SDR

AM 2

56M

8x16

mm

FBG

A

11,8x21,04mm 11,8

x22,

3mm

TSO

P54

SH770915x15mm

��

��

��

��

HD64461

GPS-MS1Piggyback

17x17mm

WinCE Engine with GPS-MS1

Figure 6: GPS-MS1 as Piggyback on the WinCE Engine

Piggyback GPS-MS1

Figure 7: GPS-MS1 mounted as Piggyback over BGA and SMT Components.

The GPS-MS1 receiver can be mounted piggyback on the WinCE Engine and communicatesvia it’s serial port 0 to the serial port 1 of the SH7709 processor. The SH7709 host controls allfunctions of the GPS-MS1 receiver via serial I/O.

Low power operation of the GPS-MS1, such as Trickle Power or Push to Fix Mode are con-trolled from the SH7709 host. Either a 3.3V active antenna or a passive antenna is supported.

Differential GPS data can be input externally via the serial port 1 of the GPS-MS1 receiverthat is available externally as well as the 1 puls per second 1PPS signal.

41



The GPS-MS1 systems SRAM can be backed up by an external backup battery connected toVBAT.

Updates to the GPS-MS1 firmware can be downloaded via the SH7709 host system.

7 Pinout of the WinCE Engine Module

Pinout of the WinCE Engine ModulePinname Pinno. Function DestinationGeneralVCC3.3V 0, 25, 49, 100, 125, 149GND 50, 75, 99, 150, 175, 199VCC5 98 5 Volt Flash support voltage FlashVCC_RTC 198 Real Time Clock support voltage SH7709SystemD[0..31] 65–74, 76–97 Databus SH7709A[0..25] 27, 26, 24–1 Addressbus SH7709NMI 58 Interrupt SH7709IRQ1 52 Interrupt SH7709IRQ2 51 Interrupt SH7709STATUS0 57 Processor Operating Status SH7709STATUS1 56 Processor Operating Status SH7709IRQOUT_N 55 Interrupt SH7709WAKEUP_N 54 SH7709RESET_EXT 62 External Reset SH7709CKIO 53 System Clock SH7709MD3 60 Select Area 0 Memory Width SH7709MD4 59 Select Area 0 Memory Width SH7709Vpen 63 Erase/Program/Block lock enable FlashSTS 64 Status FlashTouchscreenAN[0..3] 126–129 Touch Screen Interface SH7709AN[4,5] 130, 131 Analog Input SH7709AN[6,7] 132, 133 Analog I/O SH7709LCDLCDM[0..7] 141, 148 Output data bus for LCD module HD64461CL1 140 Display data latch clock for LCD module HD64461CL2 139 Display data shift clock for LCD module HD64461LCD_BACKLIGHT 138 LCD Backlight ON/OFF_N SH7709LCD_CONTRAST 137 LCD Contrast Voltage ON/OFF_N SH7709FLM 136 First line marker for LCD module HD64461DON 135 Display ON/OFF control for LCD module HD64461M 134 Display Control HD64461PCMCIAPCCRDWR 197 PCMCIA Interface HD64461PCC0DRV 196 PCMCIA Interface HD64461CE1B_N 195 PCMCIA Interface HD64461CE2B_N 194 PCMCIA Interface HD64461RDB_N 193 PCMCIA Interface HD64461

42


Pinout of the WinCE Engine Module continuedPinname Pinno. Function DestinationWEB_N 192 PCMCIA Interface HD64461ICIORDB_N 191 PCMCIA Interface HD64461ICIOWRB_N 190 PCMCIA Interface HD64461PCC0RESET 189 PCMCIA Interface HD64461PCC0WAIT_N 188 PCMCIA Interface HD64461PCC0WP_N 187 PCMCIA Interface HD64461PCC0RDY 186 PCMCIA Interface HD64461PCC0BVD1 185 PCMCIA Interface HD64461PCC0BVD2 184 PCMCIA Interface HD64461PCC0CD1_N 183 PCMCIA Interface HD64461PCC0CD2_N 182 PCMCIA Interface HD64461PCC0VS1_N 181 PCMCIA Interface HD64461PCC0VS2_N 180 PCMCIA Interface HD64461PCC0A25 179 PCMCIA Interface HD64461PCC0REG_N 178 PCMCIA Interface HD64461PCC0A24 177 PCMCIA Interface HD64461VCC0SEL0 176 PCMCIA Interface HD64461VCC0SEL1 174 PCMCIA Interface HD64461PCC1DRV 173 PCMCIA Interface HD64461CE1A_N 172 PCMCIA Interface HD64461CE2A_N 171 PCMCIA Interface HD64461RDA_N 170 PCMCIA Interface HD64461WEA_N 169 PCMCIA Interface HD64461PCC1RESET 168 PCMCIA Interface HD64461PCC1WAIT_N 167 PCMCIA Interface HD64461PCC1WP_N 166 PCMCIA Interface HD64461PCC1RDY 165 PCMCIA Interface HD64461PCC1BVD1 164 PCMCIA Interface HD64461PCC1BVD2 163 PCMCIA Interface HD64461PCC1CD1_N 162 PCMCIA Interface HD64461PCC1CD2_N 161 PCMCIA Interface HD64461PCC1VS1_N 160 PCMCIA Interface HD64461PCC1VS2_N 159 PCMCIA Interface HD64461PCC1A25 158 PCMCIA Interface HD64461PCC1REG_N 157 PCMCIA Interface HD64461PCC1A24 156 PCMCIA Interface HD64461VCC1SEL0 155 PCMCIA Interface HD64461VCC1SEL1 154 PCMCIA Interface HD64461VCCA 153 PCMCIA support voltage HD64461VCCB 152 PCMCIA support voltage HD64461VCCD 151 PCMCIA support voltage HD64461AFEDIN 124 AFE Interface HD64461DOUT 123 AFE Interface HD64461SCLK 122 AFE Interface HD64461HC1 121 AFE Interface HD64461FS 120 AFE Interface HD64461

43



Pinout of the WinCE Engine Module continuedPinname Pinno. Function DestinationRESETO_N 119 AFE Interface HD64461PWRDWNO_N 118 AFE Interface HD64461MCLKO 117 AFE Interface HD64461RING 116 AFE Interface HD64461RLYCNT 115 AFE Interface HD64461HD64461 GPIOPA0 33 GPIO HD64461PA1 34 GPIO HD64461PA2 35 GPIO HD64461PA3 36 GPIO HD64461IRDAPA4 37 IR Clock HD64461PA5 38 IR RXD HD64461PA6 39 IR Mode or RX2 HD64461PA7 40 IR TXD HD64461Serial I/ORXD0 114 Serial Port 0 SH7709TXD0 113 Serial Port 0 SH7709SCK0 112 Serial Port 0 SH7709RXD2 111 Serial Port 2 SH7709TXD2 110 Serial Port 2 SH7709SCK2 109 Serial Port 2 SH7709RTS2_N 108 Serial Port 2 SH7709CTS2_N 107 Serial Port 2 SH7709PB0 41 RI UART HD64461PB1 42 DCD UART HD64461PB2 43 DSR UART HD64461PB3 44 DTR UART HD64461PB4 45 CTS UART HD64461PB5 46 RTS UART HD64461PB6 47 RX UART HD64461PB7 48 TX UART HD64461GPS-MS11PPS 106 One pulse per second reference GPS-MS1RX_DGPS 105 Differential GPS Input GPS-MS1TX_DGPS 104 Differential GPS Input GPS-MS1

Table 6: Pinout of the Module

44

CAppendix Hardware

45

Chapter C: Appendix Hardware

C.1 WinCE Engine Schematics

Figure C-1WinCE Engine schematic page 1

46

C.1. WinCE Engine Schematics


47



48

C.1. WinCE Engine Schematics


49



50

C.2. Bill of Material

C.2 Bill of MaterialTitle: Bill of MaterialsDesign: WINCE_ENGINE_1Date: Feb 5 13:47:07 1999Template: /home/thiel/cds/cdssetup/template.bom

Page: 1

Item Qty Ref Des Value Tolerance Manufacturer Order Number Description==== === ========== ========== ========== ==================== ==================== ====================

1 1 U1 ? ? ANALOG_DEVICES ADM809TART 3.08V RESET CIRCUIT2 5 C1,C4,C6, 100N 10% AVX 0603YC104KAT_A CAPACITOR, X7R, 16V

C63,C643 42 C12-C28, 10N 10% AVX 0402YC103KAT_A CAPACITOR, X7R, 16V

C30-C43,C45-C55

4 2 C10,C11 12P 5% AVX 04023A120JAT_A CAPACITOR, COG, 25V5 2 C57,C58 1U0 20% AVX 0805ZC105MAT_A CAPACITOR, X7R, 10V6 2 C2,C3 22P 5% AVX 04023A220JAT_A CAPACITOR, COG, 25V7 2 C8,C9 33P 10% AVX 04023A330KAT_A CAPACITOR, COG, 25V8 2 C5,C7 470P 10% AVX 0402YC471KAT_A CAPACITOR, X7R, 16V9 4 C56, 10U 20% AVX TAJA106M010 CAPACITOR, TANTALUM,

C59-C61 10V,ESR3.010 2 J1,J2 ? ? MOLEX 53929-1001 CONNECTOR FOR JBS

BOARD11 1 U10 ? ? FAIRCHILD NC7SZ32M5 TINY LOGIC UHS

2-INPUT OR GATE12 1 U4 ? ? HITACHI HD64461 SH-3 COMPANION CHIP13 1 U2 ? ? HITACHI SH7709 SH-3 CPU14 2 U5,U6 ? ? INTEL 28F640J5 64M X 8 3V/5V FLASH15 2 U7,U8 ? ? MICRON ? SDRAM16 1 U3 ? ? MICRON ? EDO RAM17 2 R7,R8 100K 10% AVX CR05-104K RESISTOR, 0.063W18 1 R3 10K 10% AVX CR05-103K RESISTOR, 0.063W19 1 R5 2K2 5% AVX CR05-222J RESISTOR, 0.063W20 1 R6 2M0 5% AVX CR05-205J RESISTOR, 0.063W21 1 U11 ? ? UBLOX GPS-MS1 GPS RECEIVER MCM22 1 Y3 31.0MHZ 50PPM EPSON FA-365-31.0 SMD QUARTZ CRYSTAL

UNIT23 1 Y1 32.768KHZ 50PPM MICRO_CRYSTAL CX4V-T232.768KHZ SMD QUARTZ CRYSTAL

UNIT24 1 Y4 9.216MHZ 50PPM MICRO_CRYSTAL CXAT-T19.216MHZ SMD QUARTZ CRYSTAL

UNIT25 1 Y2 26.668 50PPM EPSON SG8002CA/PC SMD QUARTZ CRYSTAL

OSCILLATOR==== === ========== ========== ========== ==================== ==================== ====================

82

51


52

DAppendix Software

D.1 WindowsCE Development using EBX7709This section describes the EBX7709 evaluation platform and how it can be used todevelop WindowsCE images and WindowsCE programs.

D.1.1 Key featuresThe EBX7709 is based on the Hitachi SH7709 CPU. The SH7709 is accompanied byits companion chip, the Hitachi HD64461, which provides many of the I/O functionsdescribed hereafter. The board is equipped with 32 Mb of DRAM and 16 Mb of flashmemory. That is enough flash to hold up to two moderately sized WinCE images.These images can be executed in place.

The HD64461 provides the display controller. It can interface to LCD’s and CRT’sthrough appropriate daughter boards. These daughter boards are stackable, al-lowing both LCD and CRT interfaces to be resident together. The software driverhowever does not allow simultaneous use of them.

The HD64461’s PC-Card interface is made availalbe through two standard PC-Cardslots, holding up to two Type 2 cards or one Type 3 sized card.

The EBX7709 contains a STM ST7546 analogue front end interfacing to theHD64461. The STM ST7546 provides the necessary ADC and DAC signal pro-cessing functions to support V34bis modem and business audio applications. Theanalogue signals are present at a connector. No software modules make currentlyuse of these features.

Mouse and keyboard ports are present. They are provided by a 8042 micro-controllerbased keyboard and mouse controller. They are not based on main CPU or companionchip capabilities.

53

Chapter D: Appendix Software

The CPU and the companion chip provide a waste range of serial communicationports. Seven of these are available through windows device drivers. One port isdedicated to debugging and can not be used in windows. See figure D-1 at the endof this section for more details on serial device drivers.

D.1.2 How to compile a Windows CE development systemYou need a fast Windows NT computer with 1 Gb of free disk space and 32 Mb RAM.Your account must have administrator privileges. Make sure to have the followingCD’s at hand:

� Microsoft Visual C++ 5.0 (2 CD set)

� Microsoft Windows CE Embedded Toolkit for Visual C++ 5.0 (3 CD set)

� CD ROM for EBX7709

Install the various programs in the following order:

1. Install Visual C++ 5.0 from the first CD set above

2. Add the Windows CE Toolkit for Visual C++ 5.0 from the second set

3. Next install the Windows CE Embedded Development Kit from the same set

4. Copy the Ebx7709 directory from CD three above to your%_WINCEROOT%nplatform directory

5. Change the file permissions for all files in the Ebx7709 directory now on yourhard-drive from ‘‘read only’’ to ‘‘archive’’

D.1.3 How to compile a Windows CE imageFirst step to take toward compiling a Windows CE image is setting up a developmentshell with a certain set of environment variables. Here is how that is done. Havinginstalled all the above software packages you should have a ‘‘Windows CE EmbeddedDevelopment Kit’’ folder somewhere in the Start menu. This folder contains shortcutsto some of the demo projects (e.g. called SH3 DEMO1). Copy one of these shortcuts,rename it to something like SH3 EBX7709 DEMOx, open its ‘Properties’ and choosethe ‘Shortcut’ panel. Edit the target to reflect the demo project you would like tobuild and change the platform from ‘ODO’ to ‘EBX7709’. An entry then looks like‘‘wince.bat SHx SH3 CE DEMO7 EBX7709’’. Wince.bat is a wrapper program, thatsets up the build environment according to the options it is given.

Double click the shortcut you just created. A command prompt window pops up. Thisis your development shell. Type ‘builddemo’ to build the associated demo project.If something goes wrong during the build process check the file permissions andavailable disk space before trying to track down any errors. If the build succeedsyou should have a nk.bin file in the release directory.

54

D.1. WindowsCE Development using EBX7709

D.1.4 Adapting Windows CEGlobal WinCE image parameters should be set in the ebx7709.bat batchfile. ThisFile is run everytime a development shell is opened. Therefore do not forget to closeand reopen your shell after altering this file. The following things can be customizedin ebx7709.bat:

� Image location (i.e. RAM or FLASH)

� Image location in FLASH (i.e. low or high 8 Mb)

� Mouse cursor support

� Graphics driver

The ebx7709.bat does not alter any settings itself, but sets or clears some environ-ment variables, which then influence the way the bib-files are processed.

D.1.5 How to transfer a Windows CE image to the EBX7709WindowsCE images are transfered to the EBX7709 through a parallel connectionusing the PPSH transfer utility. Before the PPSH utility can be used, a few stepshave to be carried out on the development platform (i.e. the Windows NT machine).First set the parallel port mode to bidirectional. This can be done in the PC’s BIOSsettings menu. After rebooting the machine make sure the PPSH device driver iscorrectly installed and started:

1. Open the control panel and select the devices section

2. Verify that Parallel, Parport and ParVdm startup are listed as Manual. If not,change them to Manual.

3. Verify that PPShell status is listed as Started and Startup is listed as Auto-matic. If not, change Startup to Automatic and start the device by clicking onStart.

To transfer an image open the appropriate development shell. Make sure a nk.binfile is in the release directory. Start the PPSH utility by typing the followingcommand sequence:

ppsh -s -p cepc

CTRL-C

ppsh -s -p cepc

The ‘-p cepc‘ option tells PPSH to use the parallel port settings stored under CEPCin the registry.

Power up the EBX7709 with DIP switch 8 set to ON. See figure D-2 at the end ofthis section for a full listing of all possible dip switch settings. The EBX7709 thentries to connect to PPSH and loads the image to either flash or RAM (depends onthe location set in the ebx7709.bat file).

55


D.1.6 Debuging the imageUse the SIO3 serial port of the SH7709 to display debug information. Connect it tothe development workstation using a straight through serial cable. Set the serialport settings to 38’400bps, 8 bits, no parity and 1 stop bit.

D.1.7 Connecting a WindowsCE device to a host computerWindowsCE devices can be connected to a host computer using a serial connectionand a PPP stack. Use a null-modem cable to connect the EBX7709 to the host. Makesure the CD signal is tied to high (e.g. to DTR). See table D-3 for a pin out.

On the host computer Windows CE Services should be running with the MobileDevices folder opened. On the EBX7709 an image with network capabilites must berunning.

D.1.8 Lookup-tables

Table D-1: EBX7709 Serial Devices

56

D.1. WindowsCE Development using EBX7709

Table D-2: DIP Switch Settings

Signal Name WinCE device host computerFrame Ground FG - - FGTransmit Data TD 3 2 RDReceive Data RD 2 3 TD

Request to Send RTS 7 8 CTSClear to Send CTS 8 7 RTSSignal Ground SG 5 5 SGData Set Ready DSR 6 4 DTR

Data Terminal Ready DTR 4 6 DSRCarrier Detect CD Pin 1: tie to DTR Pin 1: tie to DTR CD

Table D-3: DB9 null modem pin out (two DTEs)

57


58

EAdditional Documentation

A collection of all additional documentation is available containing the followingdocuments. For further information, especially current updates please refur to thespecific web pages and/or the contact persons listed in the next chapter.

� Analog Devices ADM809/810 Datasheet

� Dyconex Design Rules for 2D Microvia Boards

� Dyconex Design Rules for 4D Microvia Boards

� Dycostrate Microvia Design Guide

� High-Performance Dycostrate MLBs

� Dyconex Rigid-flexible Multilayer Boards

� Epson SG-8002CA Series Programmable Oszillator Datasheet

� Epson Table of Crystal Units

� Epson FA-365 Crystal Unit Datasheet

� Fairchild Semiconductor NC7SZ32 TinyLogic Or Gate Datasheet

� Hitachi SH7709 Manual (Online as pdf)

� Hitachi HD64661 Manual (Online as pdf)

� Hitachi EBX7709 User Manual

� Hitachi EBX7709 Reference Platform Schematics

59

Chapter E: Additional Documentation

� Hitachi SH7709 T-FBGA1515-216 Package Dimensions and Pinout

� Hitachi/ITE LBGA208 Package Dimensions and Pinout

� Intel µBGA Package Mechanical and Shipping Media Specification

� Intel Comprehensive Userguide for uBGA Packages

� Intel StrataFlash Memory 0.25µ-Generation Migration Guide

� Intel StrataFlash Memory Technology 32 and 64 Mbit

� Intel StrataFlash Memory Design Guide

� MicroCrystal CXAT Datasheet

� MicroCrystal CX4 Datasheet

� Micron Synchronous DRAM 64Mbit Datasheet



� Micron EDO DRAM 64Mbit Datasheet

� Molex 0.5 mm Board to Board Connector Drawings

� µ-blox GPS-MS1 Receiver Datasheet

60

FContacts

All the contacts given below are correct as of February 1999 and were involved inthis project.

DyconexUnterwerkstrasse 3CH-8052 Zürich

Director R&DMarco Martinelli+41-1-306 24 [email protected]

EME (Molex Connectors)Lohwisstrasse 50CH-8123 Ebmatingen

Peter Krüsi+41-1-982 11 [email protected]

Eurodis (Oszillators)Bahnstrasse 58/60CH-8105 Regensdorf

Kurt Ernst+41-1-843 31 11

61

Chapter F: Contacts

Hitachi Europe GmbHDornacher Strasse 3D-85622 Feldkirchen bei München

Product MarketingGünter Plechinger+49-89-991 80 [email protected]

IntelIndustrade AGHertistrasse 31CH-8304 Wallisellen

Bernhard [email protected]

ITE2710 Walsh AvenueSanta Clara, CA 95051USA

MarketingDavid Lin+1-408-980 81 [email protected]

Micron Semiconductor Deutschland GmbHSternstrasse 20D-85609 Aschheim

Strategic Accounts ManagerHerbert Walser+49-89-904 872 [email protected]

Sirf Technology Inc.3970 Freedom CircleSanta Clara, CA 95054USA+1-408-980 47 00

Project ManagementJean-Marie [email protected]

62

Software/WinCE QuestionsAndy [email protected]

µ-blox AGGloriastrasse 35CH-8092 Zürich

Andy Thiel+41-1-632 66 [email protected]

Claus Habiger+41-1-632 76 [email protected]

Jean-Pierre Wyss+41-1-632 52 [email protected]

63

Chapter F: Contacts

64

Bibliography

[1] T.Imielinski and H. Korth. Mobile Computing. Kluwer Academic Publishers,1996.

[2] P. Sandborn and H. Moreno. Conceptual Design of Multichip Modules and Sys-tems. Kluwer Academic Publishers, 1994.

[3] D. Doane and P. Franzon. Multichip Module Technologies and Alternatives: TheBasics. Van Nostrand Reinhold, 1993.

[4] R. Tummala and E. Rymaszewski, eds. Microelectronics Packaging Handbook.Van Nostrand Reinhold, 1989.

[5] P. Horowitz and W. Hill. The Art of Electronics. Cambridge University Press,1989.

[6] High Performance DYCOstrate MLBs. Dyconex, 1999.

[7] http://www.dyconex.com

[8] http://www.hitachi-eu.com/hel/ecg/index.htm

[9] http://semiconductor.hitachi.com/

[10] http://www.iteusa.com/

[11] http://www.microsoft.com/windowsce/default.asp

[12] http://www.u-blox.ch

65

SH-3 WinCE engine Semester Thesis WS 98/99beutel/pub/19990205_wince_report.pdf · runden Sie diesen...

Documents

Transcript of SH-3 WinCE engine Semester Thesis WS 98/99beutel/pub/19990205_wince_report.pdf · runden Sie diesen...