Setup the Debugger for a CoreSight System - · PDF fileSetup the Debugger for a CoreSight...

Setup the Debugger for a CoreSight System

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Setup the Debugger for a CoreSight System ................................................................. 1

Introduction .................................................................................................................... 3

Example of a CoreSight System ................................................................................... 4

Using this Application Note .......................................................................................... 6

Diagnosis ........................................................................................................................ 7

Description 7

Example of a Diagnosis Protocol 7

Debug Access Port (DAP) ............................................................................................. 9

Common Debugger Setup 9

Example 10

Real-Time Memory Access (MEM-AP) 11

Core Debug Register Access 12

JTAG Access Port (JTAG-AP) 13

Serial Wire Debug Port (SW-DP) ................................................................................... 14

Description 14

Embedded Trace Macrocell (ETM/PTM) ....................................................................... 16

AMBA AHB Trace Macrocell (HTM) .............................................................................. 17

Description 17

Debugger Setup 17

Usage 18

Instrumentation Trace Macrocell (ITM) ........................................................................ 19

Description 19

Debugger Setup 19

Usage 20

Funnel, AMBA Trace Bus (ATB), Replicator ................................................................ 21

Description 21

Setup the Debugger for a CoreSight System 1 ©1989-2015 Lauterbach GmbH

Debugger Setup 21

Usage 21

Trace Port Interface Unit (TPIU) .................................................................................... 22

Description 22

Debugger Setup 22

Usage 23

Embedded Trace Buffer (ETB) ...................................................................................... 24

Description 24

Debugger Setup 24

Usage 25

Serial Wire Viewer (SWV), Serial Wire Output (SWO) ................................................. 26

Description 26

Debugger Setup 26

Usage 27

Embedded Cross Trigger (ECT), Cross Trigger Matrix (CTM), Cross Trigger Interface (CTI) 28

Description 28

Debugger Setup 28

Usage 28

Setup the Debugger for a CoreSight System 2 ©1989-2015 Lauterbach GmbH

Setup the Debugger for a CoreSight System

Version 19-May-2015

Introduction

The CoreSight technology from ARM provides additional debug and trace functionality with the objective of debugging an entire system-on-chip (SoC). CoreSight is a collection of hardware components which can be chosen and implemented by the chip designer appropriate to his system-on-chip to extend the debug features given by the cores.

This application note explains which settings the debugger will need to support the CoreSight components implemented on your system-on-chip. It further describes the debugger commands you will need to use the new CoreSight features.

Here you shall get an idea what is relevant to debug a CoreSight based system. A full description of the commands can be found in ”ARM Debugger” (debugger_arm.pdf).

Setup the Debugger for a CoreSight System 3 Introduction ©1989-2015 Lauterbach GmbH

Example of a CoreSight System

Figure: Debug Access Port (DAP)

Setup the Debugger for a CoreSight System 4 Example of a CoreSight System ©1989-2015 Lauterbach GmbH

Figure: System wide trigger and trace

Setup the Debugger for a CoreSight System 5 Example of a CoreSight System ©1989-2015 Lauterbach GmbH

Using this Application Note

Identify in the list below which CoreSight components you have on your system-on-chip and read the appropriate chapter. There you will find:

• an short explanation of the CoreSight component

• the debugger set-ups you will need in your start-up script

• a list of commands related to the new features

The debugger will most likely work even without the described settings, but you will need them as soon as you intend to use the additional CoreSight features.

In case you can select your chip from the CPU list (SYStem.CPU <type>) you can assume that the debugger is informed about the CoreSight system on this chip and all settings are done automatically. In this case often a start-up script like

is sufficient to use all debug features. Nevertheless the application note still will give you information of how to use these CoreSight features.

If you do not have access to the chip documentation to inform you about the details of your CoreSight system you can read out some information with the debugger. See chapter Diagnosis.

For more information regarding the CoreSight modules see DDI0314 CoreSight Components Technical Reference Manual which can be downloaded from the ARM web site at www.arm.com.

CoreSight Components:

• Debug Access Port (DAP)

• Serial Wire Debug Port (SW-DP)

• Embedded Trace Macrocell (ETM)Program Trace Macrocell (PTM)

• AMBA AHB Trace Macrocell (HTM)

• Instrumentation Trace Macrocell (ITM)

• Funnel, AMBA Trace Bus (ATB), Replicator

• Trace Port Interface Unit (TPIU)

• Embedded Trace Buffer (ETB)

• Serial Wire Viewer (SWV), Serial Wire Output (SWO)

• Embedded Cross Trigger (ECT), Cross Trigger Matrix (CTM), Cross Trigger Interface (CTI)

SYStem.CPU <type>SYStem.Up

Setup the Debugger for a CoreSight System 6 Using this Application Note ©1989-2015 Lauterbach GmbH

Diagnosis

Description

The following command sequence reads the CoreSight ROM table which includes information about the CoreSight system configuration. It displays the information in the message area window.

If the diagnosis does not work the following sequence will probably work:

If the DAP TAP is daisy-chained then you need to set the DAPIRPRE, … parameter first (see Debug Access Port (DAP)).

The diagnosis protocol provides part of the information you need to setup the debugger.

Example of a Diagnosis Protocol

DIAG 3411AREA

SYStem.JtagClock 100kHzSYStem.Option EnReset OFFDIAG 3411AREA

Debug Access Port (DAP) Discovery:

AP = 0x0IDR = 0x14770001 (MEM-AP AHB)BASE = 0xffffffff (no debug entries present)

AP = 0x1IDR = 0x04770002 (MEM-AP APB)BASE = 0x80000000 (ROM Table at 0x80000000)

0x80001000 Trace Sink: Buffer, for example ETB 0x80002000 Debug Control: Trigger Matrix, for example ECT 0x80003000 Trace Sink: Trace port, for example TPIU 0x80004000 Trace Link: Trace funnel, Router 0x80005000 Trace Source: Associated with a processor core 0x80006000 Debug Control: Trigger Matrix, for example ECT 0x80007000 Trace Source: Associated with a Bus, …

AP = 0x2IDR = 0x14760010 (JTAG-AP)

Setup the Debugger for a CoreSight System 7 Diagnosis ©1989-2015 Lauterbach GmbH

The following debugger setting can be derived from that information. Compare this with the relevant chapters of this application note.

depending on the CTI you want to look at (can be changed any time).

Other information, not included in the ROM table, is still missing. You need to get it from the chip documentation. In this example the following is missing:

AP = 0x0IDR = 0x14770001 (MEM-AP AHB)-> SYStem.CONFIG MEMORYACCESSPORT 0

AP = 0x1IDR = 0x04770002 (MEM-AP APB)-> SYStem.CONFIG DEBUGACCESSPORT 1

AP = 0x2IDR = 0x14760010 (JTAG-AP)-> SYStem.CONFIG JTAGACCESSPORT 2Only if the core you want to debug is connected to this JTAG Access Port!

0x80001000 Trace Sink: Buffer, for example ETB-> SYStem.CONFIG ETBBASE 0x80001000

0x80003000 Trace Sink: Trace port, for example TPIU-> SYStem.CONFIG TPIUBASE 0x80003000

0x80005000 Trace Source: Associated with a processor core-> SYStem.CONFIG ETMBASE 0x80005000

0x80004000 Trace Link: Trace funnel, Router-> SYStem.CONFIG FUNNELBASE 0x80004000

0x80007000 Trace Source: Associated with a Bus, …-> SYStem.CONFIG HTMBASE 0x80007000

0x80002000 Debug Control: Trigger Matrix, for example ECT0x80006000 Debug Control: Trigger Matrix, for example ECT-> SYStem.CONFIG CTIBASE 0x80002000 or-> SYStem.CONFIG CTIBASE 0x80006000

SYStem.CONFIG ETMFUNNELPORT <number>SYStem.CONFIG HTMFUNNELPORT <number>

Setup the Debugger for a CoreSight System 8 Diagnosis ©1989-2015 Lauterbach GmbH

Debug Access Port (DAP)

The DAP can provide the following features:

• Real-Time Memory Access (MEM-AP)

• Core Debug Register Access

• JTAG Access Port (JTAG-AP)

This features will be described in the following chapters. See also Example of a CoreSight System.

Common Debugger Setup

In case the DAP is not the only Test Access Port (TAP) in the JTAG scan chain you need to setup the position in the JTAG scan chain

Setup mask to specify the position of the DAP in a JTAG scan chain.

SYStem.CONFIG DAPIRPRE <value>

SYStem.CONFIG DAPIRPOST <value>

SYStem.CONFIG DAPDRPRE <value>

SYStem.CONFIG DAPDRPOST <value>

SYStem.CONFIG.state Display settings

Setup the Debugger for a CoreSight System 9 Debug Access Port (DAP) ©1989-2015 Lauterbach GmbH

Example

TDI -> TAP1 -> TAP2 -> DAP -> TAP4 -> TDO

Instruction register (IR) length of:

Data register (DR) length is 1 bit for each TAP (IR = BYPASS).

TAP1: 3 bit

TAP2: 5 bit

TAP4: 6 bit

SYStem.CONFIG.DAPIRPRE 0x6 ; IR TAP4

SYStem.CONFIG.DAPIRPOST 0x8 ; IR TAP1 + TAP2

SYStem.CONFIG.DAPDRPRE 0x1 ; DR TAP4

SYStem.CONFIG.DAPDRPOST 0x2 ; DR TAP1 + TAP2


Real-Time Memory Access (MEM-AP)

Description

The DAP can act as a bus master and can allow memory access to Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) even while the core is running. The busses are connected to Memory Access Ports (MEM-AP) of the DAP.

Since the control register of the CoreSight components are mostly mapped on the APB you will need this initialization.

Debugger Setup

The debugger needs to know the access port number the busses are connected to

<number> is between 0 and 255. The default numbers for the memory access port is 0 and for the debug access port is 1 which is correct in most cases.

Usage

Normal memory access commands can be used together with new access classes ’AHB:’ and ’APB:’ (old syntax: ’DAP:’). During runtime you need to add an ’E’ -> ’EAHB:’, ’EAPB:’.

Examples:

If you want to access memory as seen by the core you can use the standard access classes like ’SD:’ for data and ’SR:’ or ’ST:’ for code memory. But the debugger can not access memory via the core when the core is running. If you want to get it accessed via AHB (MEM-AP of the DAP) only when the core is running you need to add an ’E’ before the access class like ’ESD:’, ’ESR:’, ’EST:’ and you need to enable real time memory access by the command:

SYStem.CONFIG MEMORYACCESSPORT <number> ; AHB

SYStem.CONFIG DEBUGACCESSPORT <number> ; APB

Data.Set APB:0x90003020 %Long 0x12345678Data.dump AHB:0x80000000

SYStem.MemAccess DAP

Data.dump ED:0x874500a8

Var.View %E flags


Core Debug Register Access

Description

The new ARM debug interface architecture ADIv5 gives the designer the choice to use the old method, where you access the core debug registers directly via JTAG scan chains, or to use a DAP instead. The latter method is used on all Cortex cores. This method is assumed in this chapter.

Debugger Setup

The core debug register are within a 4 KByte memory block typically mapped on the Advanced Peripheral Bus (APB) which is connected to a Memory Access Port (MEM-AP) of the DAP. The debugger needs to know the base address of this register block

<accessclass> is typically ’APB’ which is the default access class.

In case of the Cortex-M there is a fix base address which is set per default.

Usage

These settings only inform the debugger how to access the core debug register in order to provide the (normal) core debug functions. There are no additional features.

SYStem.CONFIG COREBASE <accessclass>:<baseaddress>


JTAG Access Port (JTAG-AP)

Description

For cores which do not have the debug register memory mapped like ARM7, ARM9, ARM11 or any non-ARM core with JTAG debug interface, the DAP offers the possibility to connect these cores to a JTAG Access Port (JTAG-AP). The JTAG-AP can drive up to 8 JTAG interfaces. The debugger communicates with registers in the DAP to cause the DAP to generate JTAG sequences on a certain ’port’ of the JTAG access port. This way you have multiple JTAG interfaces. One between the debugger and the DAP and for each connected core another one between DAP and core. This reduces performance compared to a daisy-chained JTAG connection, but the advantage in a multi core system is that even if a core is powered down or has no or reduced clock the other cores can still be debugged.

Debugger Setup

The debugger needs to know the JTAG-AP number where the JTAG-AP is connected to the DAP.

The <number> is between 0 and 255. (Commonly 2 is used.)

The COREJTAGPORT specifies to which of the 8 possible ports of the JTAG-AP the core is connected to

The <portnumber> is between 1 and 8.

Usage

These settings only inform the debugger how to access the core debug register in order to provide the (normal) core debug functions. There are no additional features.

SYStem.CONFIG JTAGACCESSPORT <number>

SYStem.CONFIG COREJTAGPORT <portnumber>


Serial Wire Debug Port (SW-DP)

Description

A Debug Access Port (DAP) based system normally provides a standard JTAG interface between the debugger and the DAP consisting of the signals TMS, TDI, TCK, TDO, nTRST. Alternatively a Serial Wire Debug Port (SW-DP) can be implemented which uses just two signals TMSC and TCKC. Some chips provide both interfaces. The user can switch to the serial wire debug interface and use the remaining three signals for different purposes e.g. the TDO signal can be used as Serial Wire Output (SWO) for the Serial Wire Viewer (SWV). This interface often can be found on Cortex-M3 based devices.

Debugger Setup

At first you need a certain debug cable which supports the SW-DP. You can use all versions of the CombiProbe and the debug cable version V4 or newer. The pin position of TMSC is the same as TMS and TCKC the same as TCK.

You need to inform the debugger that the two pin communication shall be used:

This command must be used before the debugger establishes connection (SYStem.Up).

SYStem.CONFIG SWDP ON

Figure: CombiProbe

Figure: Debug Cable Version 4(older versions look different)

Setup the Debugger for a CoreSight System 14 Serial Wire Debug Port (SW-DP) ©1989-2015 Lauterbach GmbH

Usage

There are no additional features. It is just an alternative interface between debugger and DAP in order to save pin count.

Setup the Debugger for a CoreSight System 15 Serial Wire Debug Port (SW-DP) ©1989-2015 Lauterbach GmbH

Embedded Trace Macrocell (ETM/PTM)

Description

The ETM/PTM outputs information of the core’s activity (program and data trace).

The data can be passed directly or combined with other trace sources via Funnel and AMBA Trace Bus (ATB) off-chip to the Trace Port Interface Unit (TPIU). There it will be captured by a trace port analyzer (ETM Preprocessor or CombiProbe). Alternatively it can be stored on-chip in the Embedded Trace Buffer (ETB) for later readout via JTAG or Serial Wire Debug Port (SW-DP).

Debugger Setup

If there is a non-CoreSight ARM ETM implemented on the chip then no additional settings are required. If there is a CoreSight ETM and the control registers are memory mapped, then the debugger needs to know the base address:


Non-ARM and non-ETM trace modules like TI DSP cTools trace (TMS320C55x, TMS320C64x) use instead the option


Usage

The standard ETM features (Analyzer …, ETM …) can be used like on a non-CoreSight ETM. See ”ARM-ETM Trace” (trace_arm_etm.pdf) for details.

SYStem.CONFIG ETMBASE <accessclass>:<address>

SYStem.CONFIG TRACEBASE <accessclass>:<address>

Setup the Debugger for a CoreSight System 16 Embedded Trace Macrocell (ETM/PTM) ©1989-2015 Lauterbach GmbH

AMBA AHB Trace Macrocell (HTM)

Description

The HTM outputs information on an AHB bus on the chip. It gives visibility to bus information which can not be provided by the Embedded Trace Macrocell (ETM). You can get information about the bus utilization, free bus capacities and you can see if (cache, write buffer) and when a memory access happens and you get the time correlation between the bus access, program flow and data access.

The data can be passed - probably combined with other trace sources - via Funnel and AMBA Trace Bus (ATB) off-chip to the Trace Port Interface Unit (TPIU). There it will be captured by a trace port analyzer (ETM Preprocessor or CombiProbe). Alternatively it can be stored on-chip in the Embedded Trace Buffer (ETB) for later readout via JTAG or Serial Wire Debug Port (SW-DP).

Debugger Setup

The debugger needs to know the base address of the control register block:


SYStem.CONFIG HTMBASE <accessclass>:<address>

Setup the Debugger for a CoreSight System 17 AMBA AHB Trace Macrocell (HTM) ©1989-2015 Lauterbach GmbH

Usage

For the HTM similar commands as for the ETM are available. They provide the same functionality but for the HTM instead for the ETM:

On Cortex-M3 no data trace is available. The HTM could be used as a workaround to get the data information which is missing in the ETM trace. A mixed display of ETM and HTM trace data can be displayed and analyzed by the command:

HTM.<subcommand> ; commands to configure the AHB Trace; Macrocell (HTM)

HTMAnalyzer.<subcommand> ; HTM information via TPIU

; HTM information recorded by ; ETM preprocessor

HTM.viewHTMAnalyzer.List

; display the HTM settings; display recorded information

MergedAnalyzer.<subcommand>

MergedAnalyzer.List

Setup the Debugger for a CoreSight System 18 AMBA AHB Trace Macrocell (HTM) ©1989-2015 Lauterbach GmbH

Instrumentation Trace Macrocell (ITM)

Description

The ITM outputs system trace information. Software running on an ARM processor can write to memory mapped registers.

The data can be output directly to the Serial Wire Output (SWO) where it will be captured by the CombiProbe. Alternatively it can be output - probably together with other trace sources - via the AMBA Trace Bus (ATB) to the Trace Port Interface Unit (TPIU). There it will be captured by a trace port analyzer (ETM Preprocessor or CombiProbe). Another possibility is to store it on-chip in the Embedded Trace Buffer (ETB) for later readout via JTAG or Serial Wire Debug Port (SW-DP).

Debugger Setup

The debugger needs to know the base address of the control register block:


Besides this the ITM needs a synchronization clock. You can activate it e.g. by setting the SYNCTAP and CYCCNTENA bit in the DWT Control Register. See Cortex-M3 manual.

SYStem.CONFIG ITMBASE <accessclass>:<address>

Setup the Debugger for a CoreSight System 19 Instrumentation Trace Macrocell (ITM) ©1989-2015 Lauterbach GmbH

Usage

For the ITM similar commands as for the ETM are available, like

ITM.<subcommand> ; commands to configure the Instrumentation ; Trace Macrocell (ITM)

ITMAnalyzer.<subcommand> ; ITM information via TPIU

; ITM information recorded by; ETM preprocessor

ITM.viewITMAnalyzer.List

; display the ITM settings; display recorded information

Setup the Debugger for a CoreSight System 20 Instrumentation Trace Macrocell (ITM) ©1989-2015 Lauterbach GmbH

Funnel, AMBA Trace Bus (ATB), Replicator

Description

The Funnel is used to combine multiple trace sources into a single bus, called the AMBA Trace Bus (ATB). A Replicator is required if you need to (simultaneously) feed more than one trace sink like a Trace Port Interface Unit (TPIU) and an Embedded Trace Buffer (ETB). The trace data includes a source ID that the debug tool can identify the source of the trace packet.

Debugger Setup

There is no setup needed for the AMBA Trace Bus (ATB) and Replicator, but the debugger needs the base address of the Funnel control register block


and depending on the trace sources one or more of the funnel channel numbers the trace source is connected to

TRACEFUNNELPORT is for non-CoreSight trace sources, e.g. cTools TI DSP (TMS320C55x, TMS320C64x).

Usage

The settings are required for the debugger to control the trace recording of the Embedded Trace Macrocell (ETM), AMBA AHB Trace Macrocell (HTM), Instrumentation Trace Macrocell (ITM), … data. The features are described at these components.

SYStem.CONFIG FUNNELBASE <accessclass>:<address>

SYStem.CONFIG ETMFUNNELPORT <number>

SYStem.CONFIG HTMFUNNELPORT <number>

SYStem.CONFIG ITMFUNNELPORT <number>

SYStem.CONFIG TRACEFUNNELPORT <number>

Setup the Debugger for a CoreSight System 21 Funnel, AMBA Trace Bus (ATB), Replicator ©1989-2015 Lauterbach GmbH

Trace Port Interface Unit (TPIU)

Description

The TPIU formats and transmits the probably multi-source trace data coming from the AMBA Trace Bus (ATB) off-chip to the debug tool. The trace frequency is independent from the core clock and the data will be output on a parallel port configurable from 2 to 32 bit.

Debugger Setup

An ETM Preprocessor is required. The following figure shows the ETM Preprocessor LA-7992 AutoFocus II. Alternatively other types can be used like LA-7921 and LA-7991.

For 4-bit wide trace port and trace clock <= 200 MHz the CombiProbe can be used.

Figure: ETM Preprocessor AutoFocus II

Figure: CombiProbe

Setup the Debugger for a CoreSight System 22 Trace Port Interface Unit (TPIU) ©1989-2015 Lauterbach GmbH

The debugger needs to know the base address of the TPIU control register block


To activate external trace via TPIU instead into the Embedded Trace Buffer (ETB) you need to set

This is default if a ETM Preprocessor is connected to the debugger.

Usage

The port size and port mode can be selected. This will be done by Embedded Trace Macrocell (ETM) commands to be compatible with non-CoreSight ETMs which have the TPIU included:

SYStem.CONFIG TPIUBASE <accessclass>:<address>

Trace.Method Analyzer

ETM.PortSize <size>

ETM.PortMode <mode>

Setup the Debugger for a CoreSight System 23 Trace Port Interface Unit (TPIU) ©1989-2015 Lauterbach GmbH

Embedded Trace Buffer (ETB)

Description

The ETB stores trace data on-chip at high rates and at 32-bit data width. The data can be read out via JTAG or Serial Wire Debug Port (SW-DP) when the trace recording has ended. Also the components ETF and ETR can be used as onchip trace using the same setup commands.

Debugger Setup

In case of a non-CoreSight ETB you need to set the JTAG chain position (ETBIRPRE, ETBIRPOST, ETBDRPRE, ETBDRPOST) of the ETB TAP, otherwise the base address needs to be provided for ETB, ETF or ETR:


To activate ETB instead of the Trace Port Interface Unit (TPIU) you need to set

This is default if no ETM Preprocessor is connected to the debugger.

In case an ETR address is used by command SYStem.CONFIG.ETBBASE the debugger will read the target memory location from the ETR peripheral because usually an application would control these settings rather then the debugger. Therefore before the onchip trace can configured the target must run until the point where the ETR registers are initialized or they are initialized by script:

SYStem.CONFIG ETBBASE <accessclass>:<address>

Trace.Method ONCHIP

//use ETR as onchip traceSYStem.CONFIG ETBBASE DAP:0x80001000

//setup ram size register (RSZ) in 32 bit wordsd.s DAP:0x80001004 %LONG 0x80000 /v

//setup target base address (DBALO)d.s DAP:0x80001118 %LONG 0x04010000 /v

//initialize onchip traceo.init

Setup the Debugger for a CoreSight System 24 Embedded Trace Buffer (ETB) ©1989-2015 Lauterbach GmbH

Usage

The Onchip commands (Onchip …) can be used. They work the same way as the Analyzer …commands for the Trace Port Interface Unit (TPIU).

Setup the Debugger for a CoreSight System 25 Embedded Trace Buffer (ETB) ©1989-2015 Lauterbach GmbH

Serial Wire Viewer (SWV), Serial Wire Output (SWO)

Description

The Serial Wire Viewer provides an output for the Instrumentation Trace Macrocell (ITM) through a single pin, the Serial Wire Output (SWO).

Debugger Setup

A CombiProbe is required.

Besides the settings for the ITM the debugger needs to be informed that it gets the ITM data through the Serial Wire Output (SWO). The connector pin named TDO is used for that purpose. In order to use this pin for the ITM it is required to use the Serial Wire Debug Port (SW-DP) instead of the standard JTAG interface. As soon as SW-DP is activated

the CombiProbe expects ITM data at TDO. At the moment only UART protocol is supported.

SYStem.CONFIG SWDP ON

Figure: CombiProbe

Setup the Debugger for a CoreSight System 26 Serial Wire Viewer (SWV), Serial Wire Output ©1989-2015 Lauterbach GmbH

Usage

The ITM is a system trace therefore the system trace commands must be used:

ITM.<subcommand> ; commands to configure the Instrumentation ; Trace Macrocell (ITM)

SystemTrace.<subcommand> ; ITM information via Serial Wire Output

; ITM information recorded by CombiProbe

ITM.view ; display the ITM settings

SystemTrace.state ; display the CombiProbe trace; settings

SystemTrace.List ; display recorded information

Setup the Debugger for a CoreSight System 27 Serial Wire Viewer (SWV), Serial Wire Output ©1989-2015 Lauterbach GmbH

Embedded Cross Trigger (ECT), Cross Trigger Matrix (CTM), Cross Trigger Interface (CTI)

Description

The Embedded Cross Trigger (ECT) is a mechanism for passing debug events between multiple cores or modules. It can e.g. be used for halting cores synchronously or to trigger the trace capturing. It consists of a Cross Trigger Matrix (CTM) which broadcasts the event signals via channels and one or more Cross Trigger Interfaces (CTI) which enable the processor or module to react on a event and/or to broadcast events to the other processors or modules. The Cross Trigger Interfaces (CTI) need to be programmed to get the functionality you want (see description below). There is nothing to do with the Cross Trigger Matrix (CTM) which is a static implementation to broadcast the signals of the Cross Trigger Interfaces (CTI).

The Cross Trigger Interface (CTI) has a 4 KByte memory mapped register block. By writing to these register you can select which event shall be broadcasted and on which event you want to react.

It is up to the chip designer which event is routed to which CTI signal. There is just a recommendation from ARM in the CoreSight documents.

Debugger Setup

The debugger needs to know the base address of the register block that the peripheral file knows the location of the register.

<accessclass> is typically ’APB’ (default).

Usage

The CTI is not yet automatically used by the debugger, although a default programming is planned assuming the connections on the chip are done as ARM has recommended. To get a certain feature active the user needs to program the CTI himself. He can use the CTI peripheral file for this purpose:

For a detailed description of the CTI register functionality see DDI0314 CoreSight Components Technical Reference Manual chapter Embedded Cross Trigger which can be downloaded from the ARM web site at www.arm.com.

SYStem.CONFIG CTIBASE <accessclass>:<address>

PER percti.per

Setup the Debugger for a CoreSight System 28 Embedded Cross Trigger (ECT), Cross Trigger ©1989-2015 Lauterbach GmbH

http://www.arm.com

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