Settling Time of Opamp

8/11/2019 Settling Time of Opamp

1/7

IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-17, NO. 1, FEBRUARY 1982

Analysis of the Settling Behavior of an

Operational Amplifier

C.. CHUANG, STUDENTMEMBER,IEEE

,4bstruct-

The settling behavior of a pole-splitting compensated oper-

ational amplifier is analyzed using a second-order two-pole transfer

function. It is shown that although the slewing period of the amplifier

is well approximated by the commonly used formula for slew rate, the

settling behavior after the dewing period can only be fully explained

using a second-order two-pole transfer function.

Simple criteria

relating the circuit parameters to the damping ratio of a second-order

feedback system are given. Analytical expressions for the amplifier

responses and settling times are derived. The analysis is justitled by

clme correspondence with computer simulations.

I. INTRODUCTION

HE settling time of an operational amplifier is a direct

measure of the ability of the amplifier to deliver a large

input signal either step inputs or high-frequency sinusoidal

signals) [1] , [2] . Settling time is an important parameter in

many applications, such as A/D and D/A converters, and is

defined as the time taken for the output of the amplifier to

settle to within 0.1 or 0.01 percent of its final value after the

application of an input step. The settling time consists of two

distinct periods [1]. The first period is the slewing period

resulting from the limited available current of the input stage

to charge the compensation capacitor. During the slewing

period, the amplifier acts in a nonlinear fashion and the output

makes the transition from the original value to the vicinity of

the new value. After the slewing period, the amplifier starts

to settle to the final value in a quasi-linear fashion. Circuit

approaches such as input stage transconductance reduction

[3] and doublet pole-zero pair) compression [4] have been

used to reduce the settling time. However, little has been

done on the analysis of the settling behavior of an operational

amplifier. Kamath et al. [5] analyzed the effects of the doublet

on the frequency response and settling time of the operational

amplifier. As in most analyses [1], [2], a single dominant-

pole transfer function is assumed.

It is well known that when the amplifier starts to settle in

the quasi-linear region, the output may have underdamped

overshoot followed by damped sinusoidal), critically damped,

or overdamped exponentially approaching the final value)

response,

depending on circuit parameters. In high-speed

operational amplifiers, the slewing time can be very short,

and this second period can dominate the settling time of the

Manuscript received April 29, 1981; revised September 7, 1981. This

work was supported in part by the National Science Foundation under

Grant ENG-78-22193.

The author is with the Department of Electrical Engineering and

Computer Sciences and the Electronics Research Laboratory, Univer-

sity of California, Berkeley, CA 94720.

~c

v

Fig. 1. Simplified small-signal equivalent circuit for pole-splitting

compensated two-stageoperational amplifier.

amplifier. A second-order two-pole) transfer function has to

be considered to fully explain the settling behavior in this

quasi-linear region.

This paper analyzes the settling behavior of a pole-splitting

compensated [6] operational amplifier. The slewing period is

analyzed first and the result reduces to the familiar single

dominant-pole approach under certain approximations. Simple

criteria relating the circuit parameters to the damping ratio of

a linear second-order feedback system that determines whether

the response is underdamped, critically damped, or over-

damped are then given. Analytical expressions for the ampli-

fier response and settling time in each case are derived. These

expressions can be used to quickly estimate the amplifier per-

formance.

Finally, computer simulation results are given to

validate the analysis.

II. BASIC MODEL FOR CALCULATION OF TRANSIENT

RESPONSE

We assume that the amplifier can be well approximated by a

two-stage configuration with only two high impedance nodes

as illustrated in Fig. 1 [2], [6]. Each of the two stages is

assumed to be characterized by a transconductance, load resis-

tance, and load capacitance.

We also assume that the circuit

is compensated by a single pole-splitting capacitor CC.

It has been shown [2] , [6] that the transfer function can be

approximated by

vi

s

=

O

1-:

a s) =

s) 1+ ) k)

where

~o = ( nlZ?l)( 2~2)

1

1 = 1 +gmzRz)Rlcc

1)

2)

3)

0018-9200/82 /0200-0074 00.75 01982 IEEE


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CHUANG: SETTLING BEHAVIOROF AN OPERATIONALAMPLIFIER

~

Fig. 2. Operational amplifier model for analysis of the transient response

in voltage follower configuration.

4)

= if Cc, C2 >> Cl)

5)

and

gm2

Z1 = y.

(6)

c

We further assume that the right half plane zero has been

eliminated by circuit techniques such as inserting a source

follower to drive the right end of the compensation capacitor

from the output of the second stage [7] or inserting a nulling

resistc}r in series with the compensation capacitor [8] . The

transfkr function can therefore be written as

v~ s) =

a s

=

VI

s

,+42+4

(7)

\ u,/ \ W,j

This transfer function is adequate for small-signal linear

analysis of the amplifier. However, when a large step is applied

to the amplifier input, the amplifier responds in a grossly non-

linear fashion during the slewing period and a linear analysis is

unjustifiable. A model similar to the one used by Kamath

et al.

[5] which represents the situation in a practical amplifier

is shown in Fig. 2. The input stage is modeled as shown with

a mm imum available current 10 and a transfer characteristic

slope of gml for values of IVII less than 10 /gml. The whole

amplifier is connected in a voltage follower configuration.

Consider the situation when a step of magnitude V is applied

to the input. In general,

v>>

I J

gm ~

(8)

and V is large enough to cause current limiting in the input

stage. This is the slewing period of the amplifier, and the

feedback loop is effectively open during this period. When

the output voltage approaches within 10 /gml of

V,

the differ-

ential input stage enters the linear region and the whole circuit

settles to its final value with the feedback loop closed [5].

III. ANALYSIS

A. Slewing Period

During the slewing period, the input stage is limiting and

ll(s) = -

a. /gm~

vi(s) =11(s)

(1+ ) (l+ )

9)

75

lo)

Taking the inverse Laplace transform, we have

H

oIo

vi t)=

1

1- L e-wt + f e-r .

m 1

U2 - CJI

J2 - A l

11)

Notice that C.J2>> al so that e-f is a fast-decaying term.

We can approximate Vo(t) by

Vo(t) =

H

[1 - e-u]. 12)

At time

t= T.,

the output reaches

V- (10/gml )

and the whole

amplifier starts to settle as a linear feedback amplifier with the

initial condition

I.

VO(TJ = V-

()

10

v l-

gm 1

gmlv

The time T,, obtained by solving 12), is given by

13)

14)

A much simpler expression results if we make the approxima-

tion

e

WTS==1- COITS

15)

before solving 12) for

T..

Then

)

=~ V-L L

m

aocol

16)

Since

m

aotil =

cc

17)

6) can be written as

T_

R )=J-:)

I. [Cc SR

18)

where

SR II)ICC

(19)

is the familiar slew rate of an operational amplifier [1], [2], [6].

1Two initi~ conditions are required in a detailed analysisof a second-

order state-variable feedback system. However, it can be shown that

the approximation involved in neglectingthe initial condition for V2at

t = T,~s equivalent to the approximation 1 + gm1R2 ) ~ gm2R2.


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IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-17,NO. 1, FEBRUARY 1982

B. Linear ReBon

For t> T~, the amplifier operates linearly and the feedback

loop is closed. The transfer function becomes

~ s) _ 4)

A s)=-

v-~(s) 1+ a(s)

)

.

2

l+ao in

.

82 +-2&.Jns - -0;

()

aO

2

l+ao

r-

= [(s+ &un) + (an {~)]

(20)

where

Q; = (1 +ao)w1w2

~aoc.d1cd2

(21)

a )

(if Cc, C2 >> Cl) (22)

2@n =(UI +tiz)

(23)

and the initial condition at t= TJ is given by (13).

The closed-loop transfer function in (20) has poles at

S=-gLdn*dmc

Jn.

(24)

The nature of the closed-loop response depends almost com-

pletely on the damping ratio ~ [9]. The value of tin simply

adjusts the time scale.

If& is less than 1 (underdamped), the

closed-loop poles are complex conjugates; if & is equal to 1

(critically damped), both closed-loop poles are equal to -con;

and if ~ is greater than 1 (overdamped), both closed-loop poles

are real and negative.

To relate the damping ratio ~ to circuit parameters, notice

that from (21) and (23),

~=

+- 6++ -+)

1

=

(u, + (.02)

2< +ao)6-r1ti2

JJz

2=

(25)

JZm

(if CC,C , >> Cl).

(26)

24=

.

Hence, the conditions ~ 1 correspond, approximately, to

We will treat the three cases separately.

Case

I- Underdamped, ~

1

1

1

1

I

I

*t

T, tp

TSET

~~

Sl ewmg Pmod

Set tl , n g ,n Li near Reg,on

T,

T~L

Fig. 3 . Typical underdamped (O< g < 1) response of a vol tage follower

for a step input .

With the intial condition given by (13), it can be shown that

for t>

T,

~ y ]

(){

vii(t)= Q

l+ao

N.1

){

)

0

a.

~

v 1- * .-EU(-T)

l+ao

}

. sin [tin{= (t-

T.)+ ~] , t> T. (29)

where

d-

~ = tan-l

E

(30)

Here the actual frequency of oscillation in radians per second

is known as the damped frequency ad and is given by

[

=

(1 +ao)co1ti2 - W1 ~ti2)2 2

1

[

2

u~

=

aoti1ti2 -

4

(31)

[

)1

gm2

1 2

~gmlgmz___

cc C2

4 C2

(if CC, C2 >> Cl).

(32)

A typical oscillatory response is shown in Fig. 3 and pertinent

characteristics of the curves are labeled. These are discussed

below.

The period of oscillation

Td

associated with the damped fre-

quency cod is

(33)


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CHUANG: SETTLING BEHAVIOROF AN OPERATIONAL AMPLIFIER

Normalized percent overshoot.

Po

lO/gm,V

100

50

L

00

05

10

.

Fig. 4. Normalized percent overshoot as a function of the damping

ratio ~for the underdamped case.

The time to the maximum, or peak, value of the output is

tp.

The maximum value of V.(t) maybe found by taking the

derivi~tive of VO

(t)

with respect to

t

and equating the result to

zero. If this is done, it can be found that dVo

(t)/dt

s zero

when

()

=,~=T n >

2

rz=o, l,2, . (34)

~d

The peak value of V.(t)occurs when n = 1 or

and is given by

(35)

.o(t)mm=(~).{l+ [l-~ -~)]

WA

( )v{l+&ex& J}

(36)

The percent overshoot (PO) is 100 times the peak value of

Vo(t)

minus the final value, divided by the final value. From

(36), the percent overshoot is simply

p,,.,()()

~.*(1----J ]

,XP -J J

IOO(fi)ex- J

(37)

The percent overshoot (normalized with respect to 10 /gml V)

for a range of values of ~ i s shown in Fig. 4.

The settling time

T,et

is defined as the time required for the

response to remain within 0.1 percent of its final value. Since

the magnitude of the sinusoidal portion of (29) is always less

than or equal to 1, for convenience the settling time can be

apprc,ximated as the time beyond which the overshoot (or

undershoot) is less than 0.001 or

JQ--exp

(-d )

> Cl),

gm

~~

slewing

settling time in

period

linear region

(40)

Case11Critically Damped, ~=1:

In this case, both closed-

IOODpoles are equal to - con and the respose with initial condi-

tion (13) can be shown to be

()

i(t)= ~

V[l - e

- (t-TJ

l+ao

()

I.

- Un(t - Ts)e

- (WS)] + 1 _

gmt

[e

_Un(r-~~) + ~n(t - T~)e

-con(t-T~)

(*) {l-* e-wn(-Ts) ]

+@n(t - T~)e

wn(t-Ts)]}, t> T..

(41)

The settling time is therefore determined by

gjv

e

-un ~~et~s

~n(T,e, - TJ e

-n(Te-T)]=

0.001

(42)

or

[1 4T,.t -

]e

Wiz( et~s) _ g?rrv

_.

100010

(43

The settling time for this case can be determined through

graphical solution of (43). In practice, as the damping ratio

approaches 1 from either above or below, it becomes more

and more difficult to establish the actual damping ratio by

input-output measurement of the closed-loop system.

Case 111Overdamped, ~ >1: In this case, the closed-

loop transfer function has two real negative poles located at

,=-gankwnd~.

(44)

The response for

t>

T~

with initial condition (13) can be

shown to be

( ){

()

.

vi(t) ~ ~ v 1-

grnlv

l+ao

2-

[(g+m)

. exp(-c+(t -

T.)( - ~)) - ( - ~)

}

exp(-on(t -

TJ(& +~))] , t> Ts.

(45)


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IEEE JOURNAL OF SOLID STATE CIRCUITS VOL. SC 17 NO. 1 FEBRUARY 1982

Note that the exp (- tin(t - Ts)(g ~ ~)) term is the

slowly- decaying term. The settling time can therefore be deter-

mined approximately from

1

.

exp (- tin(T~et - T~)(~ - ~)) = 0.001. (46)

Solving for

T~et,we

have

\

?

slewing

settling time in linear region

period

(47)

IV, COMPUTERSIMULATION

Direct measurements and experimental verification of the

circuit behavior described above are djfficult to perform in

practice because most modern operational amplifiers have

unity-gain compensation included on the monlithic chip and

the effects of different parameters in the circuit are difficult

to isolate.

To validate the analysis, a computer simulation using the

SPICE 2 [10], [11], circuit-analysis program has been per-

formed on a basic CMOS two-stage operational amplifier [8].

The circuit configuration is shown in Fig. 5 and the pertinent

parameters are as follows:

10 =9.11 X 10-6 A

gml = 2.03 X 10-5 A/V

gmz = 1.82X 10-4 A/V

1

Rn=-n

gm

a. =

5248

Cz = 5.0 pF.

(48)

The compensation capacitor Cc is varied from 1.0 to 4.5 pF,

giving rise to a damping ratio ranging from 0.53 to 1.19. The

results of the computer simulation and the analysis for the

transient response with a -2.5 V input step applied to the

CMOS operational amplifier in a unity-gain voltage follower

configuration are shown in Fig. 6(a) for comparison. The

graphs of Fig. 6(a) are then shown in expanded scales in Fig.

6(b) and (c) to allow observation of the overshoot, damped

oscillatory behavior, and 0.1 percent settling time. The close

correspondence between the analysis and the computer simu-

lation is evident.

V.

DISCUSSION

As can be seen from the above amdysis, the slewing period of

an operational amplifier is well approximated by the familiar

formula (19) for slew rate.

On the other hand, the settling

behavior of the amplifier after the slewing period can only

9rn

9m2

0.0

R,

c

cc

.m

~

Blasdng current source of the f[rst stage

=911x 10-e A

Transconductonce of the f rst stage

=203 x10-

A/V

Tronsconductance of the second stage

=182 x10-4 A/V

Open loop voltage ga[n

=5248

Nulllng res, s tor : ~ Q

Load

cxpac fence =

OpF

Comp ens ati on c ap ac bt or , v ar ied t o c han ge d ar np ,n g r atmc

Fig. 5. Configuration of a basic CMOS two-stage operational amplifier

and pertinent parameters used in the computer simulation.

be fully explained using a second-order (two-pole) transfer

function.

The normalized 0.1 percent settling time in the

linear region [(39) and (47)], which we denote as tin

T~L, is

plotted as a function of the damping ratio ~ with the quan-

tity 10/gml V as a parameter in Fig. 7. It can be seen that (47)

is very accurate for values of greater than 1.1. When the

damping ratio . approaches 1 from above, the exp (- tin(f -

TJ( +~)) term in (45) becomes more and more sig-

nificant in determining the settling time. As this term is of

opposite sign to the exp (- Un(t -

T~)( - ~))

term,

the actual settling time is shorter than that given by (47). The

range for which is greater than 1.5 is seldom of any interest

because of the requirement of a huge compensation capacitor

and the resulting long slewing and settling times. In general,

for a fwed step size

V,

if we decrease the ratio gm~/10 while

keeping the unity-gain frequency aotil constant (or equiva-

lently, keeping the gun constant), the slewing period T~will

decrease, while the settling time in the linear region

T~L

will

increase. A logarithmic plot of

T~,T~L,

and

T~et

versus 10/gm~V

in the underdamped case for CC = 1.0 pF is shown in Fig. 8.

It can be seen that the total settling time Tset decreases as we

increase 10/gml V due to the decrease in T~, but only up to

(approximately) the point where T, has become smaller than

T=.

For larger values of 10/gn,

V,

no further decrease of the

total settling time is found because of the slowly increasing

value of

T L.

VI.

CONCLUSION

We have analyzed the settling behavior of a pole-splitting

compensated operational amplifier using a second-order (two-

pole) transfer function. Criteria relating the circuit parameters

to the damping ratio of a second-order feedback system have

been given and analytical expressions for amplifier responses

and settling times were derived. Computer simulation justified

the validity of the analysis. The results should prove very

useful in estimating amplifier performance.


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CHU,4NG: SETTLING BEHAVIOROF AN OPERATIONALAMPLIFIER

79

Vo volts)

1

-3.0

l

Analysis

---

Simul at ion SPICE 2)

L

2.5

10/gmi

[~

d ?[ ?./ - {

L INEAR REGION

=0.449V

2 o

-

v

1.5

/

/

/

/ /

I///

I1lIX

/

-1.0

; , ,/ ,/

/, ,/

11 /,/

0.5

/1 /,

] j /,,~

1

00

0.5

Vo volts:

2.6

2.5

2,4

2.3

.

1

I

1

1.0 1.5

2.0

T]me pee)

a

Analysis

--- Snmulatkan SPICE 2)

b

1

I

Vo volts)

2.51

Analysts

---- S[mulatmn SPICE 2)

I

srf

..___-l

..77 -. -

2.50 _____+

-; L\_

1-.- -- /L_

__________

0 1 @

;;

20.1/.

2.481

1

I 1 I

o

0.5

I.0

I.5

2.0

Time ~sec)

c

Fig. 6. Comparison of the analyzed and computer simulated transient

responses of the amplifier in voltage follower configuration. a Linear

voltage scale. b , c Expanded voltage scale.


7/7

80

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 1, FEBRUARY 1982

wnT,L

1

35 -

30 -

25 -

20 -

15

10 -

5

Normal ued 0. 1% Set tl{ng T me 1. L,near Regi on

I

UNDERDAMPED+

Eq (39)

m

urveo/gmlv

0.025

2

0,050

3

0,100

4

0.200

5

0.400

+ OVEROAMPED

Eq. (47)

Exact7 from

Eq. (45)

I

00

I

0.5

1.0 I .5

%

(oQmpl.g

RotIo)

Fig. 7. Normalized 0.1 percent settling time in the linear region as a

function of the damping ratio ~.

Tim:( sec)

\

T~ Eq. (14)

5.0 \

--.

T,L . Eq. (39 )

\,

-- h=TS TSL

Eq.39)

\

\

\.

\

\.\

1.0

~.

=. =._._,_-

/--

---

/-

,,-

0. 0 :

0.01

1 1

0.01

0. I I .0 Io/gm,v

Fig. 8. Logarithmic plot of T , T L, and T~et versus lo/gml V in the

underdamped case for Cc = 1.0 pF. The rest of the parameters are

as shown in Fig. 5.

ACKNOWLEDGMENT

The author gratefully

of Prof. R. M. White.

appreciated.

acknowledges the help and support

The comments of the reveiwers are

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

REFERENCES

P. R. Gray and R. G. Meyer, Recent advances in monolithic

operatiomd amplifier design,

IEEE Trans. Circuits Syst .

vol.

CAS-21, pp. 317-327, May 1974.

J. E. Solomon,

The monolithic op-amp: A tutorial study:

IEEE J. Solid State Circuits VOLSC 9 pp. 314-332, Dec. 1974.

J. C. Schmoock, An input transconductance reduction technique

for high-slew rate operational amplifiers, IEEE J. Solid State

Circuits vol. SC-10, pp. 407-411, Dec. 1975.

R. J. Apfel and P.R. Gray, A fast-settling monolithic operational

amplifier using doublet compression techniques, IEEE J. Solid

State Circuits vol. SC 9 pp. 332-340, Dec. 1974.

B. Y. Kamath, R. G. Meyer, and P. R. Gray, Relationship be-

tween frequency response and settling time of operational ampli-

iiers~

IEEE J. Solid State Circuits VOLSC 9

pp. 347-352, Dec.

1974.

P. R. Gray and R. G. Meyer,

Analysis and Design of Analog

Integrated Circuits. New

York: Wiley, 1977.

Y. P. Tsividis and P. R. Gray, An integrated NMOS operat ional

amplifier with internal compensation, IEEE J. Sol id State Cir

cuits vol. SC-11, pp. 748-753, Dec. 1976.

P. R. Gray, Basic MOS operational amplif ier des ignAn over-

view, in Arrirlog MOS Integrated Circuits P. R. Gray, D. A.

Hodges, and R. W. Brodersen, Eds. New York: IEEE Press,

1980, pp. 28-49.

R. C. Dorf, Modern Control Systems 2nd ed. Reading, MA:

Addison-Wesley, 1974.

L. W. Nagel , A computer program to simulate semiconductor

circuits, Electron. Res. Lab., Univ. California, Berkeley, Memo.

ERL-M520, May 1975.

E. Cohen, Program reference for SPICE 2, Electron. Res. Lab. ,

Univ.California, Berkeley,Memo.ERL-M592,June 1976.

a Research Assistant in

C. T. Chuang (S78)

was born in Taiwan on

January 11, 1953. He received the B. S.E.E.

degree from National Taiwan Universi ty, Tai-

pei, Taiwan, in 1975.

From 1975 to 1976 he was a Teaching Assis-

tant in the Department of Electr ical Engineer-

ing, National Taiwan University, Taipei. From

1976 to 1977 he was with Department of Elec-

trical Engineering, University of South Carolina,

Columbia, doing research on thermal analysis

for silicon web ~owth. Since 1977 he has b~en

the Electronics Research Laboratory. University

of California, Berkeley, where he is currently working tow;d the Ph.D.

degree . His main research interest is in the area of solid-state devices,

integrated circuits, and microwave acoustics.

Settling Time of Opamp

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