Sequential Circuits IEP on Synthesis of Digital Design 2007 1 Sequential Circuits S. Sundar Kumar...

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Sequential CircuitsIEP on Synthesis of Digital Design 2007

Sequential CircuitsSequential Circuits

S. Sundar Kumar Iyer

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AcknowledgementAcknowledgement Slides taken from http://

bwrc.eecs.berkeley.edu/IcBook/index.htm

which is the web-site of “Digital Integrated Circuit – A Design Perspective” by Rabaey, Chandrakasan, Nicolic

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OutlineOutline

Background and naming conventions Timing constraints and stability issues MUX based latch and registers Cross-coupled pair Implementations

Pseudo-static, C2MOS, TSPC, … Pipelining

Schmitt Trigger and Multivibrators

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Sequential LogicSequential Logic

2 storage mechanisms

• positive feedback

• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs

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Naming ConventionsNaming Conventions

Rabaey’s Convention a latch is level sensitive a register is edge-triggered

There are many different naming conventions For instance, many books call edge-

triggered elements flip-flops This leads to confusion however

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Latch versus RegisterLatch versus Register Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

Register

stores data when clock rises

Clk Clk

D D

Q Q

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LatchesLatches

In

clk

In

Out

Positive Latch

CLK

DG

Q

Out

Outstable

Outfollows In

In

clk

In

Out

Negative Latch

CLK

DG

Q

Out

Outstable

Outfollows In

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Latch-Based DesignLatch-Based Design

• N latch is transparentwhen = 0

• P latch is transparent when = 1

NLatch

Logic

Logic

PLatch

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Timing DefinitionsTiming Definitions

t

CLK

t

D

tc 2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q

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Characterizing TimingCharacterizing Timing

Clk

D Q

tC 2 Q

Clk

D Q

tC 2 Q

tD 2 Q

Register Latch

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Maximum Clock FrequencyMaximum Clock Frequency

FF’s

LOGIC

tp,comb

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delay

tclk-Q + tp,comb + tsetup = T

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Positive Feedback: Bi-StabilityPositive Feedback: Bi-StabilityVi1 Vo2

Vo2 =Vi1

Vo1 =Vi2

Vi1

A

C

B

Vo2

Vi1=Vo2

Vo1 Vi2

Vi2=Vo1

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Meta-StabilityMeta-Stability

Gain should be larger than 1 in the transition region

A

C

d

B

Vi2

5V

o1

Vi1 5Vo2

A

C

d

B

Vi2

5V

o1

Vi1 5Vo2

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Writing into a Static LatchWriting into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

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Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ InClkQClkQ

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Mux-Based LatchMux-Based Latch

CLK

CLK

CLK

D

Q

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Mux-Based LatchMux-Based Latch

CLK

CLK

CLK

CLK

QM

QM

NMOS only Non-overlapping clocks

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Master-Slave (Edge-Triggered) Master-Slave (Edge-Triggered) RegisterRegister

1

0D

CLK

QM

Master

0

1

CLK

Q

Slave

QM

Q

D

Two opposite latches trigger on edgeAlso called master-slave latch pair

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Master-Slave RegisterMaster-Slave Register

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexer-based latch pair

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Clk-Q DelayClk-Q Delay

D

Q

CLK

2 0.5

0.5

1.5

2.5

tc2 q(lh)

0.5 1 1.5 2 2.50time, nsec

Volt

s

tc2 q(hl)

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Setup TimeSetup Time

D

Q

QM

CLK

I2 2 T2

2 0.5

Volt

s

0.0

0.2 0.4time (nsec)

(a) Tsetup5 0.21 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0

DQ

QM

CLK

I2 2 T2

2 0.5V

olt

s

0.0

0.2 0.4time (nsec)

(b) Tsetup5 0.20 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0

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Reduced Clock Load Reduced Clock Load Master-Slave RegisterMaster-Slave Register

D QT1 I1

CLK

CLK

T2

CLK

CLKI2

I3

I4

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Avoiding Clock OverlapAvoiding Clock OverlapCLK

CLK

A

B

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK

Need to use non-overlapping clocks 1 and 2

Must be careful about limiting the non-overlapping period

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Overpowering the Feedback Loop ─Overpowering the Feedback Loop ─Cross-Coupled PairsCross-Coupled Pairs

Forbidden State

S

S

R

QQ

Q

QRS Q

Q00 Q

101 0

010 1

011 0RQ

NOR-based set-reset

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Cross-Coupled NANDCross-Coupled NAND

S

QR

Q

M1

M2

M3

M4

Q

M5S

M6CLK

M7 R

M8 CLK

VDD

Q

Cross-coupled NANDsAdded clock

This is not used in datapaths any more,but is a basic building memory cell

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Sizing IssuesSizing Issues

Output voltage dependence on transistor width

Transient response

4.03.53.0W/L5 and 6

(a)

2.52.00.0

0.5

1.0

1.5

2.0

Q (

Vo

lts)

time (ns)

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

W = 1 m

3

Vo

lts

Q S

W = 0.9 m

W = 0.8 m

W = 0.7 mW = 0.6 m

W = 0.5 m

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Storage MechanismsStorage Mechanisms

D

CLK

CLK

Q

Dynamic (charge-based)

CLK

CLK

CLK

D

Q

Static

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Making a Dynamic Latch Pseudo-StaticMaking a Dynamic Latch Pseudo-Static

D

CLK

CLK

D

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Other Latches/Registers: COther Latches/Registers: C22MOSMOS

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

“Keepers” can be added to make circuit pseudo-static

Clocked CMOS

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Insensitive to Clock-OverlapInsensitive to Clock-Overlap

M1

D Q

M4

M2

0 0

VDD

X

M5

M8

M6

VDD

(a) (0-0) overlap

M3

M1

D Q

M2

1

VDD

X

M71

M5

M6

VDD

(b) (1-1) overlap

May have dual edge registers

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Other Latches/Registers: TSPCOther Latches/Registers: TSPC

CLKIn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

True Single Phase Clocked Registers (avoids CLK’)

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Including Logic in TSPCIncluding Logic in TSPC

CLKIn CLK

VDDVDD

QPUN

PDN

CLK

VDD

Q

CLK

VDD

In1

In1 In2

AND latchExample: logic inside the latch

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TSPC RegisterTSPC Register

CLK

CLK

D

VDD

M3

M2

M1

CLK

Y

VDD

Q

Q

M9

M8

M7

CLK

X

VDD

M6

M5

M4

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Pulse-Triggered LatchesPulse-Triggered LatchesAn Alternative ApproachAn Alternative Approach

Master-Slave Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:

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Pulsed LatchesPulsed Latches

CLKGD

VDD

M3

M2

M1

CLKG

VDD

M6

Q

M5

M4

CLK

CLKG

VDD

XMP

MN

(a) register (b) glitch generation

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Pulsed LatchesPulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

P1

M3

M2D

CLK

M1

P3

M6

Qx

M5

M4

P2

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Hybrid Latch-FF TimingHybrid Latch-FF Timing

20.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.20.0 0.4

QD

time (ns)

Vo

lts

0.6 0.8 1.0

CLKDCLK

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PipeliningPipeliningR

EG

RE

G

RE

G

log

a

CLK

CLK

CLK

Out

b

RE

GR

EG

RE

G

log

a

CLK

CLK

CLK

RE

G

CLK

RE

G

CLK

Out

b

Reference Pipelined

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Latch-Based PipelineLatch-Based Pipeline

F G

CLK

CLK

In Out

C1 C2

CLK

C3

CLK

CLK

Compute F compute G

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Non-Bistable Sequential Circuits─Non-Bistable Sequential Circuits─Schmitt TriggerSchmitt Trigger

In Out

Vin

Vout VOH

VOL

VM– VM+

•VTC with hysteresis

•Restores signal slopes

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Noise Suppression using Schmitt Noise Suppression using Schmitt TriggerTrigger

Vin

t0

VM

VM

t

Vout

t0 + tp t

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CMOS Schmitt TriggerCMOS Schmitt Trigger

Moves switching thresholdof the first inverter

Vin

M2

M1

VDD

X Vout

M4

M3

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Schmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC

2.5

VM2

VM1

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4 . The width isk* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

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CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)

VDD

VDD

OutIn

M1

M5

M2

X

M3

M4

M6

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Multivibrator CircuitsMultivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

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Transition-Triggered MonostableTransition-Triggered Monostable

DELAY

td

In

Outtd

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Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

0.0

0.0

0.5

1.0

1.5

2.0

2.5V1 V3 V5

3.0

20.50.5

time (ns)

Vo

lts

1.0 1.5

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Differential Delay Element and VCODifferential Delay Element and VCO

in2

two stage VCO

v1

v2

v3

v4

Vctrl

Vo2 Vo1

in1

delay cell

simulated waveforms of 2-stage VCO

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

20.51.5

V1 V2 V3 V4

time (ns)2.5 3.5

Sequential Circuits IEP on Synthesis of Digital Design 2007 1 Sequential Circuits S. Sundar Kumar...

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Transcript of Sequential Circuits IEP on Synthesis of Digital Design 2007 1 Sequential Circuits S. Sundar Kumar...