Lloyd Dixon

Summary:The SEPIC converter combines the best features

of the boost and flyback topologies. making it

especially advantageous in high power factor

preregulator applications.In addition, ripple current can be steered away

from the input, dramatically reducing input noise

filtering requirements.This paper discusses the design of the SEPIC

converter, design of the coupled inductor to achieve

ripple current steering, and Zero Voltage Transition

circuitry to minimize switching losses.

The SEPIC Preregulator:

A Single-Ended Primary Inductance Converter

(SEPIC) is shown in Fig. 1, configured as a non-

isolated high power factor preregulator .

The SEPIC converter uses two inductances. The

input inductor Ll together with the switch resem-

bles a simple boost topology, whereas the shunt

inductor L2 location is similar to a buck-boost, or

flyback topology.

inductance (LL) is located in series with L1 in theinput, the high frequency ripple current is steeredaway from L1 and into L2, thus greatly easing inputnoise fIltering requirements.

The main advantages and disadvantages of theSEPIC high power factor preregulator are:

PROs:.Single switch.Continuous input current (like Boost)

.Any output voltage (like Flyback).

.Ripple current can be steered away from input,reducing the need for input noise filtering.

.Inrush/overload current limiting capability.

.Switch location facilitates MOSFET gate drive.

.Outer loop control scheme identical toBoost-UC3854 can be used in same manner.

.Possibility of isolation/step down using secondaryinductor winding, if a way can be found to avoidleakage inductance problems.

CONs:.Higher switch/diode peak voltages and currents

compared to boost topology..Bulk capacitor size/cost will be greater if operat-

ed at lower voltage than boost.

SEPIC Circuit OperationIn most high power factor preregulator applica-

tions, the switching frequency is very much greaterthan the 50-60Hz line frequency. Except for thebulk filter capacitor, the inductor and capacitorvalues in the power circuit are based upon switch-ing frequency (HF) considerations, Their imped-ances are negligible at line frequency (LF). Thus,instantaneous values along the rectified line wave-form are regarded as "dc" values when analyzingHF operation.

Fig 1. -SEPIC Power Circuit

In a conventional SEPIC converter, inductors Lland L2 are independent. This paper will show thatimproved dynamic performance is obtained bycoupling these inductors. More importantly, if thecoupled inductor is designed so that its leakage

High Power Factor SEPIC Preregulator

and Vcc cancel, so that Vo also appears across £1,with its dotted end also negative. ILl and 112 bothramp downward at the same rate: VoI£.

While the switch is OFF, IlN charges Cc. Whilethe switch is ON, Cc is discharged by 112. Althoughthe steady-state average Vcc equals V IN, the nearlyrectangular current wavefonn through Cc results ina triangular ripple voltage across Cc.

By inspection, note that although the switch andrectifier conduct alternately, both block (VlN+VO),and both conduct (llN+I12). Also, if D is the switch

duty cycle,(1)/0 = (1IN+IL2)(l-D)

Since steady-state (and LF) lcc must equal zero,

10 = IL2 (2)

(3)

Obviously, by inspection,

IIN = ILl

Assuming 100% efficiency, VoIo = VINlIN, and

I [2 = 10 = I IN(V IN/V 0) (4)

Thus with VIN = 220V, Vo = 200V and 200W,Fig. 2 shows lo(avg) = lA and lIN(avg) = O.9A.

Since the steady-state (and LF) voltage acrossany inductor must equal zero, the volt-secondsapplied to L2 (and Ll) during the ON time must beopposed by equal volt-seconds during the off time.Thus:

Coupling capacitor Cc is an important element inthe SEPIC topology. Its voltage offset allows theSEPIC's boost-like inductor input to coexist with anoutput voltage which may be less than VIN.

The steady-state average voltage across Ccalways equals VIN. To demonstrate this, look at thecircuit mesh including VIN, CC, and inductances L1and L2. Since the steady-state average voltageacross all inductor windings must equal zero,VCC(avg) must equal VIN. In a practical SEPIC pre-regulator, Cc is small (=0.5pF for 200W), so thatVCC(avg) tracks the rectified line voltage. A smalltriangular HF ripple voltage also appears across Cc.

Fig. 2 shows the inductor currents in a conven-tional 200 Watt SEPIC converter operating atIOOkHz with VIN=220V, IIN(avg)=0.9A, andVo=200V .Inductors L1 and L2 are equal ( 4mH)and independent (not coupled). Input ripple is

250mAp-p.Circuit explanation: Refer to the waveforms of

Fig. 2 and the circuit of Fig. 1 with the inductorsindependent. When the switch is ON, the instanta-neous rectified line voltage, VIN, is applied to L1,with its dotted end positive. At the same time, Vcc= VIN is applied to L2, with its dotted end alsopositive. Since L1 = L2, ILl and 112 ramp upward at

the same rate: VIN/L. The switch current is the sumof ILl (input current) and ILl. The rectifier reversevoltage equals VIN plus Vo.

When the switch is OFF, the currents flowingthrough L1 and L2 force their voltages to reverseuntil the output rectifier conducts current (Iu+I12),previously conducted by the switch. L2 is clampeddirectly across Vo with its dotted end negative. VIN

140

120

Vov IND = V o(l-D) ; D = (5)(V1N+V 0)

Note that the duty cycle relationship above forthe SEPIC converter is identical to the buck-boost(flyback) topology, even though the input currentcharacteristic closely resembles a boost converter.

Ripple Current SteeringIdentical voltages are applied to Ll and L2 at all

times throughout the switching period. This permitsthe inductors to be coupled by winding them (withequal turns) on a single magnetic core. (In order tomaintain the same total ripple current and sametotal inductive energy storage, the coupled induc-tance value is halved: 2mH.) Referring to Fig. 3,

~

IDOOU OUDU '.'DU 7OOU a>&JTIME.. Secs

-SEPIC Waveforms, Independent Inductors

[1)-IIN, [2)-1l2

UNITRODE CORPORATION

Fig. 3 -SEPIC with Coupled Inductors

the coupled inductor is designed so that its leakageinductance, LL, is located in series with winding Llin the input In this example, LL is 10% of the 2mHmutual inductance, or 0.2mH. The high impedanceof LL in series with Ll opposes the ripple current,forcing most of it into winding L2, which has onlythe relatively low impedance of Cc in opposition.As shown in Fig. 4, the triangular HP ripple currentthrough L2 is increased to 500mAp-p. The inputripple is reduced to only 50mAp-p (mostly at thelOOkHz fundamental), greatly diminishing the inputnoise filtering requirements.[l]

!Jil

1000U 3O0U 5O0U 700U QOOUTNE " Seco

SEPIC Waveforms, Coupled Inductors

[lJ-IINI [2J-IL2 .

The design of the coupled inductor to achievethis important result is given in a separate paper.l2]

To summarize, the diversion of ac ripple from Llto L2 occurs because (a) although the total cUlTentin coupled windings Ll and L2 is difficult tochange, current can easily transfer from one wind-ing to the other, and (b) the high impedance of LLopposes the ac ripple CUlTent in input winding Llwhile the low impedance of Cc provides an easypath for the HF ripple CUlTent through winding L2.

The single coupled inductor is also smaller andcosts less than two independent inductors with thesame energy storage capability .

Design Considerations: The coupled inductancevalue Ll = L2 is made as small as possible to

reduce cost/size and improve frequency response,limited by the amount of ripple current that can betolerated. In this application, 2mH results in aworst-case ripple of 0.65App at highest VIN =

365V pk. This is best calculated during the OFF timewhen Ml2/tOfF = Vo/L. Max tofF can be calculated

at max VIN using Eq. 5.A large LL-Cc product results in low input

ripple, but impairs frequency response and increasescost. It is better to make Cc small to reduce inrushsurge and cost. LL should be correspondingly largeprovided it can be integrated into the design of thecoupled inductor to eliminate its size/cost.

Worst-case input ripple (and EMI) is at the lowline peak and full load. A near-rectangular currentwaveform passes through Cc: lIN when the switchis OFF, and IL2 (=10) in the other direction whenthe switch is ON. This current waveform producesa triangular ripple voltage across Cc. This is bestcalculated during the ON time when ~VCC/tON=-10/CC. 10 = 2A at 400Wpk, 200V out. Max toN can

be calculated from Eq. 5 at min VIN. In this applica-tion, a Cc of 0.5pF results in 25.6Vpp worst-case atlow-line VINpk = 113V, and 400W.

The triangular ripple voltage across Cc appearsdirectly across LL. LL integrates this triangularvoltage into a quasi-sinusoidal waveform (which isthe input ripple). The peak-peak fundamental is.{2f{3 of a peak -peak triangular waveform, or 21 V ppin this application. Dividing by Xu = 130.0. (0.2mH

at 100kHz) obtains 0.16App input ripple at 4OOWpkand low-line VINpk. (Fig. 4 shows SOmA ripple at220V input and 200W .)

Resonance problems: The coupled-inductorSEPIC topology has an unusual high-Q resonanceeffect involving leakage inductance LL and couplingcapacitor Cc. In Fig. 3, examine the circuit meshinvolving VIN, the inductances, and Cc. The acimpedance of VIN is quite low (an input noise filtercapacitor). Inductors Ll and L2 are tightly coupledin opposition, so their impedances cancel. The onlysignificant ac impedances in this loop are LL and

6-3High Power Factor SEPIC Preregulator

V1N+VO IJN (6)IIN+IO = IINVo D

From this viewpoint alone, Vo in the range ofl00-150V is probably optimum for 120V lineinput, resulting in peak switch and rectifier voltagesof 300-350V. For single range 220V, or for120V/220V input, Vo of 200V results in peakvoltages approaching ~V at high 220V line.

Bulk capacitor size and c~t: For the same bulkenergy storage capability, electrolytic capacitor sizeand cost tend to vary inversely with voltage rating(more about this later). This consideration alonefavors a high Vo, limited by capacitor reliabilityconsiderations.

Bus voltage requirements: Power distributionbus voltage will probably not be a factor in thisdecision. This SEPIC converter does not providethe line isolation usually dictated by safety require-ments. Because an additional stage is required toobtain isolation, the bulk energy can be stored atany voltage, based on the previous considerations.

Bulk Energy Storage Requirements:A bulk energy storage device -a capacitor or

battery -is an essential element in any high powerfactor system. At a minimum, power must be pro-vided to the downstream load while the line voltagewaveform transits through zero. Many systemsdefine a longer "hold-up time" requirement wherefull load power must be supplied while the lineinput is temporarily inte1TUpted. Capacitors arenormally used for bulk energy storage when hold-up time requirements are in the tens or hundreds ofmilliseconds. For longer hold-up times, capacitorsize and cost becomes prohibitive, so batteries areused.

When holdup requirements are minimal, a smallbulk capacitor may provide the required energystorage, but other factors may then become domi-nant:I.

=Cc. With 0.5pF and 0.2mH used in this example,they will resonate with high Q at 16KHz. LL andCc are tightly coupled to each other at all timesduring the switching period. Even when the switchis closed, LL and Cc are coupled through the tightlycoupled Ll and L2 windings.

Unless damped, shock-excited oscillations willsend considerable 16KHz ripple back through theinput. Theoretically, damping would be achieved ifthe input current control loop had significant gainat the 16KHz resonant frequency. However, acrossover frequency well above 16 KHz is notpractical, as will be explained later. So damping isaccomplished by the "brute-force" method usingdamping network RD and CD in shunt with Cc.(Series damping is impractical because of highlosses due to the high ac current through Cc.)

To achieve critical damping requires a shunt RDequal to 1/2 of the resonant impedance. But thisrequires a large blocking capacitor CD, increasingcost and reducing the resonant frequency. As acompromise in this application, RD of 10 Ohms isin series with CD of 2.5pF, resulting in Q = 1,

underdamped but adequate. CD reduces the self-resonant frequency to 8KHz, but at the looKHzswitching frequency, the coupling network is stilleffectively 0.5pF. Normal operating loss in RD isless than 2W. but may be 6W with output shorted.

Output Voltage LevelIn a boost preregulator, there is little choice -in

order to function, the output voltage must be greaterthan the highest peak VIN. Thus for a dual range(110/220V) input, the output voltage is normally385V to 400V.

For the SEPIC converter, no such constraintexists. Theoretically, the output voltage can be anyvalue -above or below the input voltage. However,there are several practical considerations.

Voltage and current ratings: In general, theSEPIC converter is "most comfortable" when Vo =VIN, and D = 0.5. When Vo is much greater or

much smaller than VIN, peak voltages and peakcurrents become extreme. Peak switch and rectifiervoltage is VIN+Vo. Peak current through thesedevices (neglecting HP ripple) is lIN+lo. Substitut-ing 10 from Eq. 4:

The trade-off between voltage control loopdynamics and input third harmonic distortionbecomes severe with a small bulk capacitor.The capacitor current rating (120Hz ripple cur-rent plus lOOkHz switched current) can be

2.

6-4 u NITRODE CORPORA TION

handle this situation, but there is an additionalserious complication: Resonance between LL and Ccputs two poles in the control-to-input-cUlTentcharacteristic. There is also a pole due to coupledinductor £11£2, which varies with load. Thus thereare three active poles (one variable) above the LL-Cc resonant frequency (10-15 kHz). This makes itimpractical to achieve a crossover frequency, fc ,above resonance. But with a lower crossoverfrequency there is insufficient loop gain to dampenthe high Q LL-Cc resonant peak.

The solution to this problem is to use averageCMC of the average switch current. The switchcurrent waveform is chopped, whereas the inputcurrent is continuous with a very small ripple. Eventhough their waveshapes are radically different,average switch current equals average input current(at frequencies below LL-Cc resonance). The con-trol-to-switch-cUlTent characteristic is identical tothe control-to-input-cUlTent characteristic, except theswitch cUlTent characteristic does not have the extratwo resonant poles. Thus it is easy to control theswitch cUlTent using average CMC. (peak CMCwon't do-the peak current is much greater than theaverage.) Since the £L-CC resonant circuit is nowoutside the control loop, it would ring if not for thedamping network, RD and CD.

An additional important benefit of controllingaverage switch current: Switch cUlTent is discontin-uous, allowing the use of a cUlTent transformer(CT) for CUlTent sensing. This is not possible withinput cUlTent, nor is there any apparent way tosynthesize the input current waveform.

The optimized average CMC method is wellsuited to any high power factor preregulator topolo-gy. It provides input voltage feedforward to rapidlyadapt to instantaneous line voltage changes. Iteliminates the peak-to-average error which contrib-utes to distortion with peak CMC. It providessufficient gain and bandwidth in the discontinuousmode to adequately track the sudden reversal ofcUlTent required at the cusp of the rectified voltagewaveform.

Figure 5 shows the SEPIC preregulator withaverage CMC control loop. Optimization of theCUlTent control loop is covered in a separate Semi-nar topic[5], which includes the derivation of a

inadequate -this relates to its EquivalentSeries Resistance.

3. 120Hz ripple voltage becomes large.These concerns are discussed in Ref. [3] and [4].

Capacitor size and cost: Electrolytic capacitorsare "fonned" by the manufacturer to various dielec-tric thicknesses. Thus several different voltageratings and capacitance values are available in asingle case size. The voltage rating is proportionalto the dielectric thickness, but the capacitance valueis inversely proportional. Therefore, for a givencase size, C.V tends to be a constant value. Acapacitor rated for 200V operation will have twicethe capacitance as its 400V counterpart in the samecase size.

However, at 200 Volts, 4 times the capacitancevalue is required as at 4OOV to achieve the sameenergy storage (1/2CV1 holdup capability , the sameloop dynamics vs. harmonic distortion tradeoff, andthe same percent 120Hz ripple. Thus, twice thephysical volume (and cost) is required at 200V. Fora given application, capacitor size and cost tends tovary inversely with voltage. Storing bulk energy at48V vs. 385V can require 8 times the capacitorsize, weight, and cost.

Current Control Loop DesignThe control characteristic of the SEPIC converter

is complex. Fortunately, in a high power factorpreregulator application, the current loop controlcharacteristic is simplified because: (a) Input cur-rent, rather than output current, is controlled, (b ) Vois essentially constant because of the large outputbulk capacitor which buffers the current controlloop against rapid load changes, and ( c ) the outervoltage control loop requires very low bandwidth tominimize line current distortion and thus does notcontribute to current loop instability.

Conventional (peak) current mode control de-pends upon a current wavefonn with a linearlyincreasing ramp. However in this SEPIC converter,ripple current is steered away from the input,leaving only the small amplitude quasi-sinusoidalwavefonn shown in Fig. 4. This wavefonn is totallyunsuited for peak CMC of input current.

Average current mode control, using a currenterror amplifier as embodied in the UC3854A, could

6-5High Power Factor SEPIC Preregulator

small-signal model of the coupled-inductor SEPICconverter.

Figure 6 demonstrates the ability of the SEPICpower circuit with average CMC to track a changein input current demand from lA to SOrnA, and itsstability. The max. rate of input current change isdetermined by LL and Cc, and is much faster thanthe most severe requirement of the actual applica-tion. Note that portions of the IL2 waveform gonegative, yet operation is not discontinuous becausetotal inductor current IL1+1L2 is not negative.

200

1~

D-~ 100c

~

~ 5OOM

characteristic is associated with the input cwrent.However because of the unique identity betweenaverage switch cwrent and input cwrent. the dis-continuous switch cwrent can be used as a substi-tute, eliminating both problems.

A current sense res~tor is certainly the easiestcurrent sense method at the low end of the powerrange, where the sense resistor power loss is not tooserious. At least 1 Volt sense voltage at full ratedinput cwrent is required to achieve cwrent loopoptimization with low-bandwidth amplifiers such asin the UC3854. A smaller sense voltage reduces thesense resistor loss, but requires a higher amplifierbandwidth such as in the UC3854A. The switchcurrent should be sensed. This enables the sense re-sistor to be located in series with the MOSFETsource terminal which maintains the IC cwrentamplifier input at positive potential, eliminatingproblems with substrate diode conduction.

A current sense transfonner (C1) cannot beused to sense input cwrent directly because thewaveform is continuous, giving no opportunity toreset the core. Fortunately, it is better to senseswitch current for reasons discussed earlier, thusfacilitating the use of a CT. The cwrent transformercan provide a relatively high sense voltage to thecurrent amplifier, reducing its required bandwidth.The CT reduces the power loss involved in directcurrent sensing, and eliminates the cost and difficul-ty of using a low resistance value, high wattageprecision resistor.

Locating the CT primary in series with theMOSFET drain may reduce current spikes throughthe CT when the switch turns on.

Voltage Control Loop DesignOnce the current loop has been optimized and

properly closed, the specific power circuit topologyis "buried" within the cwrent loop. External to theclosed current loop, the voltage control loop func-tions in exactly the same way, with the same designconsiderations whether the power circuit topologyis boost, flyback, or SEPIC. The voltage loopestablishes the desired amount of input current. butthe current loop controls the specific power circuittopology to make it happen. Any HPF controlcircuit with a current amplifier can be used for

",,&1 ",&1 ,,;,., .17&1 .22&!TIME;.' s..,.

Fig 6. -Change in Current Demand

Input Current SensingWith most high power factor preregulator tech-

niques, input current must be sensed in order tomake it conform to the desired waveshape. It ismore difficult to sense input current in the SEPICconverter than in most other topologies, becauseinput current is continuous, ruling out current sensetransformers, and because the resonant LL-CC

6-6 UNITRODE CORPORATION

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ILO

--II--,~

T IN~

~M MULT.

KmAC

IDT -I i SQUARE-=- I VFF'l:L

Fig 7. -HPF Preregulator Voltage Loop and Current Programming,

any Topology, using the UC3854A

average CMC of the SEPIC preregulator. As shownin Figure 7, the UC3854A can be used, followingthe same procedure described in Reference [4] fora boost preregulator. (Reprinted in the back of thisSeminar manual.)

Overcurrent LimitingIn normal operation, the outer voltage control

loop programs an input current consistent with thepower demand of the load, and sets an averageinput current limit consistent with the maximumpower rating of the supply. However, when theoutput voltage is well below normal, either duringthe startup process or during severe overload, if thecontrol circuit tries to maintain full rated power, anunacceptably high current level results.

For example, a 200 Watt preregulator mustprovide 400W at the line peak. Assume 100%efficiency, PIN = POUT. At Vo = 200V and VIN =113V (peak input at 80V low line), fIN = 3.55A and/L2 = /O(a\'g) = 2A. Peak current through switch Sland rectifier Dl is 2A + 3.55A = 5.55A. But if Vo

is pulled down to IOV by a severe overload, 400Wat the input is still 3.55A, but the same 400Wdelivered to the output is now 40A! Peak currentthrough SI and Dl is now an intolerable 43.55A.This same total current through the coupled induc-tor requires it to be grossly overdesigned to preventsaturation.

The solution to this problem, effective for start-up or short-circuit conditions, is to incorporate inthe control circuit an absolute limit on the peak

switch current. This causes inputcurrent and power to be reduced inline with the reduced output power.

AD I In other words, the peak switchcurrent limit translates into foldbackinput current limiting.

Peak switch current, peak rectifi-er current and total inductor currentare the same: 11N + 10. So absolutecurrent limiting is achieved bysensing the current through SI andshutting the switch off wheneverthe absolute limit is reached.

Switch current sensing alreadyexists for use with the average cur-

rent mode control loop. This same sense voltagecan be used for peak current limiting. The UC3854HPF control IC has a peak current limit input. butit requires a negative-going signal, opposite to thepolarity used for average CMC in this application.Both polarities can be easily obtained from onesense transformer by seriesing two resistors acrossthe CT secondary , and ground referencing thejunction of the two resistors.

8!»

600a

8.~ .00

200

5O(XJ 1500 250U 350U 45BTIME ;n Sece

Fig 8. -Overload [1)-llN, [2)-IL2, [3)-Isw

Fig. 8 shows the SEPIC converter operating inequilibrium with VIN at 113V and Vo pulled downto only IOV. The normal control circuit would callfor 400W, but the peak switch current limit takesover control. When Sl turns on, its current is thesum of fIN plus 1l2. It does not take long for thecurrent to ramp up to the 6.25A limit. When Slturns off, the 6.25A transfers to the output throughDl (not shown) for the remainder of the switchingperiod. Note that 1l2 = IO(avg) = 5.65A, delivering

62.2W to the IOV output plus I V diode drop. fIN is

High Power Factor SEPIC Preregulator 6-7

only O.6A, taking 67.8W from the l13V line. The5.6W power difference is due to loss in the damp-ing network (which is worst case under this condi-tion). Without the absolute switch current limit, the400W power limit would force [12 to 40A at lOVout, or even greater current with lower Vo.

Setting the current limit: The limit must be sethigh enough to provide full power at low line innormal operation with V o=200V .For a 200Wapplication, assume 80Vrms minimum, requiring2.5Arms. Peak power is twice the average power atpeak voltage and current -400W at VIN=113V and1JN=3.55Apk. From Eq. 6:

VIN+VO 113+200l,.r+l" = l,.ro : 3.55 = 5.55A-v;;- 200

Allowing for superimposed HF ripple cun-ent, apeak switch current limit of 7 A would be appropri-ate. The inductor must be designed not to saturateat this current limit.

Start-upInrush surge: In normal operation, the voltage

across coupling capacitor Cc is always equal to theinstantaneous rectified line voltage. But at initialstartup, Cc and the bulk output capacitor are bothdischarged. When the power supply is turned on, aninrush current surge charges Cc and CD rapidlythrough the series inductor windings. This inrushsurge is actually of little consequence because thiscapacitance is small (3pF in the 200W preregulator)and charges rapidly. The much larger bulk capacitor(800pF) is then charged slowly to Vo, under currentlimit control. This behavior of the SEPIC convertercontrasts sharply with a boost converter, whoseinrush surge charge is orders of magnitude greaterbecause it charges the huge bulk capacitor directly.

Referring to Fig. 3 it can be seen that the inrushcurrent flows into the dotted end of Ll but out ofthe dotted end of L2. Thus the ampere-turns ofthese coupled windings cancel. The core will notsaturate no matter how large the inrush current is.Only the leakage inductance LL (in addition to theline impedance) limits the inrush surge. Since theleakage inductance flux is located in the non-mag-netic region in and between windings Ll and L2,there is no danger of saturating LL.

There is one serious problem: Cc resonantlycharges through LL to a voltage much higher thanthe instantaneous line voltage when the supply isturned on. Without damping, if the instantaneousline happens to be at the peak 220V high linecondition (365V) when the supply is turned on, Ccwould charge to nearly 730V, considerably morethan 365 plus 200 = 565V worst case under normal

operation. The damping network helps considerably,but because it is underdamped, the overshoot maystill be excessive, increasing the voltage ratingrequirements of MOSFET SI and rectifier Dl.

If the damping does not limit the overshootsufficiently, Vcc can be limited with a 400V Zenerdiode -a little greater voltage than the maximumpeak VIN of 365V, so the Zener will not interferewith normal operation. In most cases, the Zenerdiode should not be needed.

Figure 9a shows the inrush surge current withVIN at 300V when the supply is turned on, and Fig.9b shows the voltage across switch SI as Vcc reso-nantly charges, clamping at 400V.

The inrush surge amplitude and pulse width canbe estimated from the resonant frequency andresonant impedance of the inrush circuit (neglectingline and input rectifier impedance):

~21t{i":c-:; , ZR = ~.Ceff

With the circuit conditions of Fig. 9, LL = 0.2mH,Cc = 0.5pF, CD = 2.5pF and RD = 10.0.. The

effective capacitance at resonance is 2pF, resultingin fR = 8kHz and ZR = 10.0.. The peak undamped

inrush current would be 300V/10.Q=30A, butdamping reduces this to 25A peak. The ha1f-cycleresonant pulse width is 6Opsec, lengthened some-what by the action of the 400V clamp. Comparedto the startup surge to charge 800pF directly, thissurge is insignificant.

Fig. 9a shows that the inrush surge ends at85psec. During the surge, the switch turns onperiodically, which applies Vcc momentarily acrossL2. Thus when IIN reaches zero at the end of thesurge, IL2 is already at 3A in the positive direction.

Following the inrush surge: From 85 to 190psec, each time the switch turns on, Cc gives up a

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200

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Fig. 9a -Startup [l]-l1N, [2]-ILI

quently tracks VIN along the rectified line wave-fonn). Now, for the fIrst time since the end of thesurge, the input rectifiers can conduct and IIN startsto rise. The rate of rise is not detennined by wind-ing Ll, but by leakage inductance LL. Since Ll andL2 are coupled, whatever current is demanded byLL is easily diverted away from winding L2 intowinding Ll. As fIN starts to rise, IL2 falls in acomplementary manner. The total current flN+IL2through the switch remains at the current limit.

During this last phase of the start-up process,when Vcc = VIN, current limited operation is identi-

cal to the situation described earlier with severeoverload. The output will rise slowly as the bulkcapacitor charges at the current limited level. WhenVo rises to the point where Vo times the currentlimited charging current equals the power limit fornonnal operation, the current backs away from thecurrent limit and nonnal power-limited operationtakes over.

Note that the foldback limiting characteristic ofthe peak switch current limit requires that constantpower loads (such as downstream switching powerconverters) be disabled when Vo is low, usingundervoltage lockout. Otherwise, the reduced powerinput will not be able to pull up the preregulatoroutput during start-up or after an overload hascleared. With resistive loads, this is not a problem,because load power is automatically reduced.

When Vo is at or very close to zero, the verysmall duty cycle required to maintain the current atthe limit may require an ON time less than thesystem can provide, for various reasons includingZVT circuitry. To prevent loss of control, if thecurrent is already over the current limit when theclock pulse occurs, the current limiting circuitshould inhibit the ON pulse completely, skippingpulses until the current falls below the limit

ZVT CircuitryZero Voltage Transition capability is an impor-

tant addition to any high power factor preregulator .High voltage circuits store significant energy incircuit parasitic capacitances. High voltage rectifierrecovery characteristics are far from ideal, especial-ly at higher power levels. With "hard" switching,these characteristics translate into high losses,

Fig. 9b -Startup V SWITCH

little of its energy into L2, causing Vcc (seen acrossthe switch) to slowly fall towards VIN (300V), andI12 to slowly rise. Most of the time, the switch isoff, and IL2 is delivered through Dl to outputcapacitor Co. IIN remains at zero as long as Vcc isgreater than VIN, because when the switch turns on,Vcc is applied to L2, inducing Vcc > VIN across Llas well. Since VIN is still at 300V, the input rectifi-ers (not shown in Fig. 3) block all current flow.

At 19Opsec, I12 reaches 6.5A and the switchcurrent limit becomes effective. When the switchturns on, Vcc applied to Ll causes ILl to riserapidly until the 6.5A switch current limit isreached. When the switch turns off, ILl slowly dis-charges into Co (Vco is almost zero). The dutycycle thus is exb'emely short at the current limit.

With Co = 800pF, the output voltage rises at a

rate less than lV/lOOlJsec!! So during the entiretime shown in Fig. 8, the output is essentiallyshorted, and energy is being transferred from Cc(and CD) to Co, and fIN = 0.

At approximately lOOOpsec, Vcc has decreased toequal VIN, which is still near 300V. (Vcc subse-

High Power Factor SEPIC Preregulator 6-9

severe component stress, and radiated EMI. ZVTcircuitry facilitates nearly lossless transitions andreduces noise.Zero Voltage Transitions occur naturally wheneverthe power switch Sl turns off. Current IIN+IL2 trans-fers from the switch to the capacitance of theswitch, rectifier, and circuit parasitics (lumpedtogether as CSI in Fig. lOa) while the capacitanceholds the voltage near zero. Then the capacitancecharges as the voltage rises until clamped by theoutput rectifier conduction. Thus, turn-off loss isquite small without any special design effort.

Fig lOa -Non-zvr SEPIC Circuit

Current ramps up dJrough LR at rate (VIN+Vo)/LRuntil the cwrent (llN+IL2) through rectifier Dl istransfe1Ted to LR. When Dl recovery is complete, itdisconnects and the energy stored in CSI transfersresonantly into LR. After one quarter cycle at theresonant frequency the voltage across Sl is clampedat zero by its body diode. Sl can now be turned on-with zero switching loss. Sl should be turned onand Sl a turned off simultaneously, or as quickly aspossible to transfer the current away from the muchsmaller Sl a with its higher static losses. (As long asSl a remains on, LR will prevent the current transferto Sl.)

Although Sl now has lossless ZVT transitions,Sla clearly has turn-on losses. However, the bigturn-on losses of the non-ZVT circuit due to thecurrent transfer from D 1 and the energy stored inCSl now end up mostly as energy stored in LR. Theonly loss in Sl a is from the energy stored in itsown relatively small capacitance.

The next problem is how to recover the energythat has been stored in LR. This is accomplishedwith a second tightly coupled winding on LR, asshown in Fig. lOc. The two windings have thesame number of turns, bifilar wound. When Slaturns off, current transfers to the second windingand passes dJrough the diode to any convenientvoltage sink --Vcc or Vo, where the energy storedin LR is recovered.

Turn-on is a different matter. SI is clamped athigh voltage (VIN+VO) while the current makes itstransition, causing power loss in the switch. Thisloss is worsened by the high voltage rectifier'sreverse recovery current, especially if the switchtum-on is fast to minimize the transition time. Nomatter how fast SI turns on, the very significantenergy stored in CSI is translated into switch loss.

The fIrst step in achieving turn-on ZVT is toconnect a small inductor LR in series with anauxiliary switch SI a across main power switch SIas shown in Fig. 1 Ob. [6] SIa is a much smaller

device than main power switch SI, with muchlower Coss. When the control IC calls for switchtum-on, SI a is turned on fIrst. SI turn-on is de-

layed.Fig 10c -Energy Recovery

The ON time of the ZVT switch Si a becomesthe minimum ON time of the SEPIC converter. Innormal operation, this is not a problem. As shownby Eq. 5, the minimum duty cycle occurs at maxVIN and never approaches zero with normal valuesof Vo. But D does approach zero when Vo is zeroduring start-up or short-circuit load conditions. Thecontrol circuit must then skip pulses to reduce theFig. lOb -ZVT Inductor and Aux. Switch

6-10 UNITRODE CORPORATION

Line IsolationIt is theoretically possible to incorporate line

isolation in the SEPIC converter by adding anadditional winding £3, as shown in Fig. 11.

Insulation for 3750Vrms isolation must beincorporated between windings £2 and £3 .unfortu-nately, the high voltage insulation prevents closecoupling between these windings. The resultingleakage inductance is large and its circuit location(directly in series with either £2 or £3) causesdelays, voltage spikes and difficulty energy recov-

ery problems.

duty cycle and retain conb"ol in spite of the fixedminimum ON time.

Design Considerations: Two things must bedefined: (1) the inductor LR value, and (2) the delaytime for turning on S 1 after S la has been turned on(which will be the minimum ON time of the con-

verter).

There are three sequential times involved:

1. The time for current to ramp up in LR andb"ansfer away from Dl:

tRAMP = LR(llN+lo)/(VIN+VO)

2. Dl recovery time

3. Resonant quarter cycle when energy b"ansfersfrom CSI to LR:

tREs = 1t.fLRCSI!2

A small LR value reduces tRAMP and tREs butworsens the diode recovery current and peak reso-nant current. One approach is to consider whatwould be a reasonable delay time (minimum ONtime). A ramp time of 200ns is 2% of the IOpsecswitching period. Worst case is at peak low line,full power. Applying the values developed earlierfor this specific application to the tRAMP equationabove:

Fig 11. -SEPIC Converter with Isolation

To date, there are no known practical solutionsto this problem. If a way can be found, this wouldconsiderably enhance the usefulness of the SEPIChigh power factor topology. Bear in mind that if anisolation technique is also used to step down to anisolated 48V bus, for example, there is a substantialpenalty in bulk capacitor size and cost vs. energystorage at 200V.

A suggestion for anyone who would attempt tosolve this problem: If L1 and L2 are also coupledto maintain ripple current steering as discussedearlier, it is important to use the following windingsequence, starting from the gapped core center leg:£3 , HV insulation, L2, L1. Otherwise the leakageinductances LL in the input and LIJ in the outputwill be coupled to each other, with (probably)disastrous results.

LR = 200ns(113V+200V)/(3.55A+2A)

LR = 11.27pH

For LR = 10pH, tRAMPmax is 171nsec.

Assuming a total capacitance CSl of 5OOpF, theresonant frequency is 2.4 MHz, resulting in a timetRES of l04ns for 1/4 cycle. This time is indepen-dent of V1N or load. Resonant impedance ZR =(L/C) ~ = 141.0.. At high line peak of 365V, this

results in a peak resonant current of (365+200)/141= 4A (in addition to 3A lo+l1N at high line peak).

A total SI a ON time of 300nsec, resulting in aminimum duty cycle of .03 is reasonable andadequate for this application.

Switching losses in high power factor applica-tions are especially severe because of the highvoltages being switched. ZVT techniques areunusually advantageous. The biggest implementationproblem at this date is that existing HPF controlICs do not provide the delayed driver function,forcing it to be occomplished with ou~ components.

6-11High Power Factor SEPIC Preregulator

ConclusionsThe SEPIC converter has many advantages for

high power factor preregulator applications. Steeringthe high frequency ripple current away from theinput can dramatically reduce the size and cost ofth input noise ftlter. This advantage, the very smallstart-up surge, and the inherent current-limitingcapability become more and more significant as thepower level rises.

References:

[1] Paul Steffens, Personal Communication

[2] L.H. Dixon, "Coupled Inductor Design,"Unitrode Seminar SEM900, Topic 8, 1993

[3] L.H. Dixon, "High Power Factor Preregulatorsfor Off-Line Power Supplies," Unitrode Semi-nar SEM600, 1988 (Reprinted as Topic 12 in

SEM8OO, SEM900)

[4] L.H. Dixon, "High Power Factor SwitchingPreregulator Design Optimization," UnitrodeSeminar SEM700, 1990 (Reprinted as Topic 13in SEM8OO, SEM900)

[5] L.H. Dixon, "Control Loop Design, SEPICPreregulator Example," Unitrode SeminarSEM900. Topic 7, 1993

[6] G.C.Hua, C.S.Leu, y .M.Jiang, F.C.Lee "NovelZero-Voltage Transition PWM Converters,"VPEC Power Electronics Seminar Proceed-ings, p33, 1992

6-12 u NITRODE CORPORATION

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