Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011

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Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011 Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc/

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Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011. Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc/. The npn Gummel-Poon Static Model. C. R C. I CC - I EC = IS ( exp(v BE /NFV t - exp(v BC /NRV t )/Q B. I BR. B. R BB. I LC. - PowerPoint PPT Presentation

Transcript of Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011

Page 1: Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011

Semiconductor Device Modeling and

Characterization – EE5342 Lecture 34 – Spring 2011

Professor Ronald L. [email protected]

http://www.uta.edu/ronc/

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The npn Gummel-Poon Static ModelC

E

BB’

ILC

ILE IBF

IBRICC - IEC = IS(exp(vBE/NFVt

- exp(vBC/NRVt)/QB

RC

RE

RBB

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Gummel Poon npnModel Equations

IBF = ISexpf(vBE/NFVt)/BFILE = ISEexpf(vBE/NEVt)

IBR = ISexpf(vBC/NRVt)/BRILC = ISCexpf(vBC/NCVt)

QB = (1 + vBC/VAF + vBE/VAR ){½ + ¼ + (BFIBF/IKF + BRIBR/IKR)}

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Values for ms

with metal gate

02586.0V ,12.1E ,19E8.2N10E45.1n ,05.4 ,28.4

NNlnV :Si-n to Al

nNlnVq2

EnNNlnV :Note

nNNlnV :Si-p to Al

tgC

iSiAlm,

dCtSiAlm,ms

iat

g2i

aCt

2i

aCtSiAlm,ms

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Values for ms

with silicon gate

idt

g

dCt

dCtSi

gSims

iat

g2i

aCt

2i

aCtSiSims

nNlnVq2

ENNlnV :Note

NNlnVq

E :Si-n to poly p

nNlnVq2

EnNNlnV :Note

nNNlnV :Si-p to poly n

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8Fig 10.15*

ms(V)

NB (cm-3)

Typical ms values

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Flat band with oxidecharge (approx. scale)

Ev

AlSiO2

p-Si

EFm

Ec,Ox

Eg,ox~8eV EFp

Ec

Ev

EFi

'Ox

'ss

msOxmsFB

Ox

Oxc

Ox

'ss

x

ssm

ss

CQVV

xV

dxdE

q1QE

surface gate the onis Q'Q' charge

a cond FB at thenbound, Ox/Si the at

is Q' charge a If

q(fp-ox)q(Vox)

q(m-ox)

q(VFB) VFB= VG-VB, when Si bands

are flat

Ex

+<--Vox-->-

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Flat-band parametersfor n-channel (p-subst)

0nNlnVq2

EnNNlnV

gate, Si-poly n a For

den chg Ox/Si the is 'Q ,x'C

'C'QV :substratep

iat

g2i

actms

sms

ssOxOx

Ox

OxssmsFB

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Flat-band parametersfor p-channel (n-subst)

0nNlnVq2

EnNNlnV

qE gate, Si-poly p a For

den chg Ox/Si the is 'Q ,x'C

change) (no 'C'QV :substraten

idt

g2i

dvtms

gsms

ssOxOx

Ox

OxssmsFB

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Inversion for p-SiVgate>VTh>VFB

Vgate> VFB

Vsub = 0

EOx,x> 0

inversion for threshold above

E Induced depletes 0

E Induced

0xVE

Si

SiOxOx

x,Ox

Acceptors

Depl Reg

e- e- e- e- e-

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Approximation concept“Onset of Strong Inv”• OSI = Onset of Strong Inversion occurs

when ns = Na = ppo and VG = VTh

• Assume ns = 0 for VG < VTh

• Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh

• Cd,min = Si/xd,max for VG > VTh • Assume ns > 0 for VG > VTh

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MOS Bands at OSIp-substr = n-channel

Fig 10.9*

2q|p|

qp

xd,max

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Computing the D.R. W and Q at O.S.I.

Ex

Emax

x

aSi

x NqdxdE

a

pSid qN

x

22

,max

parea 2

,max,max' dad xqNQ

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Calculation of thethreshold cond, VT

Ox the across Q' induce to addedvoltage the isV where V,VVsub)-p sub,-(n xNqQ' is

charge extra the and x of value the reached has region depletion

The inverted. is surface the whenreached is condition threshold The

d,max

FBT

d,maxBd,max

d,max

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Equations forVT calculation

substr-n for 0 substr,- p for 0VqN22x ,xNqQ'

0nNV 0N

nV

CQ2VV substrnp

da

npd,maxd,maxa,dd,max

id

tnai

tp

Ox

dnpFBT

,

,

',max

,

,ln,ln

':,

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Fully biased n-MOScapacitor

0y

L

VG

Vsub=VB

EOx,x> 0

Acceptors

Depl Reg

e- e- e- e- e- e- n+ n+

VS VD

p-substrate

Channel if VG > VT

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MOS energy bands atSi surface for n-channel

Fig 8.10**

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Computing the D.R. W and Q at O.S.I.

Ex

Emax

x

aSi

x NqdxdE

a

SBpSid qN

VVx

)(22,max

)(2 SBp VVarea

,maxda,maxd xqNQ

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Q’d,max and xd,max forbiased MOS capacitor

Fig 8.11**

xd,max

(m) )2-

d,max

(cmq

Q'

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Fully biased n-channel VT calc

0V ,qN

VV22x

,xNqQ' ,0NnlnV

VV'C'Q2VVV

VV :substratep

aCBp

d,max

d,maxad,maxaitp

FBOx,maxd

pFBCT

Tthreshold at ,G

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n-channel VT forVC = VB = 0

Fig 10.20*

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References* Semiconductor Physics & Devices,

by Donald A. Neamen, Irwin, Chicago, 1997.

**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986