Multilevelselvaraj/cpe100/lecture/chapter7.pdf · 3 levels, 6 gates and 19 inputs Henry Selvaraj...

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Henry Selvaraj UNLV

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This chapter’s objective:

• how to design multilevel networks

• techniques for designing with NAND and NOR gates


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Multilevel

The maximum number of gates cascaded in series between a network input and the

output is referred to as the number of levels of gates


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Terminology

• AND-OR network: two level network

• OR-AND network : two level network

• OR-AND-OR network : three level network

• network of AND and OR gates : multilevel network


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Network parameters

As we can design networks with different number of levels, using different gates, we need some parameters to decide on the suitable network for a given problem.

• Number of gates (some times called silicon area)

• number of levels

• number of inputs

• time taken to design the network


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Number of gates

The number of gates in the network directly influences the total silicon area and therefore, the cost. However, optimizing only the number of gates may lead to routing and placing difficulties. In other words, the circuit wiring could become too complex.


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Number of levelsThe number of levels in a circuit dictates the signal propagation time. It will take more time for the signal to propagate through more number of levels. It is better to optimize the number of levels for high frequency circuits. It may also reduce routing and placement problem.


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Number of inputsThe inputs to the gates are generally buffered using an electronic memory device called flip-flop. Therefore, we can assume that all variables and their complements are available as network inputs. This means we need not insert NOT gates to complement the input variable.

To measure the complexity of the network, inputs to all the gates in the network are counted.


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• The number of levels in an AND-ORnetwork can be increased by factoring the Sum of Product expression.

• The number of levels in an OR-ANDnetwork can be increased by multiplying out the Product of Sum expression.


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Exampley = (ab + c)(d + e + fg) + h

Requirements: 4 levels, 6 gates, 13 inputs

y


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y = (ab + c)(d + e + fg) + h

By partially multiplying out,

y = ab(d+e) +c(d+e)+abfg+cfg+h

If we draw the tree diagram we will need 3 levels, 6 gates and 19 inputs.

Continued...


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y = ab(d+e) +c(d+e)+abfg+cfg+h

d e

a b c abfg cfg h

y3 levels, 6 gates and 19 inputs


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Example of multilevel gate networksy(a,b,c,d) = m(1,5,6,10,13,14)

y = a’c’d+bc’d+bcd’+acd’a’c’d b c’d bcd’ a c d’


abcd

0 0 0 0

1 1 1 0

0 0 0 0

0 1 1 1


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If we factor the expression

y(a,b,c,d) = m(1,5,6,10,13,14),

we obtain, y = c’d(a’+b)+cd’(a+b).

This leads to a OR-AND-OR gate network.

a’b

ab

d

c’

c

d’

y

3 levels, 5 gates and 12 inputs


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Example of multilevel gate networks cont...Now, let us try to implement the Maxterm form of the expression.

y = (c+d)(a’+b+c)(c’+d’)(a+b+c’)

c d a’ b c c’ d’ a b c’


abcd

0 0 0 0

1 1 1 0

0 0 0 0

0 1 1 1


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If we partly multiply out the Maxterm expression,

y(a,b,c,d) = [c+d(a’+b)][c’+d’(a+b)]=

= (c+a’d+bd)(c’+ad’+bd’).

This leads to an AND-OR-AND gate network.(figure in the next slide)

y = (c+d)(a’+b+c)(c’+d’)(a+b+c’)


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a d’ b d’ a’ d b d

c’ c

y

3 levels, 7 gates and 16 inputs


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Other types of Logic GatesNAND gate

y = (abc)’ = a’+b’+c’

abc

abc

y y


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x1

x2

xn

f

f = (x1x2…. xn)’ = x1’+x2’+ …. +xn’

General expression for NAND


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NOR gate

y = (a+b+c)’ = a’b’c’

abc

abc

y y


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x1

x2

xn

f

f = (x1+x2+….+ xn)’ = x1’x2’ …. xn’

General expression for NOR gate


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NAND and NOR functions are duals

If a given circuit realizes the NAND function for positive logic, it realizes the NOR function for negative logic


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A set of logic operations is said to be functionally complete if any Boolean function can be expressed in terms of

this set of operations.


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AND & NOT are functionally complete set of gates

Realization of OR function using AND and NOT gates.

(x’y’ = x + y)

xy x + y


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NAND gate is functionally complete

Realization of NOT function using NAND gate.

aa’

a+b

a

b

Realization of OR function using NAND gate.


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HWChapter 6:

6.9 a, b.

Chapter 7: 7.15; 7.17, 7.19; 7.29 (5th edition) or 7.35 (6th edition)

DUE: Friday


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A set of logic operations is said to be functionally complete if any Boolean function can be expressed in terms of

this set of operations.


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AND & NOT are functionally complete set of gates

Realization of AND function using AND and NOT gates.

(x’y’ = x + y)

xy x + y


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NAND gate is functionally complete

Realization of NOT function using NAND gate.

aa’

a+b

a

b

Realization of OR function using NAND gate.


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Designing two-level NAND and NOR gate networks

We use the fact:

f = (f’)’


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Conversion to other two-level forms:

f = a + bc’ + b’cd AND-OR network

f = [a’(bc’)’(b’cd)’]’ NAND-NAND network

f = [a’(b’+c)(b+c’+d’)’]’ OR-NAND network

f = a+(b’ +c)’+ (b+c’+d’)’ NAND-OR network


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Example:

f = a + bc’ + b’cd

AND-OR implementation:

bc’

b’cd

a f


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f = a + bc’ + b’cd = [(a + bc’ + b’cd)’]’=

[a’(bc’)’(b’cd)’]’

bc’a’

b’cd’

f


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[a’(bc’)’(b’cd)’]’ = [a’(b’+c)(b+c’+d’)]’

This expression is used to design a OR-NAND network

[a’(b’+c)(b+c’+d’)]’ = a+(b’ +c)’+ (b+c’+d’)’

This expression is used to design a NAND-OR network


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Possible network combinations:

NAND-NAND

OR-NAND

NOR-OR

NOR-NOR

AND-NOR

NAND-AND


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Procedure to design a NAND-NAND network

• Find a minimum sum-of-products expression for F.

• draw the corresponding two-level AND-OR network

• replace all gates with NAND gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literal.


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bc’

b’cd

a f

bc’a’

b’cd

f

An example

..after transforming


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Procedure to design a NOR-NOR network

• Find a minimum product-of-sums expression for F.

• draw the corresponding two-level OR-AND network

• replace all gates with NOR gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literal.


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abc

ab’c’

ac’d

f

abc

ab’c’

ac’d

f


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D

E’

C

F’

G’

B’

HI’J

A’

KF

Level 5 level 4 level 3 level 2 level 1

Multi-level NAND Gate networks

Example: f = A’[B’+C(D+E’)+F’G’]+HI’J+K


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• Simplify the function

• Design a multilevel AND-OR network

• The output gate must be an OR gate.

• Replace all gates with NAND gates

• Invert any literal that appears as inputs to odd number of levels.


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Multi-level NAND Gate networksD’

E

C

F’

G’

B

HI’J

A’

K’F

Level 5 level 4 level 3 level 2 level 1


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Alternate gate symbols

AND OR NAND NOR

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