FREESCALE SEMICONDUCTOR

SCM-i.MX 6D Data Sheet

Phillippe, John

6/11/2015

Rev. 0.2

Overview of the SCM module which contains the i.MX6Dual processor, 2Gb LPDDR2 memory, 16MByte flash and an integrated PMIC.

Overview

1. Introduction

1.1. Ordering Information

1.2. Features

1.3. References

2. Architectural Overview

2.1. Block Diagram

3. Modules List

4. Electrical Characteristics

4.1. Chip-Level Conditions

4.1.1. Absolute Max Ratings

4.1.2. Thermal Resistance

4.1.3. Operating Range

4.2. Power Supplies Requirements and Restrictions

4.2.1. Power-Up Sequence

4.2.2. Power-Down Sequence

4.2.3. Power Supplies Usage

4.2.4. OTP Boot Config

5. Boot Mode Configuration

5.1. Boot Mode Configuration Pins

5.2. Boot Devices Interfaces Allocation

6. Special Signal Considerations

6.1. Power Supplies

7. Package Information

8. Revision History

1. Introduction

1.1. Ordering Information

1.2. Features

The SCM-i.MX6D solution speeds and eases development time by addressing technology challenges

such as design of DDR, power, and uboot SW. This single chip system module consists of the i.MX 6Dual

applications processor, PF0100 (PMIC) for power management, 2 Gb of Micron’s LPDDR2, 16 MB of

Micron’s SPI NOR, and 109 discrete components. In addition, a fully tested board support package (BSP)

enabled in both Android™ and Linux® will be available.

The i.MX family encompasses a quad-core platform running up to 1 GHz with 1 MB of L2 cache, and 2-

channel, 32-bit LPDDR2 support. Integrated FlexCAN and MLB busses, PCI Express® and SATA-2 provide

excellent connectivity while integration of dual, MIPI display port, MIPI camera port and HDMI v1.4

makes it an ideal platform for consumer, automotive and industrial multimedia applications.

1.3. References

This document is intended to be a companion to the data sheets of the following integrated parts:

a) i.MX 6D

b) MMPF0100

c) Micron SPI Nor (N25Q128A13)

d) Micron LPDDR2

For more detailed information of each parts operation please reference those data sheets.

2. Architectural Overview

2.1. Block Diagram

3. Modules List

Block Name Description/Notes

i.MX6D i.MX6dual processor. Fully functional as a normal i.MX 6dual except the MLB bus is disabled and not pinned out.

MMPF0100 Power management IC requires only a single 4.2V supply and can provide power and voltage references to entire SCM.

SPI NOR 16 megabytes of SPI NOR which contains the uBoot SW and OS.

LPDDR2 LPDDR2 module

3.1. Special Signal Considerations

<TBD>

3.2. Recommended Connections for Unused Analog Interfaces

<TBD>

4. Electrical Characteristics

4.1. Chip-Level Conditions

4.1.1. Absolute Max Ratings

Parameter Description Symbol Min Max Unit

PMIC System Supply Voltage Range SYS_4V2 -0.3 4.8 V

Temperature range (storage) T_storage -40 150 C

4.1.2. Thermal Resistance - TBD

4.1.3. Operating Range

Parameter Description Symbol Min Max Unit

PMIC System Supply Voltage Range SYS_4V2 3.6 4.2 V

Junction Temperature standard commercial Tj 0 95 C

4.2. Power Supplies Requirements and Restrictions

4.2.1. Power-Up Sequence

If only providing a single system supply (SYS_4V2) than no special power sequencing

required. The supply slew rate limit needs to be observed.

4.2.2. Power-Down Sequence

<TBD>

4.2.3. Power Supplies Usage

<TBD>

4.2.4. OTP Boot Config

<TBD>

5. Boot Mode Configuration

5.1. Boot Mode Configuration Pins

5.2. Boot Devices Interfaces Allocation

6. Special Signal Considerations

6.1. Power Supplies

6.1.1. Block Diagram of on/off chip supply connections

Notes:

1. Red lines indicate power nets required by SCM.

2. The voltages in parenthesis of the MMPF0100 are the default voltages assigned during

power up. All regulators can be reconfigured by software.

6.2. Recommended Connections for Unused Analog Interfaces

<TBD>

6.2.1. Fuses

7. Package Information

7.1. Signal List

The table below shows the differences between the ballmap of the i.MX6 Dual and the SCM-

i.MX6D.

i.MX6Dual

SCM-i.MX6D

Bottom Ball Ball Name

PoP Bottom Ball Ball Name remarks

C12 BOOT_MODE0 U11 BOOT_MODE0

F12 BOOT_MODE1 V12 BOOT_MODE1

C7 CLK1_N U18 CLK1_N

D7 CLK1_P U17 CLK1_P

C5 CLK2_N W19 CLK2_N

D5 CLK2_P W20 CLK2_P

F4 CSI_CLK0M N20 CSI_CLK0M

F3 CSI_CLK0P N19 CSI_CLK0P

E4 CSI_D0M R20 CSI_D0M

E3 CSI_D0P R19 CSI_D0P

D1 CSI_D1M P19 CSI_D1M

D2 CSI_D1P P20 CSI_D1P

E1 CSI_D2M M19 CSI_D2M

E2 CSI_D2P M20 CSI_D2P

F2 CSI_D3M L20 CSI_D3M

F1 CSI_D3P L19 CSI_D3P

D4 CSI_REXT grounded in package

M1 CSI0_DAT10 H17 CSI0_DAT10

M3 CSI0_DAT11 H18 CSI0_DAT11

M2 CSI0_DAT12 J17 CSI0_DAT12

L1 CSI0_DAT13 J18 CSI0_DAT13

M4 CSI0_DAT14 K17 CSI0_DAT14

M5 CSI0_DAT15 K16 CSI0_DAT15

L4 CSI0_DAT16 N16 CSI0_DAT16

L3 CSI0_DAT17 M18 CSI0_DAT17

M6 CSI0_DAT18 L17 CSI0_DAT18

L6 CSI0_DAT19 M17 CSI0_DAT19

N1 CSI0_DAT4 E17 CSI0_DAT4

P2 CSI0_DAT5 E18 CSI0_DAT5

N4 CSI0_DAT6 F17 CSI0_DAT6

N3 CSI0_DAT7 F18 CSI0_DAT7

N6 CSI0_DAT8 G17 CSI0_DAT8

N5 CSI0_DAT9 G18 CSI0_DAT9

P3 CSI0_DATA_EN D18 CSI0_DATA_EN

P4 CSI0_MCLK C18 CSI0_MCLK

P1 CSI0_PIXCLK C17 CSI0_PIXCLK

N2 CSI0_VSYNC D17 CSI0_VSYNC

E5 DDR_1V2 DDR Supply – 1.2V

E9 DDR_1V2 DDR Supply – 1.2V

V15 DDR_1V2 DDR Supply – 1.2V

W8 DDR_1V2 DDR Supply – 1.2V

E14 DDR_1V2_SW3FB

SUPPLIES SW3FB AND THE VINREFDDR ON THE PMIC.

V5 DDR_1V8 DDR Supply – 1.8V

N19 DI0_DISP_CLK A4 DI0_DISP_CLK

N21 DI0_PIN15 A2 DI0_PIN15

N25 DI0_PIN2 B4 DI0_PIN2

N20 DI0_PIN3 B3 DI0_PIN3

P25 DI0_PIN4 A3 DI0_PIN4

P24 DISP0_DAT0 D5 DISP0_DAT0

P22 DISP0_DAT1 C5 DISP0_DAT1

R21 DISP0_DAT10 B7 DISP0_DAT10

T23 DISP0_DAT11 A7 DISP0_DAT11

T24 DISP0_DAT12 D8 DISP0_DAT12

R20 DISP0_DAT13 C8 DISP0_DAT13

U25 DISP0_DAT14 B8 DISP0_DAT14

T22 DISP0_DAT15 A8 DISP0_DAT15

T21 DISP0_DAT16 D9 DISP0_DAT16

U24 DISP0_DAT17 C9 DISP0_DAT17

V25 DISP0_DAT18 B9 DISP0_DAT18

U23 DISP0_DAT19 A9 DISP0_DAT19

P23 DISP0_DAT2 B5 DISP0_DAT2

U22 DISP0_DAT20 D10 DISP0_DAT20

T20 DISP0_DAT21 C10 DISP0_DAT21

V24 DISP0_DAT22 B10 DISP0_DAT22

W24 DISP0_DAT23 A10 DISP0_DAT23

P21 DISP0_DAT3 A5 DISP0_DAT3

P20 DISP0_DAT4 D6 DISP0_DAT4

R25 DISP0_DAT5 C6 DISP0_DAT5

R23 DISP0_DAT6 B6 DISP0_DAT6

R24 DISP0_DAT7 A6 DISP0_DAT7

R22 DISP0_DAT8 D7 DISP0_DAT8

T25 DISP0_DAT9 C7 DISP0_DAT9

AC14 DRAM_A0

AB14 DRAM_A1

AA15 DRAM_A10

AC12 DRAM_A11

AD12 DRAM_A12

AC17 DRAM_A13

AA12 DRAM_A14

Y12 DRAM_A15

AA14 DRAM_A2

Y14 DRAM_A3

W14 DRAM_A4

AE13 DRAM_A5

AC13 DRAM_A6

Y13 DRAM_A7

AB13 DRAM_A8

AE12 DRAM_A9

AE16 DRAM_CAS

Y16 DRAM_CS0

AD17 DRAM_CS1

AD2 DRAM_D0

AE2 DRAM_D1

AA6 DRAM_D10

AE7 DRAM_D11

AB5 DRAM_D12

AC5 DRAM_D13

AB6 DRAM_D14

AC7 DRAM_D15

AB7 DRAM_D16

AA8 DRAM_D17

AB9 DRAM_D18

Y9 DRAM_D19

AC4 DRAM_D2

Y7 DRAM_D20

Y8 DRAM_D21

AC8 DRAM_D22

AA9 DRAM_D23

AE9 DRAM_D24

Y10 DRAM_D25

AE11 DRAM_D26

AB11 DRAM_D27

AC9 DRAM_D28

AD9 DRAM_D29

AA5 DRAM_D3

AD11 DRAM_D30

AC11 DRAM_D31

AA17 DRAM_D32

AA18 DRAM_D33

AC18 DRAM_D34

AE19 DRAM_D35

Y17 DRAM_D36

Y18 DRAM_D37

AB19 DRAM_D38

AC19 DRAM_D39

AC1 DRAM_D4

Y19 DRAM_D40

AB20 DRAM_D41

AB21 DRAM_D42

AD21 DRAM_D43

Y20 DRAM_D44

AA20 DRAM_D45

AE21 DRAM_D46

AC21 DRAM_D47

AC22 DRAM_D48

AE22 DRAM_D49

AD1 DRAM_D5

AE24 DRAM_D50

AC24 DRAM_D51

AB22 DRAM_D52

AC23 DRAM_D53

AD25 DRAM_D54

AC25 DRAM_D55

AB25 DRAM_D56

AA21 DRAM_D57

Y25 DRAM_D58

Y22 DRAM_D59

AB4 DRAM_D6

AB23 DRAM_D60

AA23 DRAM_D61

Y23 DRAM_D62

W25 DRAM_D63

AE4 DRAM_D7

AD5 DRAM_D8

AE5 DRAM_D9

AC3 DRAM_DQM0

AC6 DRAM_DQM1

AB8 DRAM_DQM2

AE10 DRAM_DQM3

AB18 DRAM_DQM4

AC20 DRAM_DQM5

AD24 DRAM_DQM6

Y21 DRAM_DQM7

AB15 DRAM_RAS

Y6 DRAM_RESET not connected

AC15 DRAM_SDBA0

Y15 DRAM_SDBA1

AB12 DRAM_SDBA2

Y11 DRAM_SDCKE0

AA11 DRAM_SDCKE1

AD15 DRAM_SDCLK_0

AE15 DRAM_SDCLK_0_B

AD14 DRAM_SDCLK_1

AE14 DRAM_SDCLK_1_B

AC16 DRAM_SDODT0

AB17 DRAM_SDODT1

AE3 DRAM_SDQS0

AD3 DRAM_SDQS0_B

AD6 DRAM_SDQS1

AE6 DRAM_SDQS1_B

AD8 DRAM_SDQS2

AE8 DRAM_SDQS2_B

AC10 DRAM_SDQS3

AB10 DRAM_SDQS3_B

AD18 DRAM_SDQS4

AE18 DRAM_SDQS4_B

AD20 DRAM_SDQS5

AE20 DRAM_SDQS5_B

AD23 DRAM_SDQS6

AE23 DRAM_SDQS6_B

AA25 DRAM_SDQS7

AA24 DRAM_SDQS7_B

AB16 DRAM_SDWE

AC2 DRAM_VREF

H3 DSI_CLK0M P18 DSI_CLK0M

H4 DSI_CLK0P P17 DSI_CLK0P

G2 DSI_D0M R17 DSI_D0M

G1 DSI_D0P R18 DSI_D0P

H2 DSI_D1M N17 DSI_D1M

H1 DSI_D1P N18 DSI_D1P

G4 DSI_REXT grounded in package

H25 EIM_A16 H1 EIM_A16

G24 EIM_A17 H4 EIM_A17

J22 EIM_A18 J2 EIM_A18

G25 EIM_A19 J3 EIM_A19

H22 EIM_A20 J4 EIM_A20

H23 EIM_A21 K1 EIM_A21

F24 EIM_A22 K2 EIM_A22

J21 EIM_A23 K3 EIM_A23

F25 EIM_A24 K4 EIM_A24

H19 EIM_A25 R5 EIM_A25

N22 EIM_BCLK B1 EIM_BCLK

H24 EIM_CS0 H3 EIM_CS0

J23 EIM_CS1 H2 EIM_CS1

C25 EIM_D16 V3 EIM_D16_NOR Also connected to internal SPI NOR.

F21 EIM_D17 U4 EIM_D17_NOR Also connected to internal SPI NOR.

D24 EIM_D18 U3 EIM_D18_NOR Also connected to internal SPI NOR.

G21 EIM_D19 T4 EIM_D19

G20 EIM_D20 T3 EIM_D20

H20 EIM_D21 R4 EIM_D21

E23 EIM_D22 P3 EIM_D22

D25 EIM_D23 P4 EIM_D23

F22 EIM_D24 T5 EIM_D24

G22 EIM_D25 N3 EIM_D25

E24 EIM_D26 M4 EIM_D26

E25 EIM_D27 M3 EIM_D27

G23 EIM_D28 L4 EIM_D28

J19 EIM_D29 L3 EIM_D29

J20 EIM_D30 L2 EIM_D30

H21 EIM_D31 L1 EIM_D31

L20 EIM_DA0 E1 EIM_DA0

J25 EIM_DA1 F4 EIM_DA1

M22 EIM_DA10 D2 EIM_DA10

M20 EIM_DA11 D4 EIM_DA11

M24 EIM_DA12 C4 EIM_DA12

M23 EIM_DA13 B2 EIM_DA13

N23 EIM_DA14 C2 EIM_DA14

N24 EIM_DA15 C3 EIM_DA15

L21 EIM_DA2 F2 EIM_DA2

K24 EIM_DA3 F3 EIM_DA3

L22 EIM_DA4 E2 EIM_DA4

L23 EIM_DA5 D1 EIM_DA5

K25 EIM_DA6 E4 EIM_DA6

L25 EIM_DA7 E3 EIM_DA7

L24 EIM_DA8 C1 EIM_DA8

M21 EIM_DA9 D3 EIM_DA9

K21 EIM_EB0 G3 EIM_EB0

K23 EIM_EB1 G2 EIM_EB1

E22 EIM_EB2 V4 EIM_EB2_NOR Also connected to internal SPI NOR.

F23 EIM_EB3 N4 EIM_EB3

K22 EIM_LBA F1 EIM_LBA

J24 EIM_OE G1 EIM_OE

K20 EIM_RW G4 EIM_RW

M25 EIM_WAIT F5 EIM_WAIT

U21 ENET_CRS_DV D11 ENET_CRS_DV

V20 ENET_MDC D12 ENET_MDC

V23 ENET_MDIO C12 ENET_MDIO

V22 ENET_REF_CLK C13 ENET_REF_CLK

W23 ENET_RX_ER C11 ENET_RX_ER

W21 ENET_RXD0 A11 ENET_RXD0

W22 ENET_RXD1 B11 ENET_RXD1

V21 ENET_TX_EN D13 ENET_TX_EN

U20 ENET_TXD0 A12 ENET_TXD0

W20 ENET_TXD1 B12 ENET_TXD1

A5 FA_ANA Grounded in package

GND <See footnote 1>

C8 GPANAIO U12 GPANAIO

T5 GPIO_0 E16 GPIO_0

T4 GPIO_1 E15 GPIO_1

R2 GPIO_16 M15 GPIO_16

R1 GPIO_17 R16 GPIO_17

P6 GPIO_18 AD12 GPIO_18_PMIC_INTB

P5 GPIO_19 P16 GPIO_19

T1 GPIO_2 D16 GPIO_2

R7 GPIO_3 A19 GPIO_3

R6 GPIO_4 F16 GPIO_4

R4 GPIO_5 G16 GPIO_5

T3 GPIO_6 H16 GPIO_6

R3 GPIO_7 J16 GPIO_7

R5 GPIO_8 L16 GPIO_8

T2 GPIO_9 M16 GPIO_9

J5 HDMI_CLKM K19 HDMI_CLKM

J6 HDMI_CLKP K20 HDMI_CLKP

K5 HDMI_D0M J19 HDMI_D0M

K6 HDMI_D0P J20 HDMI_D0P

J3 HDMI_D1M G19 HDMI_D1M

J4 HDMI_D1P G20 HDMI_D1P

K3 HDMI_D2M F19 HDMI_D2M

K4 HDMI_D2P F20 HDMI_D2P

K2 HDMI_DDCCEC H19 HDMI_DDCCEC

K1 HDMI_HPD K18 HDMI_HPD

J1 HDMI_REF

L7 HDMI_VP L14 HDMI_VP

M7 HDMI_VPH K14 HDMI_VPH

H6 JTAG_MOD U19 JTAG_MOD

H5 JTAG_TCK T17 JTAG_TCK

G5 JTAG_TDI V18 JTAG_TDI

G6 JTAG_TDO V17 JTAG_TDO

C3 JTAG_TMS T18 JTAG_TMS

C2 JTAG_TRST_B T16 JTAG_TRST_B

W5 KEY_COL0 E12 KEY_COL0

U7 KEY_COL1 E13 KEY_COL1

W6 KEY_COL2 C14 KEY_COL2

U5 KEY_COL3 W13 KEY_COL3_PMIC_SCL

i.MX6(KEY_COL3) connects to PF0100 (SCL).

T6 KEY_COL4 C15 KEY_COL4

V6 KEY_ROW0 E11 KEY_ROW0

U6 KEY_ROW1 F14 KEY_ROW1

W4 KEY_ROW2 D14 KEY_ROW2

T7 KEY_ROW3 W12 KEY_ROW3_PMIC_SDA

i.MX6(KEY_ROW3) connects to PF0100 (SDA).

V5 KEY_ROW4 D15 KEY_ROW4

Y11 LICELL PF0100 - Coin cell supply input/output

V4 LVDS0_CLK_N B19 LVDS0_CLK_N

V3 LVDS0_CLK_P B20 LVDS0_CLK_P

U2 LVDS0_TX0_N E19 LVDS0_TX0_N

U1 LVDS0_TX0_P E20 LVDS0_TX0_P

U4 LVDS0_TX1_N D19 LVDS0_TX1_N

U3 LVDS0_TX1_P D20 LVDS0_TX1_P

V2 LVDS0_TX2_N C19 LVDS0_TX2_N

V1 LVDS0_TX2_P C20 LVDS0_TX2_P

W2 LVDS0_TX3_N A18 LVDS0_TX3_N

W1 LVDS0_TX3_P B18 LVDS0_TX3_P

Y3 LVDS1_CLK_N A16 LVDS1_CLK_N

Y4 LVDS1_CLK_P B16 LVDS1_CLK_P

Y1 LVDS1_TX0_N A17 LVDS1_TX0_N

Y2 LVDS1_TX0_P B17 LVDS1_TX0_P

AA2 LVDS1_TX1_N B15 LVDS1_TX1_N

AA1 LVDS1_TX1_P A15 LVDS1_TX1_P

AB1 LVDS1_TX2_N B14 LVDS1_TX2_N

AB2 LVDS1_TX2_P A14 LVDS1_TX2_P

AA3 LVDS1_TX3_N A13 LVDS1_TX3_N

AA4 LVDS1_TX3_P B13 LVDS1_TX3_P

A11 MLB_CN not connected

B11 MLB_CP not connected

B10 MLB_DN not connected

A10 MLB_DP not connected

A9 MLB_SN not connected

B9 MLB_SP not connected

A16 NANDF_ALE U15 NANDF_ALE

C15 NANDF_CLE T15 NANDF_CLE

F15 NANDF_CS0 T14 NANDF_CS0

C16 NANDF_CS1 Y16 NANDF_CS1

A17 NANDF_CS2 W16 NANDF_CS2

D16 NANDF_CS3 U16 NANDF_CS3

A18 NANDF_D0 R13 NANDF_D0

C17 NANDF_D1 T13 NANDF_D1

F16 NANDF_D2 R12 NANDF_D2

D17 NANDF_D3 T12 NANDF_D3

A19 NANDF_D4 R11 NANDF_D4

B18 NANDF_D5 T11 NANDF_D5

E17 NANDF_D6 R10 NANDF_D6

C18 NANDF_D7 T10 NANDF_D7

B16 NANDF_RB0 U14 NANDF_RB0

E15 NANDF_WP_B V16 NANDF_WP_B

V13 NOR_HOLD_B

Connected internally to NVCC_EIM0_NOR through a 10kOhm resistor.

AA13 NOR_W_B

Connected internally to NVCC_EIM0_NOR through a 10kOhm resistor.

N7 NVCC_CSI H15 NVCC_CSI

NVCC_DRAM NVCC_DRAM

K19 NVCC_EIM0 L5 NVCC_EIM0_NOR

L19 NVCC_EIM1 K5 NVCC_EIM1

M19 NVCC_EIM2 J5 NVCC_EIM2

R19 NVCC_ENET G5 NVCC_ENET

P7 NVCC_GPIO G15 NVCC_GPIO

J7 NVCC_JTAG P15 NVCC_JTAG

P19 NVCC_LCD H5 NVCC_LCD

V7 NVCC_LVDS2P5 F15 NVCC_LVDS2P5

K7 NVCC_MIPI M14 NVCC_MIPI

G15 NVCC_NANDF P10 NVCC_NANDF

E8 NVCC_PLL_OUT R14 NVCC_PLL_OUT

G18 NVCC_RGMII M5 NVCC_RGMII

G16 NVCC_SD1 M6 NVCC_SD1

G17 NVCC_SD2 N10 NVCC_SD2

G14 NVCC_SD3 P11 NVCC_SD3

D12 ONOFF AD13 ONOFF

A2 PCIE_REXT grounded in package

B1 PCIE_RXM Y20 PCIE_RXM

B2 PCIE_RXP Y19 PCIE_RXP

A3 PCIE_TXM AA19 PCIE_TXM

B3 PCIE_TXP AA20 PCIE_TXP

H7 PCIE_VP N15 PCIE_VP

G7 PCIE_VPH N12 PCIE_VPH

G8 PCIE_VPTX N14 PCIE_VPTX

Y8 PMIC_ICTEST

PF0100 - Reserved pin. Connect to GND in application.

Y13 PMIC_SDWNB

PF0100 - Open drain signal to indicate an imminent system shutdown.

AD9 PMIC_VCOREREF PF0100 - Main band gap reference.

Y9 PMIC_VDDOTP PF0100 - Supply to program OTP fuses.

C24 RGMII_RD0 N1 RGMII_RD0

B23 RGMII_RD1 N2 RGMII_RD1

B24 RGMII_RD2 M1 RGMII_RD2

D23 RGMII_RD3 M2 RGMII_RD3

D22 RGMII_RX_CTL P2 RGMII_RX_CTL

B25 RGMII_RXC P1 RGMII_RXC

C22 RGMII_TD0 T1 RGMII_TD0

F20 RGMII_TD1 T2 RGMII_TD1

E21 RGMII_TD2 R1 RGMII_TD2

A24 RGMII_TD3 R2 RGMII_TD3

C23 RGMII_TX_CTL U2 RGMII_TX_CTL

D21 RGMII_TXC U1 RGMII_TXC

D9 RTC_XTALI V19 RTC_XTALI

C9 RTC_XTALO V20 RTC_XTALO

C14 SATA_REXT grounded in package

A14 SATA_RXM AE17 SATA_RXM

B14 SATA_RXP AD17 SATA_RXP

B12 SATA_TXM AE18 SATA_TXM

A12 SATA_TXP AD18 SATA_TXP

G13 SATA_VP N13 SATA_VP

G12 SATA_VPH N11 SATA_VPH

D20 SD1_CLK AE14 SD1_CLK

B21 SD1_CMD AD14 SD1_CMD

A21 SD1_DAT0 AE16 SD1_DAT0

C20 SD1_DAT1 AD16 SD1_DAT1

E19 SD1_DAT2 AE15 SD1_DAT2

F18 SD1_DAT3 AD15 SD1_DAT3

C21 SD2_CLK AB13 SD2_CLK

F19 SD2_CMD AC13 SD2_CMD

A22 SD2_DAT0 AB14 SD2_DAT0

E20 SD2_DAT1 AB12 SD2_DAT1

A23 SD2_DAT2 AC12 SD2_DAT2

B22 SD2_DAT3 AC14 SD2_DAT3

D14 SD3_CLK AC17 SD3_CLK

B13 SD3_CMD AC16 SD3_CMD

E14 SD3_DAT0 AC18 SD3_DAT0

F14 SD3_DAT1 AB17 SD3_DAT1

A15 SD3_DAT2 AB18 SD3_DAT2

B15 SD3_DAT3 AA17 SD3_DAT3

D13 SD3_DAT4 Y17 SD3_DAT4

C13 SD3_DAT5 Y18 SD3_DAT5

E13 SD3_DAT6 W17 SD3_DAT6

F13 SD3_DAT7 W18 SD3_DAT7

D15 SD3_RST AB16 SD3_RST

E16 SD4_CLK P9 SD4_CLK

B17 SD4_CMD N9 SD4_CMD

D18 SD4_DAT0 N8 SD4_DAT0

B19 SD4_DAT1 P8 SD4_DAT1

F17 SD4_DAT2 N7 SD4_DAT2

A20 SD4_DAT3 P7 SD4_DAT3

E18 SD4_DAT4 N6 SD4_DAT4

C19 SD4_DAT5 P6 SD4_DAT5

B20 SD4_DAT6 N5 SD4_DAT6

D19 SD4_DAT7 P5 SD4_DAT7

AE9 SW1ABFB

AD7 SW1ABLX

AD8 SW1ABLX

AE6 SW1ABLX

AE7 SW1ABLX

AE8 SW1ABLX

AE5 SW1CFB

AD4 SW1CLX

AD5 SW1CLX

AD6 SW1CLX

AE4 SW1CLX

W1 SW2LX

W2 SW2LX

W3 SW2LX

Y1 SW2LX

Y2 SW2LX

Y3 SW2LX

W6 SW3ABLX

W7 SW3ABLX

Y6 SW3ABLX

Y7 SW3ABLX

AA1 SW4LX

AA2 SW4LX

AB2 SW4LX

Y10 SWBSTFB

AB10 SWBSTIN

AA10 SWBSTLX

AA11 SWBSTLX

AC10, AC11, AC2, AC3, AD10, AD11, AD2, AD3, AE10, AE11, AE2, AE3, V7, V8 SYS_4V2 Main system supply

C11 POR_B AE12 SYS_POR_B

GOES BETWEEN PMIC(RESETBMCU) AND I.MX6Q(POR_B)

D11 PMIC_ON_REQ AE13 SYS_PWRON

I.MX6Q(PMIC_ON_REQ) IS SHORTED TO PMIC(PWRON) THROUGH A 1.6kOhm resistor.

F11 PMIC_STBY_REQ AB15 SYS_STBY_REQ

GOES BETWEEN PMIC(STANDBY) AND I.MX6Q(PMIC_STBY_REQ)

AB1 SYS_SW4FB_VIN1 SHORTS THE PMIC PINS – SW4FB AND VIN1

V1 SYS_SW2FB_VIN2 SHORTS THE PMIC PINS – SW2FB AND VIN2

W10 SYS_VSNVS

PMIC(VSNVS) IS SHORTED TO I.MX6Q(VDD_SNVS_IN AND NVCC_RESET)

E11 TAMPER U13 TAMPER

E12 TEST_MODE R9 TEST_MODE

F10 USB_H1_DN AD20 USB_H1_DN

E10 USB_H1_DP AD19 USB_H1_DP

D10 USB_H1_VBUS AE19 USB_H1_VBUS

B8 USB_OTG_CHD_B AB19 USB_OTG_CHD_B

B6 USB_OTG_DN AC19 USB_OTG_DN

A6 USB_OTG_DP AC20 USB_OTG_DP

E9 USB_OTG_VBUS AB20 USB_OTG_VBUS

N12 VDD_CACHE_CAP

B5 VDD_FA

G9 VDD_SNVS_CAP P12 VDD_SNVS_CAP

G11 VDD_SNVS_IN

PMIC(VSNVS) IS SHORTED TO I.MX6Q(VDD_SNVS_IN AND NVCC_RESET)

VDDARM_CAP VDDARM_CAP M10 VDDARM_CAP

VDDARM_CAP VDDARM_CAP M11 VDDARM_CAP

VDDARM_CAP VDDARM_CAP M12 VDDARM_CAP

VDDARM_IN VDDARM_IN M7 VDDARM_IN

VDDARM_IN VDDARM_IN M8 VDDARM_IN

VDDARM_IN VDDARM_IN M9 VDDARM_IN

VDDARM23_CAP VDDARM23_CAP K13 VDDARM23_CAP

VDDARM23_CAP VDDARM23_CAP L13 VDDARM23_CAP

VDDARM23_CAP VDDARM23_CAP M13 VDDARM23_CAP

VDDARM23_IN VDDARM23_IN J15 VDDARM23_IN

VDDARM23_IN VDDARM23_IN K15 VDDARM23_IN

VDDARM23_IN VDDARM23_IN L15 VDDARM23_IN

VDDHIGH_CAP VDDHIGH_CAP P14 VDDHIGH_CAP

VDDHIGH_IN VDDHIGH_IN R15 VDDHIGH_IN

VDDPU_CAP VDDPU_CAP J6 VDDPU_CAP

VDDPU_CAP VDDPU_CAP K6 VDDPU_CAP

VDDPU_CAP VDDPU_CAP L6 VDDPU_CAP

VDDSOC_CAP VDDSOC_CAP F12 VDDSOC_CAP

VDDSOC_CAP VDDSOC_CAP F13 VDDSOC_CAP

VDDSOC_CAP VDDSOC_CAP G13 VDDSOC_CAP

VDDSOC_CAP VDDSOC_CAP H13 VDDSOC_CAP

VDDSOC_IN VDDSOC_IN G8 VDDSOC_IN

VDDSOC_IN VDDSOC_IN H6 VDDSOC_IN

VDDSOC_IN VDDSOC_IN H7 VDDSOC_IN

VDDSOC_IN VDDSOC_IN H8 VDDSOC_IN

F9 VDDUSB_CAP P13 VDDUSB_CAP

AD1 VGEN1

AC1 VGEN2

U5 VGEN3

W5 VGEN4_1V8

V9 VGEN5

U10 VGEN6

A7 XTALI T19 XTALI

B7 XTALO T20 XTALO

AE17 ZQPAD grounded in package

1. The following balls are all ground pins and should be connected to ground:

A1, A20, AA12, AA14, AA15, AA16, AA18, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AB11, AB3, AB4, AB5, AB6, AB7, AB8, AB9, AC15, AC4, AC5, AC6, AC7, AC8, AC9, AE20, C16, E10, E6, E7, E8, F10, F11, F6, F7, F8, F9, G10, G11, G12, G14, G6, G7, G9, H10, H11, H12, H14, H20, H9, J1, J10, J11, J12, J13, J14, J7, J8, J9, K10, K11, K12, K7, K8, K9, L10, L11, L12, L18, L7, L8, L9, R3, R6, R7, R8, T6, T7, T8, T9, U20, U6, U7, U8, U9, V10, V11, V14, V2, V6, W11, W14, W15, W4, W9, Y12, Y14, Y15, Y4, Y5, AE1

7.2. Package Information and Contact Assignments

8. Revision History

Revision Date Author Notes

0.1 4/29/2015 John Phillippe

0.2 6/11/2015 John Phillippe Updated TOC Updated ordering info. Updated pin list.