Scalable Processor Architecture (SPARC) Jeff Miles Joel Foster Dhruv Vyas.
-
date post
20-Dec-2015 -
Category
Documents
-
view
224 -
download
1
Transcript of Scalable Processor Architecture (SPARC) Jeff Miles Joel Foster Dhruv Vyas.
Overview
• Designed to optimize compilers and pipelined hardware implementations
• Offers fast execution rates
• Engineered at Sun Microsystems in 1985– Based on RISC I & II which were developed at
Univ of Cal at Berkeley
• SPARC “register window” architecture
Features
• Performance and Economy– Simplified instruction set– Higher number of instructions with fewer transistors
• Scalability– Flexible integration of cache, memory and FPUs
• Open Architecture– Compatible technology to multiple vendors– Now allow access to CPU component techniques– Complete set of development tool available for h/w & s/w
Architecture
• RISC machine • 64-bit addressing and 64-bit data• Increased bandwidth• Fault tolerance• Nine stage pipeline; can do up to 4
instructions per cycle• On-chip 16Kb data and instruct. Caches
– With 2Mb external cache
Registers
• General purpose/ working data registers– IU’s ‘r’ registers– FPU’s ‘f’ registers
• Control status registers– IU control/status registers– FPU control/status registers– Coprocessor (CP) control/status registers
Registers Window Overlapping
• Each window shares its ins and outs with two adjacent windows– Incremented by a RESTORE instruction
decremented by a SAVE instruction– Due to windowing the number available to
software is 1 less than number implemented – When a register is full the outs of the newest
window are the ins of the oldest, which still contain valid program data
IU Control/Status Registers
• Processor State Register (PSR)
• Window Invalid Mask (WIM)
• Multiply/Divide (Y)
• Program Counters (PC, nPC)
• Ancillary State Registers (ASR)
• Deferred-Trap Queue
• Trap Base Register (TBR)
IU Control/Status Registers
• Processor State Register (PSR)– Contains various fields that control and hold
status information
• Window Invalid Mask (WIM)– To determine a window overflow or underflow
Impl Ver Icc Reserved EC EF PIL S PS ET CWP
W31 W30 W29 ----------------------- W1 W0
31:28 27:24 23:20 19:14 13 12 11:8 7 6 5 4:0
Memory
• Each location identified by– Address Space Identifier (ASI)– 64-bit address
• Real memory– No side effects
• I/O locations– Side effects
Instruction Formats
• VIS – Visual Instruction Set– Visualization built into chip
• Examples of formats
UltraSPARC-IIi HP PA-8000 Cyrix MediaGX MIPS R10000 Intel Pentium II PowerPC 603eArchitecture SPARC V-9 HP-PA X86 MIPS III X86 PowerPC
Open versus proprietary Open Proprietary Proprietary Open Proprietary Open
64-bit architecture Ð Ð Ð Ð
High volume processor Ð Ð Ð Ð
High bandwidth Ð
Integration LevelOn-chip MMU Ð Ð Ð Ð
On-chip I/O interface Ð Ð Ð Ð
On-chip cache Ð Ð Ð Ð Ð
On-chip multimedia support Ð Ð
FeaturesClock speed 300 MHz 180 MHz 180 Mhz 195 MHz 233-300 Mhz 300 MHz
Binary compatibility with existing applications Ð Ð Ð Ð Ð Ð
PerformanceSPECint95/fp95 >12/>12 11.8/18.7 N/A 10.7/19.0 11.7/8.15 7.4/6.1
Low cost Workstations Low-power,desktops and servers
and low-costHigh-end embedded applications: networking,
servers desktops and
portables
Processor Comparison Summary
Target Environment
Desktops WorkstationsWorkstations and servers
What makes the CISC lock-up?
• Elegant forward looking branch instruction set– Compiler can go to different branches
• More complete testing of SPARC• Simpler compiler design• Better integration of OS interrupts to H/W
interrupts• Solaris has a tighter source code
– Less devices to support
References
Weaver, David/Tom Germond. SPARC Architecture Manual: Version 9, Prentice Hall. 1994.
Stallings, William. Computer Organization and Architecture: 5th Edition, Prentice Hall. 2000.
Bresani, Fred. Systems Engineer, Sun Microsystems.
http://www.sun.com
http://www.sparc.com
http://www.fujitsu.com