SAR TDC Architecture for One-Shot Timing …...Kobayashi Lab. Gunma University SAR TDC Architecture...
Transcript of SAR TDC Architecture for One-Shot Timing …...Kobayashi Lab. Gunma University SAR TDC Architecture...
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Kobayashi Lab.
Gunma University
SAR TDC Architecture
for One-Shot Timing Measurement
with Full Digital Implementation
Y. Ozawa, T. Ida, R. Jiang, S. Sakurai, R.Takahashi,
R. Shiota, H. Kobayashi
Gunma University, Socionext Inc.,
Nov. 8 WP-L2 14:30-15:50
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Objective
Development of
highly-linear, fine time-resolution TDC
for high-speed digital I/O interface timing measurement
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Innovation
Trigger Circuit
One-shot timing measurement
&
Good for low frequency repetitive timing
Ring Oscillator
One-shot timing measurement
&
Good for high & low frequency repetitive timing
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Approach
Full digital FPGA implementation
SAR TDC
SAR TDC + Ring Oscillator
SAR TDC + Trigger CircuitMeasure one-shot timing
Include analog circuit
Measure one-shot timing
Without analog circuit
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Problems in Operation of SAR
SAR TDCInput signal Output signal
Analog Digital
During measurement
The necessity to always input certain time difference
Circuit approach to problem
Multiple steps required
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Outline
Research Objective
Conventional TDC Architecture
- Flash TDC
SAR TDC Architecture & Operation
Proposed SAR TDC – Analog Centric
Proposed SAR TDC – Digital Centric
- Architecture & Operation
- High Frequency
- Low Frequency
- Simulation
Conclusion
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Outline
Research Objective
Conventional TDC Architecture
- Flash TDC
SAR TDC Architecture & Operation
Proposed SAR TDC – Analog Centric
Proposed SAR TDC – Digital Centric
- Architecture & Operation
- High Frequency
- Low Frequency
- Simulation
Conclusion
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Time to Digital Converter (TDC)
T
Start
Stop
Start
StopDoutTDC
1996 1998 2000 2002 2004 2006 20080
10
20
30
40
50
Year
LS
B [
ps]
Higher resolution with CMOS scaling
● Time interval → Measurement → Digital value
● Key component of Time-
domain analog circuit
● Higher resolution can be
obtained with scaled CMOS
8
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Background
Voltage domain
Fine CMOS
Time domain
time
Fine CMOStime
A Time-to-Digital Converter (TDC) provides a digital outputproportional to time between two clock transitions.
(e.g. I/O interface, Sensor Interfaces, All-Digital PLLs, ADCs, .. )
Supplyvoltage
The TDC is a key component in time-domain analog circuits,
Advanced CMOS VLSI● Low power-supply voltages● Fast switching speeds
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Time Domain Analog Circuit Features
● Voltage domain:
Signal range : Up to power supply voltage
Time domain:
Signal range : Time continues indefinitely
Large dynamic range
● Time domain analog circuit:
Binary amplitude(Vss, Vdd)
Can consist of digital circuit
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Outline
Research Objective
Conventional TDC Architecture
- Flash TDC
SAR TDC Architecture & Operation
Proposed SAR TDC – Analog Centric
Proposed SAR TDC – Digital Centric
- Architecture & Operation
- High Frequency
- Low Frequency
- Simulation
Conclusion
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Flash-type TDC
12
D1 D2 D3
・・・DQ
DQ
DQ
Stop
Start τ τ τ τ
DQ
D4
a b c d
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Outline
Research Objective
Conventional TDC Architecture
- Flash TDC
SAR TDC Architecture & Operation
Proposed SAR TDC – Analog Centric
Proposed SAR TDC – Digital Centric
- Architecture & Operation
- High Frequency
- Low Frequency
- Simulation
Conclusion
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SAR ADC Block
Sample Hold
DAC
SAR
Logic
Analog
input
Digital
output
ComparatorCLK
SAR ADC is digital centric.
→ Suitable for fine CMOS implementation.
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D-FF can be greatly reduced
by using MUX
Circuit operation loop can be made
with Successive Approximation
Flash type TDC
SAR TDC
SAR TDC Architecture
SAR : Successive Approximation Register
Multiplexer
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SAR ADC : Comparator DAC
SAR TDC : D-FF Delay Line
SAR-ADC
SAR-TDC
SAR-ADC VS SAR-TDC
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STEP1
Example ΔT = 4.3 τ
t t t t t t t
CLK1
Multiplexerr
D QCLK2SAR Logic
Dout
3
3
select100
1
0
SAR TDC Operation
ΔT ΔT ΔT
CLK1
CLK2
ΔT
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t t t t t t t
CLK1
Multiplexerr
D QCLK2SAR Logic
Dout
3
3
select
10
0
110
STEP2
ΔT ΔT ΔT
CLK1
CLK2
ΔT
Example ΔT = 4.3 τ
SAR TDC Operation
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CLK1
t t t t t t t
Multiplexerr
D QCLK2SAR Logic
Dout
3
3
select
0
101
100
STEP3
ΔT ΔT ΔT
CLK1
CLK2
ΔT
Example ΔT = 4.3 τ
SAR TDC Operation
Digital Output:4
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Digital Output:4
t t t t t t t
CLK1
Multiplexerr
D QCLK2SAR Logic
Dout
3
3
select
101
1
100
100
STEP4
(Stable)
ΔT ΔT ΔT
CLK1
CLK2
ΔT
Example ΔT = 4.3 τ
SAR TDC Operation
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Outline
Research Objective
Conventional TDC Architecture
- Flash TDC
SAR TDC Architecture & Operation
Proposed SAR TDC – Analog Centric
Proposed SAR TDC – Digital Centric
- Architecture & Operation
- High Frequency
- Low Frequency
- Simulation
Conclusion
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Trigger Circuit
Output starts to oscillate
at rising timing edge of input
Output waveform with no transient change
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T/H Circuit
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Trigger Circuit Waves
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Combination of Trigger Circuit & SAR TDC
Proposed Circuit
START
STOP
One-shot signal
∆𝑇
W1
W2
∆𝑇
clk1
clk2
Repetitive signals
∆𝑇 ∆𝑇
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Simulation Results
2 trigger circuits can generate
repetitive signals
One-shot timing
can be measured
with SAR TDC
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Outline
Research Objective
Conventional TDC Architecture
- Flash TDC
SAR TDC Architecture & Operation
Proposed SAR TDC – Analog Centric
Proposed SAR TDC – Digital Centric
- Architecture & Operation
- High Frequency
- Low Frequency
- Simulation
Conclusion
![Page 28: SAR TDC Architecture for One-Shot Timing …...Kobayashi Lab. Gunma University SAR TDC Architecture for One-Shot Timing Measurement with Full Digital Implementation Y. Ozawa, T. Ida,](https://reader030.fdocuments.in/reader030/viewer/2022040812/5e54e40a423e4d7f9a5e0d6e/html5/thumbnails/28.jpg)
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Ring Oscillator
Single-shot signal Timing signal
Self replicating
D Q
select
3
3Dout1
SAR Logic
𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏
Multiplexer
𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏
Mu
ltiplexer
Mu
ltiplexer
START
STOP
𝜏𝑖
𝜏𝑖
Ring OscillatorⅠ
Ring OscillatorⅡ
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Ring Oscillator
∆𝑇 ∆𝑇 ∆𝑇 ∆𝑇
START
STOP
Ring
OscillatorⅠ
Ring
OscillatorⅡ 𝑇𝑅𝑂2 𝑇𝑅𝑂
2
𝑇𝑅𝑂2
𝑇𝑅𝑂2 𝑇𝑅𝑂
2
𝑇𝑅𝑂2 𝑇𝑅𝑂
2 𝑇𝑅𝑂2
𝜏 𝜏 𝜏
𝜏𝑖
Signal
In 3-bit case
𝑇𝑅𝑂 2 = 7𝜏 + 𝜏𝑖
If τ = 1ns and τi = 1ns,
∆𝑇 ≤ 𝑇𝑅𝑂 2 = 7 + 1 = 1ns
⇒ Resolution of 1ns
𝑇𝑅𝑂 = 2(𝑛𝜏 + 𝜏𝑖)
∆𝑇 ≤ 𝑇𝑅𝑂 2
Periodic time 𝑇𝑅𝑂
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Frequency Repetitive Clock Measurement
10𝑛𝑠 × 10 = 100𝑛𝑠
Ring Oscillator
2GHz
High Frequency
Low Frequency
0.01Hz
10𝑛𝑠 × 10 = 100𝑛𝑠
Ring Oscillator
High Frequency
Low Frequency
Ready
CLK1
(CLK2)
Ring Oscillator I
(Ring Oscillator II)
START
(STOP)
Ready
CLK1
(CLK2)
Ring Oscillator I
(Ring Oscillator II)
START
(STOP)
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Simulated Circuit
D Q
CLR
D Q
CLR
D Q
CLR
D Q
CLR
D Q
CLR
D Q
CLR
D Q
CLR
D Q
CLR
D Q
D Q
D Q
D Q
D Q
Q
Q
Q
Q
START STOP
D0D1D2
Ring OscillatorⅠ Ring OscillatorⅡ
SAR Logic
Control Unit
MUX
D-FF(COMP)𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏 𝜏
𝜏𝑖𝜏𝑖
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STA
RT
ST
OP
One-Shot Input Signal
∆𝑇 =5.2ns
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Simulated Ring Oscillator WaveformsR
ing
Oscill
ato
rⅠR
ing
Oscill
ato
rⅡ
∆𝑇 ∆𝑇 ∆𝑇 ∆𝑇 ∆𝑇 ∆𝑇 ∆𝑇 ∆𝑇∆𝑇
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D-FF Output Signal at Each Step
Δ𝑇 > 4𝜏= 100
Δ𝑇 < 6𝜏= 110
Δ𝑇 > 5𝜏= 101 Δ𝑇 =5.2ns
1
D0
D1
D2
1 1 1
0
0
1
0 1 1
0 0
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Input Output Linearity
Proposed SAR TDC input & output have linear relationship
𝑇[ns]
Output
000
001
111
110
010
011
100
101
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Outline
Research Objective
Conventional TDC Architecture
- Flash TDC
SAR TDC Architecture & Operation
Proposed SAR TDC – Analog Centric
Proposed SAR TDC – Digital Centric
- Architecture & Operation
- High Frequency
- Low Frequency
- Simulation
Conclusion
![Page 37: SAR TDC Architecture for One-Shot Timing …...Kobayashi Lab. Gunma University SAR TDC Architecture for One-Shot Timing Measurement with Full Digital Implementation Y. Ozawa, T. Ida,](https://reader030.fdocuments.in/reader030/viewer/2022040812/5e54e40a423e4d7f9a5e0d6e/html5/thumbnails/37.jpg)
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Discussion (1)
SAR TDC operates with external clock
Operation speed depends on measured clock
witch may be variable
Employing ring oscillators
Frequency is fixed
Reasonable as mixed-signal circuit design
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Discussion (2)
Assumption
Two ring oscillators are completely matched
(oscillation frequencies are the same)
In reality they are not
Future work
Mismatch compensation or self-calibration method
(e.g. redundancy SAR algorithm)
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Conclusion
Trigger circuit can generate repetitive signals
Ring oscillator helps the realization of full digital FPGA
One shot timing can be measured with SAR TDC
The remaining work Taking care of mismatches between two ring oscillators
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Time is GOLD !!
TDC is a key.
Time continues indefinitely.