RTL coding guidelines - National Chiao Tung …twins.ee.nctu.edu.tw/.../RTL_coding_guidelines.pdfRTL...

RTL Coding GuidelinesMichael Keating & Pierre BricaudReuse Methodology Manual, for SoC designs, 2nd

Tzung-Shian YangVLSI Signal Processing Group

Department of Electronics Engineering

National Chiao Tung University

Nov. 2001 RTL Coding Guidelines - Tzung-Shian Yang 2

Outline

Basic coding practicesCoding for portabilityGuidelines for clocks and resetsCoding for synthesisPartitioning for synthesisConclusion

Basic Coding Practices


Basic Goal

Develop RTL code simplesimplesimplesimple and regularregularregularregularEasier to design, code, verify andsynthesize

Consistent coding style, namingconventions and structureEasy to understand

Comments, meaningful names andconstants or prarameters instead of hard-coded numbers


Naming Convention

Lowercase letters for all signal, variableand port namese.g. wire clk, rst;Uppercase letters for names ofconstants and user-defined typese.g. `define MY_BUS_LENGTH 32Meaningful names

For a RAM address bus, ram_addr insteadof ra


Naming Convention (2)

Short but descriptiveDuring elaboration, the synthesis toolconcatenates the names

clk for clock signal,More than one clock? → clk1, clk2 orclk_interface …

Active low signals: postfix with ‘_n’rst for reset signals, if active low→rst_n



When describing multibit buses, use aconsistent ordering of bits

For Verilog: use (x:0) or (0:x)

The same or similar names for portsand signals that are connected(e.g. a=>a or a=>a_int)



Other naming conventions*_r : output of a register*_a : asynchronous signal*_z : tristate internal signal*_pn : signal used in the nth phase*_nxt : data before being registered into a

register with the same name


Include Header

e.g./ *This confidential and proprietary *software … * © copyright 1996 Synopsys inc. *File : Dwpci_core.v *Author : Jeff Hackett *Date : mm/dd/yy *Version : 0.1 *Abstract : … *Modification History : date, by who, version,change description … */


Comment

Placed logically, near the code thatdescribeBrief, concise and explanatorySeparate line for each HDL statementsKeep the line length to 72 characters orlessalways @(a or b or c or d or e or f or g orororor

h or i)


IndentationImprove the readability of continued code lines andnested loops, tab of 4 is recommendedif(a)

if(b) if(c) …

Port orderingmodule my_module(clk, rst, …);{ // Inputs:

clk, // comment for eachrst, // ……

// Outputs:…

}


Port Map

Use named association rather thanpositional associationmy_module U_my_module(

.clk(.clk(.clk(.clk(clk)))), .rst(.rst(.rst(.rst(rst)))), …);


Use Function

function [`BUS_WIDTH-1:0] convert_address;input input_address, offset;begin

// … function bodyendendfunction //convert_address


Use Loop and Array

module my_module( … );…reg [31:0] reg_file[15:0];integer tmp;

always @(posedge clk or posedge rst)if(rst)

for(tmp=0; tmp<16; tmp++)reg_file[tmp] <= 32’d0;

…


Meaningful Label

Helpful for debugLabel each process block <name>_PROCLabel each instance U_<name>

Coding for Portability


Portability

Create code technology-independent,compatible with various simulation tools andeasily translatable between Verilog and VHDLConstants instead of hard-coded value`define MY_BUS_SIZE 8reg [`MY_BUS_SIZE-1:0] my_out_bus ;

Keep the `define statements for a design in asingle separate file and name the fileDesignName_params.v


Technology Independent

Avoid embedding dc_shell scriptsexception: the synthesis directives to turn synthesison and off must be embedded in the code in theappropriate places

Use DesignWare Foundation LibrariesAvoid instantiating gatesIf you must use technology-specific gates,then isolate these gates in a separate module

Guidelines for Clocks and Resets


Clock and Reset

Simple clocking structure: a singleglobal clock and positive edge-triggeredflops as the only sequential devices

clk


Mixed Clock Edges

Avoid!Duty cycle of the clock become a critical issue intiming analysisMost scan-based testing methodologies requireseparate handling of positive and negative-edgetriggered flops

If you must use both,Model the worst case duty cycleDocument the assumed duty cycleIf you must use many, separate them intodifferent modules


Clock Buffer

Avoid hand instantiatinghand instantiatinghand instantiatinghand instantiating clock buffers inRTL code. They are normally insertedafter synthesis as part of the physicaldesign.Avoid internally generated clocks andresets, all the registers in the macroshould be reset at the same time


Gated Clock

Avoid coding gated clocks in RTLin RTLin RTLin RTLCannot be made part of a scan chainIf you must use, keep the clock and/orreset generation circuitry as a separatemodule at the top level of the design ormodel it using synchronous load registerse.g. always @(posedge clk)

if(p1_gate)…

Coding for Synthesis


Infer Register

Use reset signal to initialize registeredsignals instead of use an initialstatementAvoid using any latches

Assign default value for all pathAssign outputs for all input conditionsUse else for the final priority branch

Avoid combinational feedback


Sensitivity ListSpecify complete sensitivity list avoiddifference between pre-synthesis and post-synthesis netlist in combinational blocksInclude clock and reset in sequential blocksAvoid unnecessary signals in list

always @(a) c=a or b;

b

a

c

b

a

c

ab c

pre-synthesis post-synthesissynthesized netlist


Case v.s. if-then-elseA case statement infers a single-levelsingle-levelsingle-levelsingle-levelmultiplexer, while an if-then-else one infers apriority-encodedpriority-encodedpriority-encodedpriority-encoded, cascaded combination ofmultiplexersSynopsis directive about case statementcase (sel) // synopsis parallel_case full_case// synopsis parallel_case full_case// synopsis parallel_case full_case// synopsis parallel_case full_case

if-then-else can be useful if you have a latearriving signalFor large multiplexers, case is preferredbecause faster in cycle-based simulatorConditional assignment:e.g. assign z1=(sel_a) ? a : b ;


State Machines

Separate state machines into twoprocesses:combinational and sequential

Poor coding style:always @(posedge clk)

a <= b+c;

Recommended coding style:always @(b or c)

a_nst = b+c;always @(posedge clk)

a <= a_nst;

Partitioning for Synthesis


Partition for Synthesis

Good partition provides advantages:Better synthesis resultsFaster compile runtimesAbility to use simpler synthesis strategiesto meet timing


Register Output

For each block of a hierarchical design,register all output signals

Output drive strengths equal to the drive strengthof the average flip-flopInput delays predictable

Keep related combinational logic together inthe same module

C. CC. BC. A


CriticalPath Logic

Different Design Goals

Keep critical path logic in a separate module,optimize the critical path logic for speed whileoptimizing the noncritical path logic for area

clk

NoncriticalPath Logic

clk

SpeedOptimization

AreaOptimization


Asynchronous Logic

Avoid asynchronous logicIf required, partition in a separate modulefrom the synchronous logic

Merging resourcesmux input than mux output for complicatedprocessing unit


Partition for Synthesis Runtime

Most important considerations inpartition: logic function, design goalsand timing and area requirementsGrouping related functions togetherEliminate glue logic at the top level


Conclusion

Practice makes perfect

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