Integrated Development Environment - National Chiao Tung...

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Integrated Development EnvironmentIntegrated Development Environment

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�IDE

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AndeShape

AICE

IDEAndESLiveSimulator

AndESLiveBuilder

Toolchains

AndeSight AndESLive

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AndeSight IDEAndeSight IDE

�Window

�View

�Perspective

�Editor

�Preferences…

�Help

�Advanced features

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Andes Total SW SolutionAndes Total SW Solution

user

Integrated Development Environment (IDE)Integrated Development Environment (IDE)

Toolchains: Compiler

AssemblerLinker

Debugger

Toolchains: Compiler

AssemblerLinker

Debugger

Evaluation Board

Evaluation Board

ICEICE

SoC Builder

SoC Builder

SimulationEngine

SimulationEngine

AndeSightAndeSight™™

AndESLiveAndESLive™™ AndeShapeAndeShape™™

AndESLive™AndESLive™ AndeSight™AndeSight™ AndeShape™AndeShape™Andes SW SolutionAndes SW Solution == ++ ++

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Integrated Development EnvironmentIntegrated Development Environment

Toolbar

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WindowsWindows

�What is window

� The overall outer frame

�New window

� Menu bar � Window � New Window• Same workspace and perspective

� Start another AndeSight

• Different workspace

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WindowsWindows

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ViewsViews

�What is view

� View provides alternative presentations as well as ways to navigate the information in your Workbench.

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ViewsViews

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PerspectivesPerspectives

�What is perspective

� The initial set and layout of views in the Workbench window.

� Each perspective provides a set of functionality aimed at accomplishing a specific type of task or works.

�We provide

� C/C++ coder

� Debug

� VEP Config (Andeslive)

� Profiling

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PerspectivesPerspectives

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Perspectives – Debug and ProfilerPerspectives – Debug and Profiler

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Perspectives – VEP (Virtual Evalution Platform) Config

Perspectives – VEP (Virtual Evalution Platform) Config

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Perspectives – Others…Perspectives – Others…

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EditorEditor

�Editors we provide

� C/C++

� Makefile

� Assembly

� Binary Hex

� VEP

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Features of C/C++ EditorFeatures of C/C++ Editor

�Content assistant

�Function Definition

�Auto completion

�Syntax highlight

�Formatter

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Content assistantContent assistant

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Show Function DefinitionShow Function Definition

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Text Auto CompletionText Auto Completion

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Template SupportTemplate Support

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FormatterFormatter

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PreferencesPreferences

�What settings are provided?

� Is used to set user preferences

� Can be searched using the filter function

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PreferencesPreferences

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Preference to Change FontsPreference to Change Fonts

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Commands and FunctionsCommands and Functions

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Help SystemHelp System

�Context sensitive help

� Hot key: F1

�Help Content

�Search …

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ProfilingProfiling

Andesight IDE

Andeslive Simulator

ProfilingProfiling

AnalysisAnalysis

EngineEngine

Prof.out

Profiling data preparationProfiling data preparation

Trigger Profiling

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Profiling OptionsProfiling Options

� Function Level� Pure function profiling without branch and cache information� With Branch Summary� With Cache Summary� With Branch and Cache Summary

� Branch Level� Pure branch profiling without cache information � With Cache Summary

� Views� Flat View� Call View� Timeline View� Chart View

� C and C++ Support� Fast Mode and Extended Mode� Goto Source

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Profiling OptionsProfiling Options

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Performance TuningPerformance Tuning

CoCo--SimSim

ProfilingProfiling

Meet Spec.Meet Spec.

ENDEND

Tune Performance by CPU ConfigurationTune Performance by CPU Configuration

Tune Performance by Software WorksTune Performance by Software Works

Yes

No

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Tune Performance by ProfilerTune Performance by Profiler

Profile Result of 8KB I$/D$

Profile Result of 64KB I$/D$

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Profiling – Timeline ViewProfiling – Timeline View

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Profiling – Call ViewProfiling – Call View

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Profiling – Flat ViewProfiling – Flat View

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Branch Level with Cache SummaryBranch Level with Cache Summary

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Build OptionsBuild Options

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Endian – SWEndian – SW

SW endian setting gives –EL or –EB option to compiler

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Endian – HWEndian – HW

HW endian setting gives option to simulator

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Library – SWLibrary – SW

SW library setting gives –mlib option to linker

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Library – HWLibrary – HW

HW library setting should enable Virtual IO support and select proper library for simulator

Window > Show View > Other

VEP > System Call Emulation

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Toolchain – SWToolchain – SW

Toolchain includes one for hardcore, one for softcore

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CPU SelectionCPU Selection

Virtual SoC Builder provides one hardcore and one softcore

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�Virtual Platform IntroductionFrom physical to virtual and vice versa

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What is Virtual Platform?What is Virtual Platform?

“It is a system-level simulation model that characterizes real system behavior. It operates at the level of processor instructions, function calls, memory accesses and data packet transfers, as opposed to the bit-accurate, nanosecond-accurate logic transitions of a register transfer level (RTL) model.”*

*from the book ESL Design and Verification: A Prescription for Electronic System Level Design Methodology. B. Bailey, G. Martin and A. Piziali.

Elsevier Morgan Kaufmann, 2007

Andes Development Platform Andes Virtual Platform

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Integrated Development Environment

S/W Development with Physical H/W PlatformS/W Development with Physical H/W Platform

SW Developer Desktop Target Hardware

DEVICE SOFTWARE STACK

External System Connectivity

Physical Target Connection

On-Chip-Debug, Ethernet, USB, …

PHYSICAL HARDWARE

Operating Systems

BSP/Device Drivers

Middleware

Applications

Operating Systems

BSP/Device Drivers

Middleware

Applications

Editor

Compiler

Debugger

Source Code Analysis

Build

Profiling Tools

CM

Other plug-in tools

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S/W Development with Virtual PlatformS/W Development with Virtual Platform

SW Developer Desktop


Virtual Platform

Operating Systems

BSP/Device Drivers

Middleware

Applications

Operating Systems

BSP/Device Drivers

Middleware

Applications

Editor

Compiler

Debugger

Source Code Analysis

Build

Profiling Tools

CM

Other plug-in tools

Tools/API

External System Connectivity

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�Andes Virtual Evaluation Platform

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Andeshape™ Platform SoC: AG101Andeshape™ Platform SoC: AG101

N1213N1213Bus

Controller

BusController

MAC10/100

MAC10/100 USB2.0USB2.0

LCDController

LCDController

SDRAM Controller

SDRAM Controller

DMA Controller

DMA Controller

SRAMController

SRAMController

PWMPWM I2CI2C GPIOGPIO INTCINTC WDTWDT TimerTimer RTCRTC

ST

UART

STUART

BT

UART

BTUART SSPSSP CFCF I2SI2S SD/

MMC

SD/MMC

PowerManager

PowerManager

AHB to APB

Bridge

AHB to APB

Bridge

AHB Bus

APB Bus

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Virtual Evaluation PlatformVirtual Evaluation Platform

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S/W Development with Andes ToolsS/W Development with Andes Tools

SW Developer Desktop (AndeSight)


VEP (AndESLive)

Operating Systems

BSP/Device Drivers

Middleware

Applications

Operating Systems

BSP/Device Drivers

Middleware

Applications

Editor

Compiler

Debugger

Assembler

Program Builder

Profiler

SOC Builder

Other plug-in tools

AndESLive/API

AndeSoft

Virtual I/O Connectivity

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AndeESLive VEP EnvironmentAndeESLive VEP Environment

VEP module

Module descriptor

SID component

User-defined Models

Peripheral IP Models

AndesCore Model

Customer SoC

Andes AG101Andes AG101

AndESLive™

C/C++

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VEP ModuleVEP Module

User-defined Models

Essential IP Models

AndesCore

Customer SoC

Andes AG101Andes AG101

AndESLive™VEP module

Module descriptor

SID component

C/C++

slave port

master port

write port read port

bus port

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Andes VEP (a quick summary)Andes VEP (a quick summary)

� SID, an open-source framework for building simulated Embedded Systems, has been integrated into AndESLiveas backbone simulator

� Simulated component, or a SID component, can be written in C/C++, or Tcl to which the SID API is bound

� VEP module is a SID component wrapped with XML-based Module Descriptor in which the parameters and attributes are described

� Andes provides sample code (C++-based) and SID example for modeling target (bus slave) and initiator (bus master) components that run on Andeslive

� Depending on the requirements from customers, Andes can provide Modeling Training and Services as well

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�SID SimulatorThe AndESLive simulation backbone

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SID OverviewSID Overview

� The SID simulator consists of an engine that loads and connectssimulated components, based on a simulator configuration file, and runs simulation sessions.

� The SID simulator configuration file is a text file that configures a SID simulation run. The configuration file defines the simulation contents, connections, and initial states.

� SID comes with a number of simulated components (or SID components), each of which can be modified, configured, or connected to any other independently.

� Adding new components is straightforward and does not require any modifications to SID. More info on SID Component Library, refer to the SID Component Developer’s Guide.

� While running a simulation, SID can interface with standard I/O, such as a Tk-based visual simulation monitor, the gdb debugger, and the gprof profiler.

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SID Architecture (1 of 2)SID Architecture (1 of 2)

� SID is a simulation framework for supporting embedded systems software development.

� SID features a modular architecture of loosely-coupled software components that interact with each other to simulate the behavior of physical hardware parts.

� SID components share a fixed low-level API, which defines all possible inter-component communication mechanisms.

� SID is packaged as a standalone command-line program that reads and executes a configuration file.

� A typical session with SID begins with compiling or assembling code for the simulated system to run, using standard cross-development toolchain, and proceeds through loading the target binary into the simulation environment.

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SID Architecture (2 of 2)SID Architecture (2 of 2)

� Four Component Types are supported in SID� Hardware model (hw-xxx)� Software model (sw-xxx)� Bridge (Tcl/Tk bridge)� Special function (event scheduler, host network interface, etc)

� Communication mechanisms between Components:� SID API is used to model these mechanisms:

• pin, bus, attribute, and relation

� The SID API can be thought as the socket on a circuit board. The SID Component is like the IC that plugs into these sockets and the SID simulator configuration file is like the circuit wiring that connects the sockets to each other

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SID Configuration FileSID Configuration File

� The configuration file consists of three major sections:

� A listing of component libraries to be loaded (dynamically loaded libraries)

• load

� A command to instantiate components

• new

� A set of commands that connect and configure the components

• set

• connect-pin, disconnect-pin (point-to-pint)

• connect-bus, disconnect-bus (broadcast)

• relate, unrelate

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Component Connection in SIDComponent Connection in SID

CPU

(master)

Memory

(slave)

system-mem(accessor)

data-bus(bus)

bus port

bus port

connect-bus CPU system-mem Memory data-bus

CPU

(master)

Timer

(slave)

write port

read port

connect-pin CPU out1 -> Timer in1

out1 in1

CPU

(master)

Memory

(slave)

system-mem(accessor)

data-bus(bus)

master port

slave port

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�SID Component Modeling

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#include <sidcomp.h>

#include <sidtypes.h>

#include <iostream>

using sid::component;

using sid::host_int_4;

class sp_timer : public virtual component

{

public: sp_timer();

~sp_timer() throw() {};

protected:

input_pin a, b, c;

output_pin d, e, f;

private:

in_out_handler();

}

Basic Component Outline (Class Declaration)Basic Component Outline (Class Declaration)

SID and C++ header files

Namespace using

Declare this class asSID component and use other predefined utilities

Data I/O

Inaccessible data and function

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Component Declaration (1/3)common header files & utility

Component Declaration (1/3)common header files & utility

� Header filessidattrutil.h

sidbusutil.h

sidcomp.h

sidcomputil.h

sidmiscutil.h

sidpinattrutil.h

sidpinutil.h

sidscheutil.h

sidtypes.h

sidwatchutil.h

� Tens of utilities

� For simplicity issue

using namespace sid;

using namespace sidutil

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Component Declaration (2/3) class inheritance

Component Declaration (2/3) class inheritance

class sp_timer

: public virtual component

//each component class need to inherit from this

, public fixed_attribute_map_component

//if the component provide configure attribute such as “verbose?” else use //“no_attribute_map_component”

, public fixed_pin_map_component

//if the component provide input/output pin else use “no_pin_map_component”

, public fixed_bus_component

//if the component provide bus access else use “no_bus_map_component”

, public no_relation_component

//no relation utility requirement

, public no_accessor_component

//not a bus master

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Component Declaration (3/3)Data I/O

Component Declaration (3/3)Data I/O

//input type

input_pin din_pin;

friend class callback_pin<sp_timer>;

callback_pin<sp_timer> rst_pin;

//output type

output_pin intr_pin;

//clock type (connected to scheduler)

friend class scheduler_event_subscription<sp_timer>;

scheduler_event_subscription<sp_timer> clk;

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Integrating SID Component in

AndESLive

Integrating SID Component in

AndESLiveWrapping SID component with VEP module

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�Integrating SID Component in AndESLive

Wrapping SID component with VEP module

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Integrating Component in AndESLiveIntegrating Component in AndESLive

� To integrate SID component in AndESLive, an XML-based component descriptor is created for each component. The component descriptor defines the properties to be used in AndESLive (such as bus, pin, and attributes)

� Once the user-defined component descriptor is completed, save the XML file in the folder:� $ANDESIGHT_ROOT/vep/component/user

VEP module

component

descriptor

SID

component

slave port

master port

write port read port

bus port

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Sample Component Descriptor Sample Component Descriptor

� Component Definition:

� <defcomponent name="hw-sample" shortname="sample" type="SID">

� <sid-lib dlsym="sample_component_library" name="libsample.la" />

� Bus Definition:

� <busmaster name="master" type="AHB"/>

� <busslave name="registers" type="AHB"/>

� Pin Definition:

� <defpins name="sample-out-" from="0" to="5" direction="out"/>

� <defpins name="sample-in-" from="0" to="5" direction="in"/>

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QuestionsQuestions

�We want to know how a component is modeled in AndESLive and what language/description by which the modeling is based upon?

�Where can we find the document/tutorial for modeling user-defined components and if Andes can provide modeling training/services?

�Will Andes support SystemC as a modeling constructor and what if we have SystemC models, how can we incorporate them into AndESLive?

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AnswersAnswers

�We want to know how a component is modeled in AndESLive and what language/description by which the modeling is based upon?

�Where can we find the document/tutorial for modeling user-defined components and if Andes can provide modeling training/services?

�Will Andes support SystemC as a modeling interface and what if we have SystemC models, how can we incorporate them into AndESLive?

The behavior of user-defined model can be written inC/C++ and the SID API is used to compose a SIDcomponent by which a VEP-based module is created that runs on AndESLive.

There is a document in User Manual (release 1.3.1) for

creating a user-defined model. Tutorial is also being

prepared as well as application notes. Andes can provide

modeling training and/or services based on customer

requests.

In the current release (1.3.2), SystemC modeling/import is NOT supported in AndESLive. Andes is now developing SID-SystemC bridge which can communicate SystemC interface with SID-based pin and bus. Untimed SystemC models will be supported first.

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�SystemC Modeling

�How VEP can be used in

Development CycleEnable early S/W development

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VEP Use ModelsVEP Use Models

� VEP as an Early (or pre-silicon) Software Development and Software Validation Platform� Reduce SW bring-up and system test time

� Ideally start SW dev. in parallel to HW dev.

� Leave more time for SW dev. and quality assurance

� VEP as an Architecture Exploration Platform� Evaluate HW/SW configuration and/or system partitioning

� Optimize system architecture

� VEP as a RTL Verification Platform� Golden reference models for functional verification

� Verify architecture and system validation

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VEP as Early SW Development & ValidationVEP as Early SW Development & Validation

� VEP can be used for developing & testing SW(only if the VEP can run as fast as HW board does)� Low-level device drivers and kernel� OS and middleware porting� App. SW development

� One scenario is as follows:� SW team extends existing device drivers based on updated IP

spec� At the same time, Platform team enhances/creates models (ex.

new features added) based on the VEP� SW team completely debugs and tests the driver functionality early

on the VEP� SW ‘bring-up’ in a shorter time after the HW (FPGA) is available

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Development Cycle ImpactDevelopment Cycle Impact

PlatformSpecification

Hardware DevelopmentIntegration & Bring-up Debug

SW Development (OS & Device Driver Dev, Apps Dev) Final

System Testing

Scalable Development Reducing bring-up and final system test time

Traditional (or Past) Approach:

PlatformSpecification

Hardware Development

Scalable VEP

SW DevelopmentPre-silicon

System TestIntegrationBring-upDebug

FinalSystem Testing

VEP-based Approach:

• Enable Early SW Development

• Enable Scalable Development

• Pre-Silicon System Test

• Reduce Bring-up time

• Reduce Post-Silicon System Test

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VEP as Architecture ExplorationVEP as Architecture Exploration

� VEP can be used to explore design alternatives to determine the appropriate architecture (or system)

� Some alternatives to evaluate are:� AndesCore configuration

• Cache, MMU, Local memory, branch prediction, etc

� SW profiling (in AndESLive) • code optimization

� HW/SW partitioning• HW accelerator engine or SW oriented

• Performance and cost tradeoff

� Bus Matrix or Multi-layer • currently NOT supported in AndESLive

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VEP as RTL VerificationVEP as RTL Verification

� Currently NOT supported in AndESLive!

� Team-up Partnership possibilities� GUC (porting AndesCore ISS with SystemC TLM2.0)

� EVE (compiling AndesCore on ZeBu)

� CoWare (porting AndesCore ISS with SystemC/AMBA)

� Carbon (porting AndesCore ISS with CASI/SystemC)

� Cadence/Synopsys/Mentor…

� Speed is always an important concern and incentive� Transaction-based interface is the key

� HW accelerator/emulator may be too expensive to be justified

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Thank You!!!Thank You!!!

Integrated Development Environment - National Chiao Tung...

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