Roll-to-Roll Processing Inflections for the Display & IoT Industry

Neil A. Morrison, Applied Materials Web Coating GmbH, Siemensstrasse 100, 63755, Alzenau, Germany

ABSTRACT

Next generation consumer electronic devices, including wearables are placing an ever increasing emphasis on form factor. This has resulted in an increase in the number of polymeric films used in their construction. As most of these polymeric materials are initially manufactured in the form of a roll, there has been a drive towards the utilization of so called roll-to-roll processing (R2R) in order to reduce both manufacturing line setup, cleanroom and materials costs. The work presented in this paper will summarize Applied Materials development activities for next generation large area flexible electronics applications. Focus will be given on large area deposition of silicon based layer systems using a front surface contact free R2R CVD processing platform for barrier applications. Further developments will also be discussed in terms of infrastructure & process development for patterning of micron level features and devices.

1 Introduction

The interest in wearable and internet connected devices has exploded in recent years. Most of these new devices are focussed on applications driven by form factor (e.g. shape, size, weight and robustness), include communications, sport and fitness, fashion, navigation, long distance health monitoring, sensing, tracking and labelling devices. This has necessitated the use of increased levels of polymeric substrates in their construction, most of which are originally produced in the form of a roll. As such, roll-to-roll (R2R) processing provides an ideal path towards high throughput, low cost manufacturing of some of the components used. R2R processing can be considered as a batch based inline processing technology where km long substrates can be coated, patterned or etched either in vacuum or under atmospheric conditions [1, 2]. In its simplest embodiment, a R2R processing tool consists of an unwinder, a process module and a re-winder. Within such a tool, the uniformity is optimized in a single dimension only, thereby simplifying its design. As the process is continuous, the utilized process and substrate materials are more efficiently utilized when compared with traditional batch based sheet to sheet (S2S) and wafer systems. Significant demands exist in terms of winding different types and thicknesses of substrate within the same production tool. The tension applied to the substrate during winding (transport) may dramatically differ depending upon the tensile yield, substrate temperature and substrate thickness. Consequently, these R2R tools are equipped with online tension measurement and control systems to ensure stable substrate transport through the process zone. Mechanical contact between both transport and tension rollers and the coated substrate is also intentionally minimized or eliminated if possible, in order to reduce the risk of both scratch formation and particulate inclusion. As R2R systems process substrates continuously over long time periods, accurate process monitoring and control systems are required for quality and yield optimization. R2R processing is currently used in the manufacture of two critical components in todays’ wearable consumer electronic devices, namely the touch panel and the moisture barrier for both electrophoretic and OLED based displays. Active transistor manufacture has only been demonstrated at pilot production level as yield management strategies are still under optimization. Nevertheless, R2R transistor processing provides an excellent path for ultra-low cost manufacture of the electrophoretic display backplanes [1] used in wearables and for both near field communication (NFC) and general Internet of Things (IOT) based sensors with low

transistor counts and density. Rapid adoption of NFC in smart labelling, functional packaging and anti-counterfeit devices in particular is expected within the next 3–5 years. This paper therefore focusses on the evolution of the key R2R processing technologies enabling some of these wearable and IOT based product innovations.

2 Experimental

2.1 Touch panel manufacturing using R2R PVD

2.1.1 Key touch panel stack requirements

The optical performance of a touch sensor can be characterized by its light transmission over the visible spectrum, its color both in transmission and reflection and the extent to which ambient light reflection can be suppressed particularly in outdoor reading environments. As such, both the touch sensors internal reflection and integration scheme within the final product are of extreme importance. The internal reflection component is typically addressed by depositing an index matching (contrast matching) layer stack between the substrate and the Indium Tin Oxide (ITO) transparent conductive layer in order to ensure that no difference in optical performance is observed when overlaying patterned y and x drive and sense electrode array’s. The invisible ITO sheet resistance ultimately impacts the touch sensor RC delay. As such, there is an increased necessity to reduce the ITO resistivity especially when the diagonal dimensions of the touch sensor are increased.

2.1.2 R2R PVD processing for “Invisible ITO” stacks

Film based touch panels are manufactured through the sputter deposition of a thin SiO2 layer on top of a PET substrate, prior to the deposition of a high refractive index oxide layer (typically either NbOx or TiO2), a low refractive index layer (SiO2) and a low temperature ITO layer using a vacuum based R2R PVD tool (e.g. Applied Materials SmartWeb® XL, see Fig. 1) [2]. Each process module is equipped with high rate rotatable cathodes in separately pumped process compartments. The number of process modules required is determined by a combination of the layer stack structure and the desired tool productivity. The standard SmartWeb® platform employs a tempered coating drum to accurately control the substrate temperature and planarity within the coating zone. This configuration also has the advantage of permitting the use of a very small gap between the coating drum/substrate and the chamber separation walls resulting in pressure separation (greater than 2 orders of magnitude) between individual process compartments in each process module. As the PET substrates typically used in device manufacture have a glass transition temperature around 80 °C the substrate temperature increase associated with the utilized process power must be balanced against the cooling provided by the coating drum.

FIGURE 1: SmartWeb® R2R PVD architecture.

2.2 R2R barrier film manufacture using CVD

2.2.1 Barrier technology for display applications

High density inorganic layers are used in barrier films for electrophoretic, quantum dot enhanced and OLED display applications. The deposition technologies utilized must be compatible with low deposition temperatures (<110 oC) as many of the materials of construction within these displays are sensitive to thermal, UV or ion bombardment based degradation [4]. Semi-crystalline heat stabilized substrates are often used as a consequence of their relatively high glass transition temperature, low coefficient of thermal expansion, low shrinkage and high solvent resistance. These substrates can also be commercially obtained with planarization layers at the surface, reducing the barrier layer defect density and hence enhancing barrier performance [3]. Both PVD and CVD processes are commonly used for high density barrier layer production, but require markedly different defect mitigation strategies to ensure the requisite balance between performance and cost. Typically, sputtered SiOx, SiNx, AlOx and TiOx layers are produced using a reactive mid-frequency process using “metallic” targets. Particle and molten droplet contamination during thin film processing represents a major source of yield reduction in barrier production [5]. One further disadvantage of PVD is its inherent line of sight deposition capability. Small asperities either directly on the substrate surface, arising from substrate slitting, or as a consequence of arcing during processing cannot be conformally covered. As such, small pinholes in the deposited layer are typically observed and the barrier performance deviates from that, what is expected when considering only the bulk layer material. PECVD however is a deposition technology that overcomes these issues. Dense SiNx layers can be deposited under process conditions utilizing moderate to high levels of ion bombardment with the same type of Silane chemistry used for gate dielectric deposition for TFT’s. Low pressure processing is typically utilized to ensure the ion content in the deposition flux is sufficient to reduce

the overall hydrogen content of the layer and eliminate weakly bound SiH2 and NH2 moieties within the film. The ion bombardment also has the advantage of increasing the adsorbate mobility and enhances the layer conformality over defects or asperities on the substrate surface itself. Particulates generated during deposition are small and more widely spaced than observed in PVD with radii and densities more typically of the order of approximately 0.5 µm and in the tens of defects per mm2 range respectively [6]. Defect control in barrier processing is of vital importance as the influence of the low diffusivity dense inorganic layer can significantly be offset by the presence and spatial density of cracks and pinholes in the layer. Consequently, mitigation strategies often employ the use of multilayer structures where the dense, inorganic layers are separated by planarizing organic/polymeric layers. The barrier performance of the organic itself is low, typically of the same order of magnitude as the substrate, but the multilayer structure forces water vapour or oxygen to move laterally after penetration through a crack or pinhole to the next available permeation channel in the subsequent inorganic layer rather than travel vertically through the stack. This so-called “tortuous path” approach therefore permits defect decoupling from the final barrier performance. From a practical and economic perspective, the organic/polymer layer is rarely processed under vacuum conditions in combination with PVD. Typically, this layer is applied using an atmospheric slot die coater. However, the necessity of bringing the substrate in and out of vacuum in addition to the complex fluid rheology of the organic, make defect mitigation more complex and confirm the necessity to work in a clean room. These multilayer systems can however be directly deposited using CVD. Following deposition of the barrier quality SiNx layer, an organic layer is deposited using non-Silane based chemistry in either a so-called “plasma polymerization” or “initiated CVD” mode [7, 8]. This involves either the polymerization of a siloxane monomer (e.g. HMDSO) using a plasma or the thermal activation of a gas phase chemical initiator, prior to reaction with semi-organic monomer species at the substrate surface. The surface reactivity is controlled primarily by the dissociated initiator concentration, the partial pressure of the monomer and the substrate temperature and permits tuning of the process between conformal growth and planarizing growth structures. Under optimized conditions, the level of planarization is appropriate for underlying nitride defect mitigation via pore filling, thereby preventing the nucleation of through-layer nodule shaped defects. Furthermore, an additional advantage of these CVD processes is the ability to deposit these decoupling or “buffer” layers in an optically transparent, mechanically resilient form. Optimized barrier performance can therefore be achieved by using a layer thickness large enough to embed and bury defects whilst thin enough to ensure maximized optical transmission and colour neutrality in combination with two SiNx barrier layers. The R2R CVD production platform developed by Applied Materials is shown in Fig. 2. Up to five high rate linear plasma deposition sources are arranged around a tempered coating drum in separately pumped process compartments. The winding path of this platform has further been optimized to ensure both complete elimination of front surface roller contact and minimized backside contact to reduce defect creation arising from substrate conveyance. Process based particle control is also enabled by confining the plasma to the deposition zone and by rigorous fluid dynamic optimization ensuring laminar gas flow, uniform pressure distribution and no dead or recirculation zones within deposition zone itself. The linear plasma sources are themselves excited at frequencies greater than 13.56 MHz to ensure efficient power coupling to the plasma and low thermal budget, high quality inorganic layer processing. Liquid precursor handling capability also permits the deposition of multilayer structures utilizing the kind of buffer layer described previously. Further uptime advantages can also be obtained by using fluorinated gases for in-situ plasma cleans to remove side-wall deposits eliminating the need to open the tool to the atmosphere for cleaning and maintenance at the end of each roll.

2.3 R2R Thin Film Transistor Manufacture

2.2.3 Patterning Technology for Device Applications

Thin film transistors (TFT’s) provide the basis for the integrated circuits used to switch pixels in an electrophoretic display or for the logic used in both NFC and IOT sensor devices on flexible substrate materials for smart labels, functional packaging and stick on ambient sense devices. However, key to rapid adoption and proliferation of these technologies is their low cost manufacture on cheap, conventionally available lightweight and flexible substrate materials. Printed devices utilizing organic semiconductors have been demonstrated [9–10]. However, their performance level lags behind traditional devices manufactured with either amorphous silicon or amorphous metal oxide based semiconductors. Vacuum based R2R PVD, CVD and etch technologies are now being developed to meet the layer quality and defectivity requirements of this industry [1]. Nevertheless, the key challenge remains in terms of low cost, high throughput device patterning. Whilst photolithographic processing within a R2R environment has been successfully demonstrated in step and repeat form, its principal difficulty lies in obtaining high resolution pattern alignment due to changes in substrate size and shape between each individual high temperature process step. Substrate bowing due to layer stress also further reduces the degree of accuracy.

FIGURE 2: Applied Materials R2R CVD tool.

FIGURE 3: Imprint lithography used for R2R patterning.

As a result the TFT design rules on polymeric substrates are commonly such that devices must be manufactured with a size double that of those on rigid glass substrates. Recent advances have however been made in terms of the implementation of an imprint lithography step within R2R TFT backplane manufacture [1, 4, 10]. Imprint lithography can be used to create multilevel patterns on a continuously moving flexible substrate at speeds commensurate with other processing steps required for flexible backplane fabrication as shown in Fig. 3. A single, monolithic, three-dimensional mask is formed through mechanical contact with an imprint stamp and a fast curing photoresist. This multilevel mask effectively serves as a template for subsequent wet and dry based etching steps thereby eliminating the layer to layer alignment issues encountered with the photolithographic patterning of coated polymeric substrate materials. Coplanar, rather than traditional top or bottom gate device architectures are required to take full advantage of imprint lithographic patterning techniques. Mastering for imprint lithography involves the use of a scalable direct write laser process to create a greyscale image in a photoresist applied to a silicon wafer or glass substrate. This substrate is then dry etched to transfer the image and resultant three-dimensional topology directly to the silicon or glass thereby creating the so-called mold “master” before casting and curing a Polydimethylsiloxane (PDMS) stamp. Typically, the stamp is peeled from the master and bonded to an imprint cylinder used to pattern the flexible substrate and the master re-used to create further low cost stamp cylinder sleeves. Typical imprint stamp lifetimes are of the order of 1000 impressions. As such, the imprint cylinder diameter remains a critical parameter in determining the maximum processing length before stamp exchange is required. Imprinting defects result primarily from particulates and can be controlled through the use of appropriate substrate cleaning and clean room technologies prior to processing. Substrate hygiene in particular reduces so-called “tenting defects” which arise as a consequence of a difference in photoresist thickness around the particle. At a device level, this typically results in the formation of an electrical short around the data or gate lines, hold capacitor or the TFT itself manifested in either pixel, row or column loss. Direct stamp wear will also result in deviations in imprinted resist thickness and hence patterned layer stack structure. However, in-situ optical metrology and data processing can be used to directly monitor and flag stamp erosion issues as and when they arise. One further advantage of

imprint lithography is that as each of the layers required for device fabrication is deposited in blanket form prior to patterning, both the total number of process steps and the subsequent sensitivity to particulates is significantly reduced. Under comparable yield conditions this results in around a 50 % reduction in manufacturing cost, compared to flexible TFT backplanes processed using bond-debond methods, photolithography and traditional backplane architectures. However, when considering almost a 50% reduction in number of process steps on moving towards a co-planar device architecture patterned with imprint lithography the true yielded cost saving may be higher.

3 Results and Discussion

3.1 Touch Panel Manufacture Using R2R PVD

3.1.1 ”Invisible ITO” Touch Panel Stack Performance

For high durability devices, crystalline ITO films are only produced by performing a post deposition anneal on a pre-cut work-piece prior to final device manufacture. These films, in contrast to those deposited at higher temperatures on rigid glass substrates using ITO 90:10 (wt. %), were therefore deposited with ITO compositions employing higher concentrations of Indium Oxide. Fine stoichiometric variation of the indium/ tin oxide ratio fundamentally results in the control of the density and spatial distribution of both oxygen vacancies and Sn4+ dopants in the deposited film in addition to the onset temperature for crystallization. This was further modulated by adding small concentrations of hydrogen to the process gas environment. State of the art post annealed index matched ITO stacks on PET based were demonstrated with total transmission levels above 90% and sheet resistance levels of approximately 100 Ohm/square, corresponding to ITO resistivities of approximately 210 µΩ cm. These stacks were also found to be colour neutral and exhibited almost no difference in optical performance both before and after sensor patterning (as shown in Fig. 4). Post patterning crystallization was also required to ensure smooth sensor line edge formation whilst simultaneously controlling dopant activation. As deposited, low temperature ITO contains small nano-crystalline domains as a consequence of the semi-energetic nature of the deposition flux in low pressure PVD. These regions were spaced sufficiently far apart to result in lateral crystallite growth at anneal temperatures > 150 oC.

3.2 R2R Barrier Film Manufacture Using CVD

3.2.1 SiNx Performance and Process Stability

Single layer silicon nitride has been deposited on both PEN and PET substrate materials with barrier performance levels for water vapour ≤ 5 × 10–3 g/ m2day (measured using an Aquatran 2 permeation unit under 40oC/100 % RH conditions) for thickness between approximately 140 – 200 nm at substrate temperatures < 110 oC (Fig. 5). This correlates to levels ≤ 5 × 10–4 g/m2 day at ambient conditions (20 oC/50 % RH) providing the required building block for preparation of a high performance barrier stack. Excellent levels of process stability have also been demonstrated. Continuous SiNx deposition on PET for periods up to 5 hours showed less than a ≤ 1 % variation in optical layer thickness following inline measurement of the optical reflectance spectrum. This is within the measurement accuracy error limits of the inline reflection tool.

FIGURE 4: Optical characteristics of invisible ITO.

3.2.2 Multilayer Performance

A multilayer system incorporating two SiNx layers sandwiching a plasma polymerized HMDSO layer (ppHMDSO) with thickness ratios 1:2:1 was deposited on both PEN & PET substrates for subsequent integration with a display. Defect averaged barrier performance levels of approximately 7 × 10–5 g/m2day were obtained under 40 oC/100 % RH conditions (representing ambient performance levels of approximately 7 × 10–6 g/m2day) approaching the requirement for OLED of ≤ 1 × 10–6 g/ m2day. Both the intrinsic SiNx barrier performance and the substrate cleanliness however must be improved if the OLED requirements for barrier film are to be fully met.

3.2 R2R Thin Film Transistor Manufacture

3.2.1 TFT’s on Flexible Polyimide Substrates

Amorphous Silicon flexible TFT backplanes were manufactured on 50 µm thick polyimide substrates using R2R PVD for the gate and source/drain metallization and R2R CVD for the silicon based layers utilized in the device. Aluminum (100 nm) was used as a gate metal in order to increase the chemical selectivity of the wet etch process between the gate and the 100 nm chromium source/drain electrodes. Following gate metal sputtering, the CVD stack was deposited as follows. Firstly a 100 nm SiO2 etch stop layer was deposited using a SiH4/N2O plasma. This was immediately followed by a 200 nm SiNx layer, an 80 nm thick a-Si layer and a 30 nm thick n-type microcrystalline silicon layer. The 100 nm thick chromium source/drain layer was sputtered under conditions designed to balance

the layer stress from the previous PVD and CVD processes. Thereafter, the roll was coated with a soft photoresist and softly imprinted (imparting the desired mask topology) before being hardened upon illumination with UV light (Fig. 3). The patterning phase was completed through the use of a series of wet and dry R2R etch steps before TFT array isolation and testing. A typical device characteristic is shown in Figure 8. As the gate voltage was increased, more charge carriers were accelerated through the channel material leading to an initial, sharp, increase in drain current before saturation. The saturation in drain current at high gate voltages is fundamentally associated with the conductivity of the channel layer. This current, or on-current, was typically of the order of 1 × 10–5 A at gate voltages of approximately 20 V, primarily due to the good ohmic contact provided between the source/drain contacts and the amorphous silicon channel layer brought about by the highly conductive microcrystalline silicon n+ layer. The resulting on/off current ratios were > 108. Analysis of the field effect mobility in the linear regime of the TFT characteristic, where VG > VSD, also indicate high mobilities of the order of 0.95 cm2/Vs. This level is more than sufficient for active matrix electrophoretic display applications, NFC’s and simple IOT sensor based devices.

4 Conclusions

Current advances in high temperature substrate technology, coupled with improvements in both R2R deposition/ etch equipment and lithographic patterning are paving the way for the cost effective manufacture of next generation wearable and IOT enabled devices. Touch panel manufacture has already made the transition to full R2R manufacturing with major improvements in both substrate and ITO performance resulting in mainstream implementation in smartwatch, smartphone, Tablet and Ultrabook devices. ITO resistivities following annealing were of the order of 210 µΩ cm enabling the preparation of 100 Ω/square devices with an optical transmission of approximately 90 %. Barrier film technology development has also undergone significant resurgence in order to meet the aggressive cost and performance targets set by the display industry. CVD barrier film deposition has been shown to overcome the limitations presented by traditional sputtered layer stacks using technology and process recipes more traditionally utilized in the display and semiconductor industries. Finally, the technical feasibility of R2R TFT fabrication has clearly been demonstrated both for the next generation of flexible electrophoretic displays and for the logic used in NFC and IOT sensor devices for smart labels, functional packaging and stick on ambient sense devices.

FIGURE 5: WVTR performance for 200 nm SiNx on PEN.

FIGURE 6: WVTR performance for a multilayer on PEN.

FIGURE 7: Backplane imprinted photoresist prior to etch.

FIGURE 8: Typical R2R a-Si TFT device characteristics.

Acknowledgements

The author would like to thank Tobias Stolley, Fabio Pieralisi, Gerhard Steiniger, Uwe Hermanns, Thomas Deppisch, Armin Reus, Jens Degenhardt, Max Diez, Carl Taussig, John Maltabes, HanJun Kim, Rich Elder, Randy Hoffman, Edward Holland, Albert Jeans, Mark Smith, Warren Jackson and Alejandro de la Fuente Vornbrock for their help and collaboration for the aforementioned barrier, touch panel and TFT development work.

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