The control for the 500MHz superconductivity cavity test system

Rihua ZengRihua Zeng22 June 2010

OutlineOutline

• 1. The phase and amplitude feedback loops for the horizontal test of the cavity

• 2. The DAQ and Interlock for High Power Test System

• 3. The simulation of Components and HOMs

1. The phase and amplitude feedback loops f h h i l f h ifor the horizontal test of the cavity

The Phase and Amplitude Feedback Loops

The Phase and Amplitude Feedback Loops  Setup

The noise source in the system

Clock JitterPhase error due to the clock jitter during the ADC sampling. IF

o ft ⋅Δ⋅=Δ 360ϕ

ADC  quantization noise.  For a 12bit resolution ADC(ENOB, about 11 bit, SNR 68 dB),  the introduced phase error is about 0 02°error is about 0.02

The phase noise of DDS(direct digital synthesis)( from truncating error of the Phase Accumulator DAC quantization and non‐ideal( from truncating  error of the Phase Accumulator, DAC quantization and non ideal characteristics, and clock jitter). 

The nonlinearity of the mixer, amplifier and other components in analogue front end(spurious harmonics)

The Way to Suppress the Noise and suprious

In the phase and amplitude feedback control System，the methods to suppress the noise were investigated：noise were investigated：

1. SAW Filters used to suppress the suprious and harmonics in spectrum

2. The phase and amplitude detection based on non-IQ deep oversampling

3. Carefully adjust the PI gains to suppress the noise in the systemy j g pp y

4. Lower the frequency of DDS output signal to lower the phase noise

The  SAW(Surface Acoustic Wave ) filters 

To achieve the RF field stability in phase 0.1°and amplitude 0.1%, require the SNR 60dB.For 0.01°and 0.01%, require the SNR 80 dB.

SAW filters with good perfomance are taken in our system to get a good suppress to the spurious emerged in our  special   analog front end.  The PCB board to amout the filters are designed and get a good circuit match.

The suppress to the signal out of band achieved 40dB for single filter and 70 dB for 2‐fiter used in series together.

The SAW Filters used in LO generation Module

Add  one SAW filter

Spectrum in  a short span 

Add another filter

声表面滤波器在本振信号产生模块中的应用

Add one filter Add  another filter The final LO signal

The Phase Noise of LO signal

Compared with the signal output directly from signal source with the same frequency

The final LO signal Signal from the signal source

SAW filters used in Clock generation module

Add  one filter Add  another filter

The Clock phase noise and jitter

The final clock signal The signal form signal source

The jitter of the final clock

中频频率/MHz 1.00 10.00 20.00 30.00 40.00 50.00

相位误差/deg 0 007 0 072 0 144 0 216 0 288 0 360相位误差/deg. 0.007 0.072 0.144 0.216 0.288 0.360

The relationship between the phase error and IF frequency due to a clock jitter of 20ps

Phase and Amplitude Based on Non-IQ Deep Oversampling

IQ sampling and non-IQ samplling

)log(1076.102.6f

NSNR s++=

Oversampling, the sampling frequency 2 times large than the BW of IF signal

)2

g(BW

For our 500MHz CW mode RF system, we took the 100MHz ADC clock, and the IF frequency 1MHz. The fs/fIF is 100 far from the IQ sampling. And deep oversampling improved the SNR by 17dB(assume the BW of IF is 1MHz)17dB(assume the BW of IF is 1MHz)

PI Gain Adjust in Feedback LoopsPI control was simulated in Matlab firstly  to understand the effect of PI gains on the system noise suppression

The Effect of Proportional Gain Kp

As Kp Increase, the suppression to the noise is more. And the rise time of the output response is shorter p

（左）KP=20 （右）KP=100

The Effect of Proportional Gain Kp

But if the Gain increase more, the output oscillate at some level,  bring instability 

（左）KP=5000 （右）KP=100000

The Effect of Integral Gain Ki

The Ki is used to eliminate the steady‐state error, has a little contribution to the noise suppression but bring big rise time. And also bring instability if Ki too large

（左）KI=100 （右）KI=10000右

（左）KI=10^6 （右）KI=10^8

The phase and amplitude loops simulation

The above is the simplified loop simulation. For the real loops, the situation is more complicated

The simulation of phase and amplitude loops

The output without PI gains optimized The output with PI gains optimized

The Phase&Amplitude modulation based on DDS

The phase noise of DDS output signal is lower as the output frequency lower.The phase noise of DDS output signal is lower as the output frequency lower. 

DDS output：31.5MHz DDS output：10MHz

But the DDS output cannot too low due to the limitation of SAW filter’s band in modulation module

The Phase and Amplitude at DDS output 4MHz

The phase and amplitude at DDS output 2MHz

The Effect of DDS Output Frequency

DDS频率

相位5MHz 7MHz 8MHz 10MHz

均方差(deg.) 0.082 0.098 0.110 0.133

最大值(deg.) -172.270 -172.267 -172.201 -172.097

最小值(deg ) -172 976 -172 982 -173 093 -173 104最小值(deg.) 172.976 172.982 173.093 173.104

The Detection Result of Phase and Amplitude(open loop)

In 30 minutes, The phase data peak to peak±0.04°，amplitude±0.1%。

In 30 minutes, the difference between the two channel, Phase date peak to peak ±0.02°

Phase and Amplitude Stability (Close loop)

Close loop, one hour, phase stability peak to peak ±0.25°amplitude ±0.3%

Closed loop phase data in one hour

Closed loop amplitude data in one hour

Open loop to Close loopp p p

Open loop the phase is modulated by a electrical phase shifterOpen loop, the phase is modulated by a electrical phase shifter

Closed loop in the case of phase modulated by phase shifter

2. The DAQ and Interlock for High Power gTest System

HOMs absorber low power testing and the result shows that the absorber has the good absorb performance for HOMs near 1GHz which are the dangerous mode of 500MHz cavity.

Flow diagram of the data acquisition

Data acquisition via GPIB for HOMs absorber Low power test

Data acquisition and interlock of High power test

A DAQ board PCI-1716 with 250KS/s16 bit AD is employed to perform the data acquisition, which has 16 analog input channels. The Vacuum, temperature, forward power and reflected power signal are recorded and displayed. These signal are also monitored in interlock system to cut off the RF signal in time to protect the key component.

Input coupler High power Test block diagram HOMs absorber High power Test block diagram

Data acquisition for high power test Interlock for high power test

High Power Test Setup and Results

High power test for the primarily developed HOMs absorber are done and the absorber power reached 4.5kW (without damage). The power input coupler test and conditioning are underway. DAQ and interlock are work successfully in these tests.

HOMs absorber high power test

Power input coupler high power test

3. The simulation of Components and HOMs

Transitions components simulation for High Power Test

HOMs simulation for 9-cell cavity

Cavity of Tesla shape HOMs calculations in HFSS

Cavity of Ichiro shape HOMs simulation

f (GHz) G(Ω) R/Q(Ω) Phas(°)

1.2803 280.50 0.0058 19.89

1.2821 280.90 0.0087 40.23

1.2847 281.57 0.0546 61.35

1.2880 282.35 0.0259 80.20

1.2914 283.21 0.1636 100.41

1.2947 284.00 0.0392 120.32

1.2974 284.72 0.3863 141.10

1.2992 285.19 0.0880 160.01

1.2998 284.50 584.5404 172.87

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40Dis tance [meter]

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

Abs

Ez

Ansoft Corporation HFSSDesign1XY Plot 1Curve Info

AbsEzSetup1 : LastAdaptive

convergence

values calculated by scripts (monopole)

1.28

1.29

1.29

1.30

1.30

1.31

20 40 61 80 100 120 141 160 173

HOMs simulation for 9-cell cavity

Scripts to automatically calculate the mode parameters

HOMs simulation for 9-cell cavity

Practical work for high power test System

The power input coupler and the HOMs absorber are developed in IHEP for spare 500MHz cavity and a high power test stand is constructed to perform the test and conditioning.

Test bench construction and HOMs absorber investigation

Components for multi-cell cavity in IHEP

The 9-cell cavity is under fabrication and a lot of work are carried out in IHEP. It’s a good chance to get more practical excise and learn effectively from specific project.

Th k f Att ti !Thanks for your Attention!

AppendixI.PDFAppendix I The works During PhD Study Period幻灯片编号 2幻灯片编号 3幻灯片编号 4幻灯片编号 5幻灯片编号 6幻灯片编号 7幻灯片编号 8幻灯片编号 9幻灯片编号 10幻灯片编号 112.Practical work for high power test and HOMs investigation and simulation幻灯片编号 13HOMs simulation for 9-cell cavityCavity of Ichiro shape HOMs simulation Scripts to automatically calculate the mode parametersComponents for multi-cell cavity in IHEP