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K. Yau and A. Ito

Broadcom Corporation

December 9, 2015

RF VARACTOR MODELING

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Motivation

RF Modeling of 3D FinFET Varactors

Experimental Validation

Small-signal RF Validation

Large-signal Validation

Summary

OUTLINE

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MOS scaling resulted in 3D non-planar technologies to control short channel effects

Passive elements such as varactors are non-planar

An accurate RF model for 3D varactors is needed to enable RF and high-speed digital designs

MOTIVATION

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RF 3D MOS VARACTOR MODEL

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MOS varactor device structure same as FET

Except NMOS in NWELL or PMOS in PWELL

Varactor is a 3D device

Multiple FINs to increase capacitance density/area

FIN geometry (𝒉, 𝒕) are fixed process parameters

3D MOS Varactor

X-section

N-well

Gate Well contact

Gate

Oxide

P-sub

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3D MOSVAR MODELING METHODOLOGY

Leverage CMC standard MOSVAR model

Surface potential based approach

VA code can be downloaded: https://www.si2.org/cmc_index.php

Built into most SPICE simulators

Well known parameter extraction methods

Sub-circuit elements to model parasitics

Rg: gate resistance

Rcont: well contact resistance

Dnw: n-well to p-sub diode

Rsub, Csub: substrate network

Ig: gate leakage current

MOSVAR

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Adapt MOSVAR for planar devices to 3D geometry

Most parameters retain original meaning

W replaced by effective W of “flatted” device

MOSVAR MODEL FOR 3D VARACTORS

MOSAVAR 3D Varactor

𝑇𝑂𝑋 𝑇𝑂𝑋𝑒𝑓𝑓

𝜖𝑜𝑥 𝜖𝑆𝑖𝑂2

𝐿𝑔 𝐿𝑔

𝑤𝑒𝑓𝑓,𝑓 = 𝑁𝐹𝐼𝑁 × 2ℎ + 𝑡

𝑊 𝑊𝑡𝑜𝑡𝑎𝑙 = 𝑁𝐹 × 𝑤𝑒𝑓𝑓,𝑓

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1. Calculate capacitance from measured S-parameters

2. Set TOX to the effective TOX of the semiconductor process

3. Extract CFRL, CFRW, DLQ, DWQ from capacitance data of different geometry, with 𝑾 =𝑾𝒕𝒐𝒕𝒂𝒍[1]

4. Determine NSUB and VFB from 𝑪 𝑽 characteristics from accumulation to depletion

PARAMETER EXTRACTION FLOW

𝑪 = −𝟏

𝝎ℑ

𝟏

𝒚𝟏𝟐

−𝟏

[1] Z. Zhu et. al. “Improved Parameter Extraction Procedure for PSP-Based MOS Varactor Model,” IEEE ICMTS 2009

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5. Extract resistive parasitics

PARAMETER EXTRACTION METHODOLOGY

𝑅𝑔 = ℜ ℎ11 = 𝑅𝑔𝑐𝑜𝑛𝑡 +1

3

𝑊𝑜𝑑

𝐿𝑅𝑔𝑠ℎ 𝑅𝑠𝑑𝑐𝑜𝑛 = ℜ

1

𝑦22=𝑅𝑣𝑖𝑎𝑁𝑣𝑖𝑎

+ 𝑅𝑠𝑑𝑐𝑜𝑛′ /𝑊𝑡𝑜𝑡𝑎𝑙

𝑊𝑜𝑑

𝑅𝑔𝑐𝑜𝑛𝑡

𝑅𝑠𝑑𝑐𝑜𝑛𝑡

Non-scalable portion Width-scalable portion Slightly different scaling characteristics

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6. Extract UAC and RSHS from quality factor in accumulation mode and depletion mode

7. Add n-well to p-sub diode and substrate network

8. Add gate leakage current, 𝑰𝒈𝒂𝒕𝒆

PARAMETER EXTRACTION METHODOLOGY

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SMALL SIGNAL VALIDATION

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C(V) CHARACTERISTICS

Fixed L = 72 nm Fixed NFIN = 10

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DERIVATIVE OF C(V)

L = 240 nm L = 72 nm

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QUALITY FACTOR

L = 240 nm L = 72 nm

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LARGE SIGNAL VALIDATION

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Model is extracted from small-signal C(V) data

Varactors are often used in large-signal conditions, e.g., VCO tank circuit

Leeson’s phase noise formula

WHY LARGE SIGNAL VALIDATION

𝐿 Δ𝜔 = 10 log2𝐹𝑘𝑇

𝑃𝑠𝑖𝑔1 +

𝜔0

2𝑄Δ𝜔

2

1 +

Δ𝜔 1𝑓3

Δ𝜔

Need to validate model under large-signal conditions

Measure and compare time-domain 𝑣 𝑡 and 𝑖 𝑡

~kHz range, 𝑣 𝑡 and 𝑖(𝑡) can be directly measured

~GHz range, 𝑣 𝑡 and 𝑖 𝑡 reconstructed from measured X-parameters via harmonic balance simulations

Model card is extracted from small-signal data

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LARGE SIGNAL VALIDATION

Amplitude 0.8V / 1.6 Vpp

Frequency 500 kHz

L 0.24 µm

𝑽𝒈𝒃 (dc) 0 V

Amplitude 0.6V / 1.2 Vpp

Frequency 500 kHz

L 0.24 µm

𝑽𝒈𝒃 (dc) 0 V

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LARGE SIGNAL VALIDATION

Amplitude 0.5V / 1 Vpp

Frequency 500 kHz

L 0.24 µm

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LARGE SIGNAL VALIDATION

Amplitude 0.5V / 1 Vpp

Frequency 500 kHz

L 0.24 µm

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LARGE SIGNAL VALIDATION

Amplitude 0.355 V / 0.71 Vpp

Frequency 1 GHz

𝑽𝒈𝒃 (dc) 0 V

Amplitude 1.122 V / 2.244Vpp

Frequency 1 GHz

𝑽𝒈𝒃 (dc) 0 V

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CMC standard MOSVAR model adapted to model 3D FinFET varactors

VA code: https://www.si2.org/cmc_index.php

Defined a new effective finger width of 3D device as 𝒘𝒆𝒇𝒇,𝒇 = 𝑵𝑭𝑰𝑵 × 𝟐𝒉 + 𝒕 , where 𝒉

and 𝒕 are FIN height and thickness, respectively

Model is scalable and extracted from small-signal S-parameter data.

Good matching RF characteristics including Q is observed up to 70 GHz for different geometry

Using the same small-signal model, the large-signal behavior can be simulated accurately.

SUMMARY