Graphene Barristor, a TriodeDevice with a Gate-ControlledSchottky BarrierHeejun Yang,1* Jinseong Heo,1* Seongjun Park,1 Hyun Jae Song,1 David H. Seo,1

Kyung-Eun Byun,1 Philip Kim,2 InKyeong Yoo,1 Hyun-Jong Chung,1† Kinam Kim3

Despite several years of research into graphene electronics, sufficient on/off current ratio Ion/Ioff ingraphene transistors with conventional device structures has been impossible to obtain. We report on athree-terminal active device, a graphene variable-barrier “barristor” (GB), in which the key is anatomically sharp interface between graphene and hydrogenated silicon. Large modulation on the devicecurrent (on/off ratio of 105) is achieved by adjusting the gate voltage to control the graphene-siliconSchottky barrier. The absence of Fermi-level pinning at the interface allows the barrier’s height to betuned to 0.2 electron volt by adjusting graphene’s work function, which results in large shifts of diodethreshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementaryp- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

The triode, composed of a diode and a gridin a vacuum tube, was the first three-terminal active device that had been used

to amplify and to switch electric signals, whichled to the technical innovations for modern elec-tronics in the early 20th century (1). Solid-statetransistors and integrated circuits (ICs) basedon silicon were more practical for complicatedlogic circuits and thus replaced triodes. Althoughsilicon transistors have continued to improvetheir speed and integration density, they nownear the potential limit where further reductionof channel length causes inevitable leakage cur-rents (2). To present an alternative route for over-coming these challenges, we introduce a classof three-terminal devices based on a graphene-silicon hybrid device that mimics a triode op-eration. The key device function takes place atthe electrostatically gated graphene/silicon in-terface where a tunable Schottky barrier con-trols charge transport across a vertically stackedstructure. We named this barrier variable device,which is a solid-state descendant of the triode,“barristor.”

Graphene is a zero-gap semiconductor whoseFermi energy can be adjusted by electrostatic gatingowing to its two-dimensional (2D) nature (3–5).Because graphene is metallic at a sufficientlylarge Fermi energy, a Schottky barrier (SB) formsat the interface between the doped graphene andthe semiconductor (6–10). However, SB betweengraphene and a well-controlled semiconductorsurface, such as hydrogen-terminated Si, is dif-ferent from a conventional metal-semiconductorSB in two important ways. First, the formationof interface states is suppressed in graphene-semiconductor junctions (11) because the inter-

action between chemically inert graphene and acompletely saturated semiconductor surface—that is, one without dangling bonds—is negligible(12). Second, graphene’s work function (WF)can be adjusted electrostatically over a widerange by tuning the Fermi energy (EF) via theelectrostatic field effect (13, 14). We could re-alize a graphene barristor (GB) by combiningthese two effects, as also shown in (15).

A schematic diagram of the GB structureand its top view are shown in Fig. 1, A and B.Single-layer graphene in contact with the sourceelectrode forms the SB at its interface with thesilicon surface at the drain contact. Two kinds ofGBs can be formed depending on the silicondoping type: n-type GB at n-type silicon andp-type GB at p-type silicon. We used transmis-sion electron microscopy (TEM) to develop anoptimal transfer process for graphene onto Sisubstrates to create atomically sharp interfaces(inset of Fig. 1C), which minimizes atomic de-fects or silicon dioxide formation that can createcharge trapping sites. Figure 1C displays a typicalSchottky diode characteristic of a p-type GB withan optimized graphene/Si interface. The forwardcharacteristic at a low bias showed a diode ide-ality factor hid ≈ 1:1 for this particular device.The ideality factor we obtained in our GB is con-siderably better than those reported in exfoliatedgraphene-Si junctions (9), confirming the high in-terfacial quality in our GBs.

The recent availability of large-scale graphenegrowth through chemical vapor deposition (CVD)techniques (16–20) allowed us to integrate graphenedevices at wafer scales using conventional semi-conductor microfabrication processes (21). Large-scale integration has not been possible for similardevices such as p-n diodes demonstrated in high-ly customized and suspended semiconducting

1Graphene Research Center, Samsung Advanced Institute ofTechnology, Yongin 446-712, Korea. 2Department of Physics,Columbia University, New York, NY 10027, USA. 3SamsungAdvanced Institute of Technology, Yongin 446-712, Korea.

*These authors contributed equally to this work.†To whom correspondence should be addressed. E-mail:hyunjong.chung@samsung.com

Fig. 1. Graphene barristor. (A) A schematic diagram to show the concept of a GB. (B) False-coloredscanning electron microscopy image of the GB before the top gate fabrication process. (C) Currentversus bias voltage characteristic of a GB at a fixed gate voltage Vgate = 0 V, showing a Schottky diodecharacteristic. The inset shows a TEM image of graphene/silicon junction. No native oxide or defect isseen in the image. (D) A photograph of ~2000 GB arrays implemented on a 6-inch wafer.

1 JUNE 2012 VOL 336 SCIENCE www.sciencemag.org1140

REPORTS

on

June

2, 2

012

ww

w.s

cien

cem

ag.o

rgD

ownl

oade

d fr

om

nanotubes (22, 23). We demonstrated integrationof gate-tunable GB arrays on a 6-inch wafer bytransferring a single-layer graphene grown byCVD (20, 24) onto a prepatterned Si substrate.Figure 1D shows an array of 2000 devices on a6-inch (150-mm) wafer. At room temperature,the range of the ideality factor and the currentdensity of GBs are found to be 1.1 to 4.0 and101 to 104 A/cm2, respectively (see figs. S3 toS5 in the supplementary materials) (25), wherethe variation is due to the different wafer batches.These GB devices exhibited >90% device yield,with excellent uniformity in terms of devicecharacteristics across the wafer with appropri-ate current level (fig. S2).

We could electrostatically modulate thegraphene’s WF through the top gate electrodeand gate dielectric above the graphene (14),which resulted in a variation on the SB height.Because the injection of the majority carriersfrom graphene to silicon is determined by theSB height fb, the top gate then directly controlsthe magnitude of the current across the sourceand the drain. The main panel of Fig. 2 showsthe characteristic of p-type GB at various gatevoltages (Vgate). The rectification behavior of theGB was demonstrated in that the GB current(ISD) increased steeply as the bias voltage (Vbias)surpassed the “turn-on” voltage, VTO. VTO couldbe adjusted between 0 V and 1.3 V as Vgate wasmodulated between –5 and 5 V, the range neededto keep this GB in p-type operation. Similar tri-ode behavior was observed in n-type GBs (Fig.2 inset), where the bias polarity was reversed be-cause electrons become the majority carrier. Thelarge modulation of the GB current was indica-tive of a large variation in the SB height, causedby the electric field effect (EFE) from Vgate.

To quantitatively analyze the device charac-teristic, we used the diode equation

I ¼ AAT2exp−qfbkBT

exp

qVbias

hidkBT

− 1

where A is the area of the Schottky junction, A*is the effective Richardson constant, q is theelementary charge, kB is the Boltzmann constant,and T is the temperature. Quantitative analysisof the SB height fb can be done byinvestigating the temperature dependence ofthe GB current in the reverse bias saturationregime ½expðqVbias=hidkBTÞ << 1. Here, thediode current becomes insensitive to Vbias andIsatºT2exp −qfb

kBT

. Figure 3A shows a plot of

ln (Isat/T2) versus q/kBT in the reverse bias

saturation regime. We estimated the SB heightfb for a given gate voltage Vgate from the slopeof each curve. Figure 3B shows the resultingSB heights obtained as a function of Vgate. Vgateincreased from 0 to 5 V, and fb decreased sub-stantially from 0.45 eV to 0.25 eV. We attributedthe drastic change in fb to the EFE-inducedFermi level change, DEF . Indeed, as shown inFig. 3B, the measured variation of fb, DFB ¼

Fig. 2. Graphene barristor characteristics.The current and bias voltage characteristicsof p-type (main panel) and n-type (inset)GBs at various fixed Vgate values. Vgatevaries in the range –5 to 5 V, with a stepsize of 1 V for each curve. The red arrowindicates the direction of increasing Vgate.

Fig. 3. (A) Temperature-dependent diode characteristic. The saturation current of the n-type GB, Isat, isobtained by measuring the current at Vbias = 2.5 V at various temperature and gate voltage values.Different colors are used for different Vgate from –1 to 4 V with 1- to 2-V step variation. The line fit foreach Vgate value is drawn to yield the Schottky barrier height from the slope of the fitted line. (B) TheSB height obtained from the fit in (A) as a function of Vgate (black squares, left y axis). The grapheneFermi energy on the right y axis is obtained from Hall measurement at the same gate voltage Vgate.Monotonic increase and decrease of observed SB height is consistent with the band diagrams in (C) and(D), respectively. (C and D) Schematic band diagrams of GB with the EFE generated by the gate on thetop of graphene. Applying negative voltage on the gate induces holes in graphene, increasing its workfunction and increasing the Schottky barrier height. As a result, the reverse current across the Schottkybarrier decreases (C). Positive gate voltage decreases the Schottky barrier height and increases reversedcurrent (D).

-2 -1 0 1 2

0

3

6

9

Cur

rent

(µA

)

Vbias (V)

-0.5 0.0 0.5 1.00

1

2

3

4

5

Cur

rent

Den

sity

(A

/cm

2 )

graphene/n-Si

graphene/p-Si

Vgate = -5 V ~ 5 VStep = 1V

Vbias (V)

www.sciencemag.org SCIENCE VOL 336 1 JUNE 2012 1141

REPORTS

on

June

2, 2

012

ww

w.s

cien

cem

ag.o

rgD

ownl

oade

d fr

om

fb − fbðDEF ¼ 0Þ, was well correlated to thechange of DEF , obtained independently by con-verting the measured Hall carrier density (nH)using DEF ¼ ħvF

ffiffiffiffiffiffiffiffipnH

p, where vF = 106 m/sec

was used for the Fermi velocity of graphene. Weobserved that DFB ≈ −DEF for a wide range ofVgate (fig. S7), which suggests that the WF mod-ulation of graphene in the absence of Fermi-levelpinning is fully responsible for the variation offb as depicted in Fig. 3, C and D.

The absence of Fermi-level pinning, one ofthe major sources for high device resistance insilicon electronics (26), comes from the suppres-sion of the surface states at the interface of siliconand graphene. In our GB, we could eliminatethe “Fermi-level pinning” and manipulate the SBheight as in the ideal Schottky-Mott limit (Fig.3B), where the SB height is controlled throughthe selection of metal and semiconductor withappropriate WFs (27, 28).

Two different types of GB operations are pos-sible, as shown in Fig. 4A. The first type uses theGB in the reverse-biased regime (orange shadedregion in Fig. 4A). Here, a conventional FET-like device operation could be possible; that is,the GB current, I, had the tendency to saturateat large reverse bias voltages, and the on-statecurrent, Ion, had been modulated by Vgate. Theoff-state current, Ioff, was determined at thegreatest attainable SB, which yielded an Ion/Ioffratio of ~300 in Fig. 4A. The second type ofoperation could be realized by using the devicein the forward biasing region (the blue shadedregion in Fig. 4A). In this regime, the diodecurrent did not saturate as Vbias increased butdeviated from a typical FET-like device opera-

tion. However, near the diode turn-on regime, Ivaried by several orders of magnitude as Vgatechanged, resulting in a switching operation witha large Ion/Ioff ratio. Figure 4B shows the switch-ing characteristic of the diode current in a forward-biased p-type GB, demonstrating a high Ion/Ioffratio of ~105. We note that the large Ion/Ioff ratioand small off-state current overcame the keyobstacle in graphene-based electronics.

Three-terminal operation of GB offers vari-ous integrated device functionalities. Similar tothe complementary metal-oxide semiconductorinverter operation, a series connection of n- andp-type complimentary GBs inverted the inputsignal Vin to its inverse Vout (Fig. 4C). The lowVout originated from the high on/off currentratio of GBs, which implies that only a smallamount of static off-state power would be con-sumed. As for more complicated logic applica-tions, we demonstrated a half-adder circuit builtfrom n- and p-type 10 GBs. The schematic withtwo inputs (A and B) and two outputs (SUM andCARRY) is shown in Fig. 4D. The measuredoutput voltage levels are represented in Fig. 4E.These results suggest that the GB can providea route to realize high-speed logic applications(29, 30) based on graphene-semiconductor hy-brid devices.

In conclusion, our GB suggests the possibil-ity of a graphene logic device by achieving ahigh on/off ratio of ~105, which exceeds the min-imum requirement for logic transistors. Further-more, the on/off ratio and the current density canbe improved with well-developed semiconductorprocesses because there is not a fundamental(or structural) limit. GB also has an advantage

in lateral scaling because the barrier is formedvertically.

References and Notes1. J. Bardeen, W. H. Brattain, Phys. Rev. 74, 230 (1948).2. M. Lundstrom, Science 299, 210 (2003).3. K. S. Novoselov et al., Nature 438, 197 (2005).4. A. K. Geim, K. S. Novoselov, Nat. Mater. 6, 183

(2007).5. Y. Zhang, Y.-W. Tan, H. L. Stormer, P. Kim, Nature 438,

201 (2005).6. X. Li et al., Adv. Mater. 22, 2743 (2010).7. S. Tongay, T. Schumann, A. F. Hebard, Appl. Phys. Lett.

95, 222103 (2009).8. T. Seyller, K. V. Emtsev, F. Speck, K.-Y. Gao, L. Ley,

Appl. Phys. Lett. 88, 242103 (2006).9. C.-C. Chen, M. Aykol, C.-C. Chang, A. F. J. Levi,

S. B. Cronin, Nano Lett. 11, 1863 (2011).10. S. Tongay et al., Carbon 49, 2033 (2011).11. L. Bell, W. J. Kaiser, M. H. Hecht, F. J. Grunthaner,

Appl. Phys. Lett. 52, 278 (1988).12. Y. Xu et al., Nano Lett. 11, 2735 (2011).13. F. Xia, V. Perebeinos, Y. M. Lin, Y. Wu, P. Avouris,

Nat. Nanotechnol. 6, 179 (2011).14. Y. J. Yu et al., Nano Lett. 9, 3430 (2009).15. L. Britnell et al., Science 335, 947 (2012).16. A. Reina et al., Nano Lett. 9, 30 (2009).17. K. S. Kim et al., Nature 457, 706 (2009).18. X. Li et al., Science 324, 1312 (2009).19. S. Bae et al., Nat. Nanotechnol. 5, 574 (2010).20. I. Jeon et al., ACS Nano 5, 1915 (2011).21. Materials and methods are available as supplementary

materials on Science Online.22. C.-H. Liu, C.-C. Wu, Z. Zhong, Nano Lett. 11, 1782

(2011).23. J. Lee, P. P. Gipp, C. M. Heller, Appl. Phys. Lett. 85, 145

(2004).24. J. Heo et al., Phys. Rev. B 84, 035421 (2011).25. H. Yabuta et al., Appl. Phys. Lett. 89, 112123 (2006).26. F. J. Himpsel, G. Hollinger, R. A. Pollak, Phys. Rev. B 28,

7014 (1983).27. M. C. Lonergan, Science 278, 2103 (1997).28. S. W. Boettcher et al., Nat. Mater. 6, 592 (2007).

Fig. 4. (A) Switching be-havior of p-type GB in re-verse (orange background)and forward (blue back-ground) bias regimes. TheGB current is plotted againstthe source drain bias at var-ious fixed gate voltages.Vgate varies in the range of–5 to 5 V, with a step of2 V. The black arrow in-dicates the direction ofincreasing Vgate. (B) Theforward diode current asa function of gate Vgate atfixed bias Vbias = 0.3 V.Unipolar control of forwardcurrent with the ratio of105 is obtained. (C) Invert-er characteristics obtainedfrom integrated n- andp-type GBs and schemat-ic circuit diagram for theinverter. Positive supplyvoltage (VDD) is connectedto p-type GB, and the gainof the inverter is ~1.2. (D)Schematic of circuit designof a half-adder implemented with n- and p-type GBs. (E) Output voltage levels for SUM and CARRY for four typical input states.

1 JUNE 2012 VOL 336 SCIENCE www.sciencemag.org1142

REPORTS

on

June

2, 2

012

ww

w.s

cien

cem

ag.o

rgD

ownl

oade

d fr

om

29. L. Liao et al., Nature 467, 305 (2010).30. Y.-M. Lin et al., IEEE Electron Device Lett. 32, 1343 (2011).

Acknowledgments: The authors are grateful to SamsungAdvanced Institute of Technology colleague X. Li for TEManalysis assistance and the Nano Fabrication group for process

assistance. We are also grateful to S.-H. Lee and S. Seo foruseful discussions.

Supplementary Materialswww.sciencemag.org/cgi/content/full/science.1220527/DC1Materials and Methods

Supplementary TextFigs. S1 to S10References

14 February 2012; accepted 4 April 201210.1126/science.1220527

Tailoring Electrical TransportAcross Grain Boundaries inPolycrystalline GrapheneAdam W. Tsen,1 Lola Brown,2 Mark P. Levendorf,2 Fereshte Ghahari,3 Pinshane Y. Huang,1

Robin W. Havener,1 Carlos S. Ruiz-Vargas,1 David A. Muller,1,4 Philip Kim,3 Jiwoong Park2,4*

Graphene produced by chemical vapor deposition (CVD) is polycrystalline, and scattering ofcharge carriers at grain boundaries (GBs) could degrade its performance relative to exfoliated,single-crystal graphene. However, the electrical properties of GBs have so far been addressedindirectly without simultaneous knowledge of their locations and structures. We presentelectrical measurements on individual GBs in CVD graphene first imaged by transmission electronmicroscopy. Unexpectedly, the electrical conductance improves by one order of magnitude forGBs with better interdomain connectivity. Our study suggests that polycrystalline graphene withgood stitching may allow for uniformly high electrical performance rivaling that of exfoliatedsamples, which we demonstrate using optimized growth conditions and device geometry.

Most three-dimensional electronic mate-rials produced in macroscopic quanti-ties are not homogeneous but incorporate

numerous classes of dislocations and defects thatdegrade electrical performance (1). Although large-scale graphene films produced by chemical vapordeposition (CVD) (2, 3) might be expected to benearly defect free, recent transmission electronmicroscopy (TEM) studies (4, 5) have shown thatthese films are polycrystalline. Electrical trans-port between single-crystal domains could be af-fected by scattering at the grain boundary (GB),as has been shown theoretically (6–9). AlthoughTEM has provided a fast and accurate means toidentify and image the structure of GBs in CVDgraphene, the electrical impact of GBs has so farbeen studied only indirectly in experiments. Pre-vious work by Huang et al. detects no mea-surable electrical resistance from GBs withininstrument limits (4), and ensemble measurementsdone by various groups find very weak correla-tion between the average domain size of thegraphene film and overall device mobility (4, 10).In contrast, Yu et al. and Jauregui et al. inferredthe presence of GBs from the shape of partiallygrown graphene islands and extracted a finite GBresistance from their measurements (11, 12). Theambiguity in these findings arose from a lack ofknowledge of the precise domain morphology

for the graphene measured. To this end, we havedevised an experimental scheme to first image(using TEM) and then electrically address in-dividual domains and GBs in polycrystallinegraphene. Such a capability is crucial, becausegraphene domain structures generated during syn-thesis form nontrivial patterns that are stronglydependent on growth conditions and difficult topredict a priori.

In Fig. 1A, we show false-color dark-fieldTEM (DF-TEM) images of graphene films grownunder three different conditions [see supplemen-tary materials (13)] taken in a manner similar toHuang et al. (4). Each colored region correspondsto a separate graphene crystalline domain withdistinct lattice orientation. The image is generatedby using an aperture in the back-focal plane ofthemicroscope to collect electrons diffracted fromonly a narrow range of angles by the graphenelattice. In general, different graphene domainsproduce a diffraction pattern rotated with respectto one another, so each domain can be imagedseparately, colorized, and then combined.

In growth A, graphene was synthesized un-der high reactant flow rates, which produced fastgrowth and also small average domain size D ≈1 mm.Graphene from growth B was synthesizedin a dilutedmethane environment, whereas growthC was further enclosed in copper foil, after Liet al. (14), resulting in slower growths. Thelatter films were terminated after only partialsurface coverage to highlight their growthstructures. In subsequent microscopy andelectrical measurements, however, we used con-tinuous films, for which growth B yielded D ≈10 mm and growth C, D ≈ 50 mm. The overallshapes of partially grown graphene islands ingrowth B were polygons, whereas growth C gen-erally formed flowered islands (fig. S1). Despite

1Department of Applied Physics, Cornell University, Ithaca, NY14853, USA. 2Department of Chemistry and Chemical Biology,Cornell University, Ithaca, NY 14853, USA. 3Department ofPhysics, Columbia University, New York, NY 10027, USA. 4KavliInstitute at Cornell for Nanoscale Science, Cornell University,Ithaca, NY 14853, USA.

*To whom correspondence should be addressed. E-mail:jpark@cornell.edu

Fig. 1. (A) Composite false-color DF-TEM images of CVD graphene produced using three differentgrowth conditions—A, B, and C—yielding average domain size D of 1, 10, and 50 mm, respectively,in continuous films. (B) (Left) Schematic of specially fabricated TEM chip compatible with electron-beam lithography and electrical measurements. (Top right) SEM image of top-gated, graphene Hallbar device. (Bottom right) Overlaid SEM and DF-TEM images showing device crossing a single GB oftwo domains from growth C. Scale bars, 1 mm.

www.sciencemag.org SCIENCE VOL 336 1 JUNE 2012 1143

REPORTS

on

June

2, 2

012

ww

w.s

cien

cem

ag.o

rgD

ownl

oade

d fr

om

www.sciencemag.org/cgi/content/full/science.1220527/DC1

Supplementary Materials for

Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier

Heejun Yang, Jinseong Heo, Seongjun Park, Hyun Jae Song, David H. Seo,

Kyung-Eun Byun, Philip Kim, InKyeong Yoo, Hyun-Jong Chung,* Kinam Kim

*To whom correspondence should be addressed. E-mail: hyunjong.chung@samsung.com

Published 17 May 2012 on Science Express

DOI: 10.1126/science.1220527

This PDF file includes:

Materials and Methods Supplementary Text Figs. S1 to S10 References

Materials and Methods

Preparation of Graphene-Silicon Junction

A single layer graphene-silicon junction is formed by transferring CVD-grown

graphene onto pre-patterned Si substrates. The pre-patterning was conducted on a 100 nm

thick SiO2 layer grown on a 6 inch wafer of n-Si (doping density of ~1016 cm-3) or p-Si

(doping density of ~1017 cm-3). Using photolithography and Buffered Oxide Etch (BOE)

processes, windows exposing bare Si underneath were fabricated with the dimension, 2 μm

× 4 μm. Before transferring graphene, native oxide on the exposed Si substrate was carefully

removed by additional wet etching followed by the passivation of Si surface with hydrogen

treatment in a controlled atmosphere. After placing the graphene on the substrate, Raman

spectrum was obtained to determine the quality of transferred graphene. Fig. S1 shows

Raman spectrum of graphene on SiO2 and graphene on Si. Well-developed G (~1600 cm-1)

and 2D (~2700 cm-1) peaks with no appreciable increase of D peak (~1300 cm-1) indicate

that the single layer graphene is well maintained on both SiO2 and Si after the wafer-scale

transfer process.

Supplementary Text

Device Uniformity on 6 Inch Wafer

Fig. S2A shows a histogram of mobility for graphene devices measured in field

effect transistor (FET) operation mode on the 6 inch wafers. Around 2000 FET devices were

fabricated and measured on the wafer. More than 90% of the devices showed proper field

effect mobility and the measured average mobility was around 1300 cm2/V·s. A few

representative device characteristics are shown in Fig. S2B.

The Ideality Factor and Diode On-Current Density

Similar to the p-type Schottky diode operation demonstrated in Fig. 1C, we also

demonstrate an ideality factor of up to 1.1 in n-type Schottky diode operation (Fig. S3). This

value is the best ideality factor reported in graphene Schottky junctions, reflecting the high

quality of interface we achieved between graphene/Si.

While the ideality factor of a graphene barrister (GB) device is determined by the

interface quality between the graphene and Si channel, the saturation on-current density is

subject to a series resistance, composed of the sheet resistance of graphene and the resistance

of a reverse biased Schottky junction at the interface between ‘Drain electrode’ and silicon.

Those two resistances can be improved by shaping graphene to having lower sheet resistance

and high concentration doping to to lower the Schottky resistance.

Given that we use forward bias current of graphene/silicon Schottky junction, there

are two critical reasons for the current density limits: graphene-metal contact resistance

(graphene-Au in our case) and reverse Schottky regime of the opposite electrode (silicon and

drain electrode). Eventually, graphene-metal contact resistance will also limit the maximum

saturation current in our GBs. Fig. S4 shows a device where some parts of such optimizations

are implemented. In this device, operation current density up to 5x103 A/cm2 is achieved,

more than two orders of magnitude improvement compared to un-optimized devices. Further

improvement of device architecture and doping of the Metal-Si contacts will further increase

the attainable saturation current density.

We also note that although our work is for realizing new idea toward graphene-based

electronics at this stage, our device already meets the current density specification of some

applications. For example, thin film transistor (TFT) requires an on-current of 1~10 μA, or

an on-current density of 1~10 A/cm2 (24). Since the graphene mobility is far beyond the

current TFT material, there could be a breakthrough in such applications.

Transmission Electron Microscopy Analysis

We analyze the quality of the graphene/Si interface using cross sectional imaging of

the junction using TEM. The well-optimized transfer process we developed produce

atomically clean interfaces between graphene and Si free from native oxide or other

contamination layers as shown in Fig.1C inset and Fig. S5B. However, we do also observe an

occasional contamination in between graphene and Si interface. Fig. S5A, shows a larger area

TEM image taken from un-optimized graphene transfer on Si substrate. Several regions

where extra material is located between graphene and silicon (red rectangle) can be seen in

this poor quality sample. We note that this extra material reduces the local thermionic

emission current and degrades the ideality factors of GBs. Reducing damage on silicon

substrate during the wet-etching process of silicon oxide was identified as a key in producing

atomically clean interfaces.

Formula for Saturation Current in Schottky Diode

In the thermionic emission regime, the saturation current, IS in I-V characteristic of the

junction can be expressed by,

Φ−=

TkT

B

BexpAAI 2*S S1

where A is the contact area, A* is the effective Richardson constant [≈ 252A cm-2 K-2 for n-

type silicon], T is the absolute temperature, BΦ is the Schottky barrier height, k is the

Boltzmann constant. Thus, from the current data with various temperatures (see Fig. S6), we

were able to extract the barrier height, 0.407 eV at zero top gate voltage. This value is close

to 0.45 eV, the energy difference value between the work function of graphene (4.5 eV) and

the electron affinity of silicon, χ (4.05 eV) and also is comparable to 0.41 eV a value close

to the reported value for graphene and n-type Si (9).

Schottky Barrier (SB) versus Fermi Energy

Graphene Fermi level is modulated by top gating and the electric field effect induced

carrier density can be probed by using Hall measurement. Fig. S7 inset shows the Hall

resistivity (left axis) and corresponding carrier density (right axis) as a function of the top

gate voltage. The Fermi energy of graphene can then be estimated from nvΔE FF π= .

Using this result, we plot in Fig. S7 the SB height versus FΔE . We note that BF ΔΦΔE ≈

in this graph, implying that the interfacial pinning is negligible.

Temperature Endurance

The principle GB device operation relies on the variable SB to modulate current. In

the off-state, thermionic emission across the SB dominates transport while near-Ohmic

transport takes place in the on-state. As shown in Fig. S8, the on-state current hardly changes

under temperature variation while the off-state current increase exponentially as temperature

increases. Therefore, the on/off current ratio drastically changes by temperature. Such

temperature dependence of the on/off ratio variation is very common in semiconductor

devices. In CMOS, with similarly sized barriers, a silicon channel shows similar temperature

dependence of off-state current. Therefore, it is considered that the temperature endurance of

our device would be analogous to conventional CMOS and could be overcome.

Device Modeling of Graphene Barristor

In order to quantitatively understand the GB device operation, we model GB with

three capacitors: top gate dielectric, silicon depletion region, graphene quantum capacitance

(Fig. S9). These three capacitors are involved in the device operation in terms of charge

balance in a static model. The following three equations describe the above three

capacitances.

( )232

2

1212

020

22dd : ecapacitanc quantum Graphene

]Vcm[105 : dielectric gate Top

,]cmF[)/(2

:Silicon

FF

fQ

T

Ds

BSiQbi

DsSi

vVe

v

neEneC

deC

WNAQ

WeTkVVVNeC

ππ

ε

εεεε

===

×=

==−+−

=

−−

−

With these formulas, we obtain an expression of electric potential at the interface of

graphene and silicon. Based on these potential values and diode equation, we then compute

the device current versus gate voltage. The resulting current is shown as a red curve in Fig.

S10.

The dotted line is ideal device performance based on gate-induced ‘Fermi-level shifting’ in

silicon. With the same gate dielectric dimension, our GB model shows steeper gate

dependence than the performance of state-of-art CMOS transistor with 28 nm gate length.

Figure captions

Figure S1 | Raman spectrum of graphene on SiO2 and graphene on Si.

Figure S2 | (A) Histogram of mobility for devices on a 6 inch wafer (2000 devices in total). (B) a few

example of the representative FET characteristics.

Figure S3 | Current versus bias voltage characteristic of a n-type graphene barristor at a fixed gate

voltage, Vg = 0 V, showing a Schottky diode characteristic. Ideality factor of the diode operation,

1.1≈idη is obtained from the line fitting in the forward bias regime (solid line).

Figure S4 | Left panel displays I-V characteristic of GB in diode operation with various fixed gate

voltages in linear scale. The right panel shows the resulting diode current density showing maximum

saturation current density 5x103 A/cm2 is achieved at the forward bias regime.

Figure S5 | Transmission Electron Microscopy images of graphene/silicon, (A) defected interface

showing poor interfacial quality, (B) Atomically sharp interface between graphene on Si after

optimized transferring process.

Figure S6 | Temperature dependent I-V curves of graphene-silicon (p-type) diode.

Figure S7 | Schottky barrier versus graphene Fermi energy. Schottky barrier height is modulated by

FB ESΔΔΦ = where line fitting (dotted line) gives S~1. Inset; Hall resistivity, ρxy (left axis) is

measured and nH (right axis) is estimated from nH=B/eρxy , where B= 2 T is applied magnetic field.

Fermi level of graphene is then calculated by using HFF nvΔE π= .

Figure S8 | Temperature dependence of on- and off-state current of GB.

Figure S9 | Schematic diagram for GB with three capacitors.

Figure S10 | Simulation and comparison of device current (CMOS and Graphene Barristor) at room

temperature.

Fig. S1

0 1000 2000 3000 4000 50000

200

400

600

800

co

unts

mobility(cm2/V⋅s)0 1000 2000 3000 4000 5000

0

200

400

600

800

co

unts

mobility(cm2/V⋅s)-3 -2 -1 0 1 2 3 4

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

G(m

S)VG(V)

-3 -2 -1 0 1 2 3 40.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

G(m

S)VG(V)

A B

Isd=10 μA

Fig. S2

-2 -1 0 1 210-1210-1110-1010-910-810-710-610-5

Cu

rrent

(A)

Voltage (V)-2 -1 0 1 2

10-1210-1110-1010-910-810-710-610-5

Cu

rrent

(A)

Voltage (V)

ηid ≈ 1.1

Fig. S3

-4 -2 0 2 4

10-7

10-5

10-3

10-1

101

Cur

rent

(mA)

Vbias (V)-4 -2 0 2 4

10-7

10-5

10-3

10-1

101

Cur

rent

(mA)

Vbias (V)

10-6

10-4

10-2

100

102

104

-4 -2 0 2 40

1

2

3

Cur

rent

(mA)

Vbias (V)-4 -2 0 2 4

0

1

2

3

Cur

rent

(mA)

Vbias (V)

Current D

ensity (A/cm

2)

Fig. S4

Fig. S5

-2 -1 0 1 2

10-12

10-10

10-8

10-6

I(A)

Vbias(V)

260 280 300 320 340

Fig. S6

0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.220.26

0.28

0.30

0.32

0.34

0.36

0.38

0.40

0.42

-4-3-2-1 0 1 2 3 4-9-6-30369

Vtop(V)ρ xy

(kΩ)

ISD=2µA

-4-2024 n(10

12cm-2)

Φ Β(e

V)

∆EF(eV)

S∼1

Fig. S7

200 250 300 350 40010-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

Ioff ∝exp(-ΦB/kT)ΦB~0.5eV

Cu

rrent

(A)

Temperature (K)

Ion~ nearly ohmic

Fig. S8

CSi CT

CQ

VTVSi

0V

VQ

Graphene

Backgate Topgate

Schematic

Fig. S9

0.0 0.5 1.0

10-12

10-9

10-6

10-3

Curre

nt (A

)

VGATE(V)

60mV/dec 28nm CMOS GSD

theoretical SS

0.0 0.5 1.0

10-12

10-9

10-6

10-3

Curre

nt (A

)

VGATE(V)

60mV/dec 28nm CMOS GSD

theoretical SS

ND= 1016 cm-3

Vbi=0.45-0.2 eV (built-in potential)εs = 12 (silicon)gate thickness d=0.6 nm, ε=4 (SiO2)Area=0.006 μm2

Fig. S10

References and Notes

1. J. Bardeen, W. H. Brattain, The transistor, a semi-conductor triode. Phys. Rev. 74, 230

(1948). doi:10.1103/PhysRev.74.230

2. M. Lundstrom, Moore’s law forever? Science 299, 210 (2003).

doi:10.1126/science.1079567 Medline

3. K. S. Novoselov et al., Two-dimensional gas of massless Dirac fermions in graphene.

Nature 438, 197 (2005). doi:10.1038/nature04233 Medline

4. A. K. Geim, K. S. Novoselov, The rise of graphene. Nat. Mater. 6, 183 (2007).

doi:10.1038/nmat1849 Medline

5. Y. Zhang, Y.-W. Tan, H. L. Stormer, P. Kim, Experimental observation of the

quantum Hall effect and Berry’s phase in graphene. Nature 438, 201 (2005).

doi:10.1038/nature04235 Medline

6. X. Li et al., Graphene-on-silicon Schottky junction solar cells. Adv. Mater. 22, 2743

(2010). doi:10.1002/adma.200904383

7. S. Tongay, T. Schumann, A. F. Hebard, Graphite based Schottky diodes formed on Si,

GaAs, and 4H-SiC substrates. Appl. Phys. Lett. 95, 222103 (2009).

doi:10.1063/1.3268788

8. T. Seyller, K. V. Emtsev, F. Speck, K.-Y. Gao, L. Ley, Schottky barrier between 6H-

SiC and graphite: Implications for metal/SiC contact formation. Appl. Phys. Lett.

88, 242103 (2006). doi:10.1063/1.2213928

9. C.-C. Chen, M. Aykol, C.-C. Chang, A. F. J. Levi, S. B. Cronin, Graphene-silicon

Schottky diodes. Nano Lett. 11, 1863 (2011). doi:10.1021/nl104364c Medline

10. S. Tongay, T. Schumann, X. Miao, B. R. Appleton, A. F. Hebard, Tuning Schottky

diodes at the many-layer-graphene/semiconductor interface by doping. Carbon

49, 2033 (2011). doi:10.1016/j.carbon.2011.01.029

11. L. Bell, W. J. Kaiser, M. H. Hecht, F. J. Grunthaner, Direct control and

characterization of a Schottky barrier by scanning tunneling microscopy. Appl.

Phys. Lett. 52, 278 (1988). doi:10.1063/1.99493

12. Y. Xu et al., Inducing electronic changes in graphene through silicon (100) substrate

modification. Nano Lett. 11, 2735 (2011). doi:10.1021/nl201022t Medline

13. F. Xia, V. Perebeinos, Y. M. Lin, Y. Wu, P. Avouris, The origins and limits of metal-

graphene junction resistance. Nat. Nanotechnol. 6, 179 (2011).

doi:10.1038/nnano.2011.6 Medline

14. Y. J. Yu et al., Tuning the graphene work function by electric field effect. Nano Lett.

9, 3430 (2009). doi:10.1021/nl901572a Medline

15. A. Reina et al., Large area, few-layer graphene films on arbitrary substrates by

chemical vapor deposition. Nano Lett. 9, 30 (2009). doi:10.1021/nl801827v

16. K. S. Kim et al., Large-scale pattern growth of graphene films for stretchable

transparent electrodes. Nature 457, 706 (2009). doi:10.1038/nature07719 Medline

17. X. Li et al., Large-area synthesis of high-quality and uniform graphene films on

copper foils. Science 324, 1312 (2009). doi:10.1126/science.1171245 Medline

18. S. Bae et al., Roll-to-roll production of 30-inch graphene films for transparent

electrodes. Nat. Nanotechnol. 5, 574 (2010). doi:10.1038/nnano.2010.132

Medline

19. I. Jeon et al., Passivation of metal surface states: Microscopic origin for uniform

monolayer graphene by low temperature chemical vapor deposition. ACS Nano 5,

1915 (2011). doi:10.1021/nn102916c Medline

20. Materials and methods are available as supplementary materials on Science Online.

21. C.-H. Liu, C.-C. Wu, Z. Zhong, A fully tunable single-walled carbon nanotube diode.

Nano Lett. 11, 1782 (2011). doi:10.1021/nl200371z Medline

22. J. Lee, P. P. Gipp, C. M. Heller, Carbon nanotube p-n junction diodes. Appl. Phys.

Lett. 85, 145 (2004). doi:10.1063/1.1769595

23. J. Heo et al., Nonmonotonic temperature dependent transport in graphene grown by

chemical vapor deposition. Phys. Rev. B 84, 035421 (2011).

doi:10.1103/PhysRevB.84.035421

24. H. Yabuta et al., High-mobility thin-film transistor with amorphous InGaZnO4

channel fabricated by room temperature rf-magnetron sputtering. Appl. Phys. Lett.

89, 112123 (2006). doi:10.1063/1.2353811

25. F. J. Himpsel, G. Hollinger, R. A. Pollak, Determination of the Fermi-level pinning

position at Si(111) surfaces. Phys. Rev. B 28, 7014 (1983).

doi:10.1103/PhysRevB.28.7014

26. M. C. Lonergan, A tunable diode based on an inorganic semiconductor–conjugated

polymer interface. Science 278, 2103 (1997). doi:10.1126/science.278.5346.2103

Medline

27. S. W. Boettcher et al., Tunable electronic interfaces between bulk semiconductors

and ligand-stabilized nanoparticle assemblies. Nat. Mater. 6, 592 (2007).

doi:10.1038/nmat1943 Medline

28. L. Liao et al., High-speed graphene transistors with a self-aligned nanowire gate.

Nature 467, 305 (2010). doi:10.1038/nature09405 Medline

29. Y.-M. Lin et al., Enhanced performance in epitaxial graphene FETs with optimized

channel morphology. IEEE Electron Device Lett. 32, 1343 (2011).

doi:10.1109/LED.2011.2162934