Form ApprovedREPORT DOCUMENTATION PAGE OMB No. 0704-0188

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4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER

N0001 4-98-1-0830High Resolution Transferred Substrate HBT Microwave/RF 5b. GRANT NUMBERADCs

8-442530-258635c. PROGRAM ELEMENT NUMBER

6. AUTHOR(S) 5d. PROJECT NUMBER

Mark J.W. Rodwell Se. TASK NUMBER

5f. WORK UNIT NUMBER

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATIONREPORT NUMBER

Department of Electrical and Computer EngineeringUniversity of California, Santa Barbara, CA 93106

9. SPONSORINGIMONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Office of Naval ResearchAwarding Office Contact Elizabeth L. Ford ONR 251Ballston Centre Tower One 11. SPONSORINGIMONITORING800 North Quincy Street AGENCY REPORT NUMBERArlington, VA 22217-566012. DISTRIBUTION AVAILABILITY STATEMENT

13. SUPPLEMENTARY NOTES 20 30527 14214. ABSTRACT

The attached report describes development of wideband delta sigma ADCsusing high speed Indium Phosphide bipolar transistors.

15. SUBJECTTERMS DISTRIBUTION STATEMENTAApproved for Public Release

Distribution Unlimited16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF 18. NUMBER 19a. NAME OF RESPONSIBLE PERSON

a. REPORT b. ABSTRACT c. THIS PAGE ABSTRACT OF PAGES Mark J.W. Rodwell19 19b. TELEPONE NUMBER (Include area code)

(805) 893-3244

Standard Form 298 (Rev. 8-98)Prescribed by ANSI-Std Z39-18

Final contract report for

Government Contract Number: N00014-98-1-0830

UCSB Contract Number: 8-442530-25863-3

High Resolution Transferred Substrate HBT Microwave/RF ADCs

Mark J.W. Rodwell

Department of Electrical and Computer Engineering

University of California, Santa Barbara, California, 93106

IN TR O D U C T IO N ........................................................................................................................................ 2

TECHNICAL BACKGROUND: THEORY OF DELTA SIGMA ADCS ......................................... 3

IC S D ESIG N ED ........................................................................................................................................... 4

FIRST-GENERATION DELTA-SIGMA ADC ................................................................................... 5

THIRD-GENERATION DELTA-SIGMA ADC ................................................................................. 11

STAFF SUPPO RTED ................................................................................................................................ 17

PUBLICATIONS ASSOCIATED WITH CONTRACT .................................................................... 18

Introduction

In the proposed program, very high clock frequency A - Z ADCs were proposed as amethod of obtaining high effective resolutions over large signal bandwidths. In A - ZADCs, high resolutions are obtained through a combination of oversampling and noiseshaping with frequency-selective feedback; with a typical 2nd-order loop design, each2:1 increase in the sampling rate relative to the Nyquist frequency increases the effectiveresolution by 2.5 bits. Target resolution of ADCs in Naval radar systems is in the rangeof 8-12 bits, with the highest feasible signal bandwidth. Bandwidths as much as 1 GHzmight be demanded in a system with high bandwidth.

At the time of program initiation, transferred-substrate HBTs in development at UCSBhad a significant bandwidth advantage over competing devices for high speed mixedsignal ICs. A program effort was therefore undertaken to realize A - Z ADCs with veryhigh clock frequencies in this technology. The original objective was to obtain samplingrates in the 20-40 GHz range. Together with complex multi-bit internal quantizers, atheoretical resolution of 16 bits at 160 MHz signal bandwidth might be feasible.

Realizable system performance falls far below these goals. First, the limits on fabricationyield in a university process force the circuit complexity to be kept below severalhundred transistors, at high level only a single-bit internal quantizer is feasible. Secondly,although the transferred-substrate technology proved to be capable of digital circuitoperation at clock frequencies as high as 75 GHz, accurate operation of a latchedcomparator requires that its clock frequency be well below that the maximum digitalclock rate feasible. Consequently, the maximum useful clock frequency obtainable is 10-20 GHz with the current status of high speed InP HBT technology. At this level ofperformance, 8.3 effective bits resolution is feasible for a 125 MHz bandwidth. Whilethis is a very high resolution for a wideband A - Z ADC, alternative approaches(pipelined Nyquist converters) offer somewhat superior performance.

2

Technical Background: theory of delta sigma ADCs

AZ ADC: High Resolution from High Clock Speed

~s

quantizer

Ibit ~ 4ii

(its resolution) 2.5 - 102 clock frequency ) 21+ # of excess bits in2 2t signal frequency) (intemal quani

Fast Transferred-Substrate HBTs -- 20 GHz clock-- high resolution

Figure 1: Block Diagram of a A - Z ADC

A - Y ADCs obtain high resolution by placing negative feedback around (typically) aone-bit ADC. The output is a rapidly-fluctuating one-bit word whose time-average valueaccurately represents the input voltage. The frequency response of the 2-integratorfeedback loop results in very high feedback loop gain at low frequencies, suppressingquantization noise at any signal frequency in proportion to the loop gain at thatfrequency. The loop forces the signal power associated with the quantization noise powerto be driven to high frequencies, and (mostly) out of the bandwidth of interest. Given aone-bit ADC, quantizers in the ADC must set only a single threshold at zero volts, hencecomponent precision of no relevance. Against this advantage, the A - E ADC requiresvery high feedback factors at the signal frequencies of interest, which implies a very highoversampling ratio.

Mathematical theory of the A - Y ADC will not be derived here. The effective number ofbits resolution for an ideal 2nd-order A - I ADC is given by:

3

, F clockjfrequency1# bits resolution = 2.5 * log 2 I I -2.1 + # bits in the internal quantizer[ 2 x signal_frequencyI

The resolution increases at a rate 2.5 times the log of the oversampling ratio as aconsequence of (1) the uniform frequency distribution of the quantization noise of theinternal quantizer and (2) the gain of the 2-integrator loop varying as (f•,ock /f) 2 . If the

clock frequency is doubled relative to the signal frequency, the quantization noise poweris spread over a 2:1 larger bandwidth, increasing resolution by 1/2 bit, and the loop gainat a given signal frequency is increased 4-fold, increasing the resolution by 2 bit. Thuseach 2:1 increase in the clock frequency relative to the signal frequency increasesresolution by 2.5 bits.

High resolutions with lower clock frequencies can be obtained if the A - Y modulatorcontains more than 2 integrators within the feedback loop. ADCs of higher than secondorder (2 integrators) are extremely prone to limit-cycle oscillations, particularly if only asingle-bit internal quantizer is employed. In this manner, bandwidth requirements on theADC are eased, albeit at the expense of substantially increased circuit design difficulty.In particular, prevention of signal-dependent limit-cycle oscillations generally demandsuse of limiters within the A - Y feedback loop, which in turn impairs resolution. Fordemonstrated ADCs, the improvement of resolution with integration orders higher than 2is not large.

Further improvements in resolution can be obtained using multi-bit quantization withassociated error randomization, as is also illustrated in figure 1. With a multi-bit feedbackDAC, mismatch errors in the DAC are in the feedback path, and are therefore notsuppressed by the loop gain. Errors must therefore instead be suppressed by errorrandomization techniques. Such circuits, while common in CMOS, have very hightransistor counts.

Instead, in this program, higher resolutions were sought through the highest possibleclock frequencies. Transferred-substrate HBTs provided at the time record transistorbandwidth and hence offer the potential for the highest A - Z clock frequencies.

ICs designed

In this program, two generations of A - Z ADC were ultimately designed, fabricated, andtested. The first was in transferred-substrate technology, and had a 20 GHz clock rate.For this design, resolution fell far below theoretical levels, in part due to dynamic errorsarising from metastability effects in the latched comparator. Because it was found thatyielding large ICs in the transferred-substrate technology was difficult, the second-generation design was implemented in a more standard and Manufacturable mesa HBTtechnology. So as to properly interface with available digital instruments, this IC was

4

also operated at a reduced 8 GHz clock frequency, and showed resolution closer to -butstill somewhat below - theoretical predictions.

First-Generation Delta-Sigma ADC

The first-generation design was implemented in transferred-substrate HBT technology.

High SNR: Key Issues

Clock frequency limited by integrator excess delayNeed low integrator excess delay -_ high integrator bandwidth

Integrator DC gainNeed low frequency pole < signal frequency -4 gain requirementMany design fixes: gm-Zt, bootstrapping -- high integrator excess delay

Comparator metastability / hysteresis / overdrive recoveryfor more than a few mV deadzone -4 increased noiseneed fast HB Ts, low - hysteresis designs

Linearity of input stageDirectly degrades IP3Fixes: Caprio's cell, Passive summation at the input

Noise of input stageDirectly impacts SNRNeed high V 11,f/k TR -> Very high IP3 or sub - 50 n interface

Figure 2: Key issues determining A - Z ADC SNR hence resolution.

Figure 2 highlights the key issues regarding the design of high resolution A - Z ADCs.While high clock rates are potentially feasible up to the maximum frequency at which alatched comparator can be toggled, the highest clock rate at reasonable performance isalso limited the excess phase delay in the loop, and by dynamic imperfections in thecomparator. These imperfections, which include dynamic hysteresis, metastability, andoverdrive recovery time, become progressively more severe as the comparator toggle rateis increased. For this reason, although the transferred-substrate technology at the timecould support a -70 GHz toggle rate, target A - Z clock rates were instead lower at -20GHz.

Additional constrains on the performance of the A - Z ADC include the gains of theintegrators, and the linearity and noise of the input stage. Ideally, the integrator gain

5

varies at f, / f, but the finite input and load resistances of the transistor stages cause the

gain to instead be finite at low frequencies. This finite gain limits the degree of in-bandnoise suppression.

Excess Loop Delay

LK 92 lfor FFT

Vq (s) = e•sd (--g2 S )src ,(g MnVin (S) - l dacVout (S))

=sC i+ I (9m1i n Vda ot)) (s-d <<

Compensate for the delay with a zero: . z = Id

Figure 3: Excess loop delay and the impact on SNR

Excess delay in the forward path (Figure 3) arises from transistor parasitics in the 2integrators, from delay in the latch, and (if present) from additional delay associated witha 2-stage (MSS) latch. While these effects are predicted by an approximate linearizedanalysis to have no impact upon the loop noise suppression, exact analysis by MATLAB(fig. 4) shows substantial degradation when the excess delay is of order 10% of the clockperiod. Introduction of a zero (fig. 3, fig. 4) is an effective method of avoiding thisdegradation, and is effective for delays as large as 50% of the clock period

6

Limit to Clock Frequency: Excess delay0

IdealW -20 -,E - 20 ps delay

20 ps delay

corn peuisailn•-80CA."- -100 ftSC[L' fd& =20 GHz0 -120 - OSR =128 7

-140 1

10 10 107 10 10Frequency (Hz)

- 20 ps delay -- 12 dB reduction in SNR (20 GHz clock)

- SNR restored to idealioop value by delay compensationDelay compensation using a zero works!

Figure 4: Effect of excess loop delay on SNR

Integrator Design High Gain, Low Excess Delay

Objectives +sv

"* low integrator delay Common Mode -- RL- High RL,Voltage sensor 1 125 kW High DC Voltage,•, : • : High DC gain

->high clock frequency ghD gi

-- high signal / noise r-. Vout"• high integrator gain

-4 high signal/ noise delay

Approach compensatior

gm - stage loaded bygrounded capacitor: gi2thigh gain 5 5 f2

"* large load resistance 'bias 'bias"* common-mode feedback 0 .1,u F r.lo fe e d fo rw a rd

low delay -compensation

"* simple signal path"* feedforward compensation Vraf OFF-CHIP

• delay compensation Desired Common Common ModeMode Voltage Feedback

Figure 5: Integrator Design

7

The integrators within the loop must have high gain at the frequencies at whichsignificant noise suppression is desired; the noise suppression being proportional to theproduct of the 2 integrators gain at those same frequencies. While HBT processes excel atproducing wideband circuits, circuits with high gain at lower frequencies are morechallenging due to both the finite DC current gain ,6, and due to the lack of a

complementary (PNP+NPN) process. Without this, pull-up resistors of finite value mustbe used for bias currents, and their finite resistance leads to finite gain. Use (Fig. 5) ofvery large pull-up resistances results in difficulties in controlling DC bias, difficultieswhich are addressed though use of an off-wafer common-mode bias feedback controlloop.

Comparator "Metastability": Major Speed / Resolution Limit

i (Next)

V14 'iqlogicVout Vout

Voutt

inj': AVi n : V .I .21

S•Cloc Clck

Small input: loading, regeneration take several time constants

Comparator resolution degrades as clock speed is increased

Solutions:

Faster transistors, better circuit design

Reset comparator between samples to speed the recovery

Figure 6: Metastability and dynamic hysteresis errors.

The aforementioned limitations in noise suppression, while significant, are thusaddressed and resolved by appropriate circuit design. A more fundamental problemrelates to the dynamic resolution of the latched comparator (fig. 6). Two significantlimitations are dynamic hysteresis and metastability. Dynamic hysteresis (fig. 6) arisesbecause finite time required to reset the latch between clocking events. This resettransient may overwhelm a small input signal, causing the latch to hold the prior state.Metastability (fig. 6 and fig. 7) results from the modulation of latch output risetime bythe strength of the input signal.

8

Feedback Error due to Metastability

MASTER SLAVE D°°c hL

MSFFout 7- :Delayed Gated odlatioCLK CK_5

LLI

WeakLogic 01

Comparator inputs Comparator output edge timing DAC output: gated to suppressmodulated by input strength the effect of timing modulation

Comparator weak input effects-4 output timing modulation --• DAC feedback error -- SNR degradation

Solutions: Gated DAC, Extra level of regeneration,

using preamplifier at the input to quantizer

Figure 7: Metastability errors and their partial suppression by latch gating.

This modulation of signal risetime modulated the amount of charge fed back by the DACto the A - Y input. As an feedback error, the magnitude of this error is not suppressed bythe loop gain. Metastability thus is a serious limit to A - I resolution. In the firstgeneration A - Z designs, the magnitude of metastability errors was partially suppressed(fig. 8) through gating of the DAC feedback signal, eliminating much of the signal duringthe time when the risetime modulation is most significant.

Linearity and thermal noise of the input stage are additional limits to both the ADCspurious-free dynamic range and the signal/noise ratio. The first generation designs usedCaprio's cell to reduce input stage intermodulation. Bias currents and resistor values inthe input stage were selected to keep the input thermal noise below the quantizationnoise.

Figure 8 shows a simplified circuit schematic, while figure 9 shows a die photograph.The IC has approximately 200 transistors, and is fabricated in the transferred-substratetechnology. The dimensions and epitaxial layers are such that typical transistors have 200GHz f, and frax, while the latched comparators have a maximum 75 GHz clock

frequency.

9

Circuit Schematic of the entire loop

( omop.' 5.0todo-w p- o ��" p�.�J MWS latched comparator

Input --T .T

integrato i

Inero

integrator 2

clock

dleclock buffers

.rzo, c lockc

RTZ DAC clk

Figure 8: Simplified IC schematic

Die photograph of the completed IC

Figure 9: Die photograph, first generation design

10

Signal+Distortion and Noise data-I2-tone tests @ 150 MHz and @ 500 MHz

-20- -20 -20 f. f-20"I"./ 2 7 - 1 2...... , . X

-40- _-40 -40 -40

. O .N0 Ca N-/ :, .• (ý-f, (2f- T :•o60 - (2f-E2). (2ff) 2o

-80 .- 80" K • .-80 E

o lCO 0)

-100 f, 14. M ~ .- 0- f, 499.9 MHz 0.f 150.1 MHz T '5 f 500.1 MHz

O 120 .2 -120 "120 2 -120

-140- .. . ....... 140 -140 A. -1-0

-160 Noise floor -160 -160 Noise floor -160

-80 -70 -0 0 -40 -30 -20 -10 0 -7 - -40 -30 -20 -10Pin (dBm) Pin (dBm)

Figure 10: Performance, first-generation design.

Figure 10 shows the measured performance with 2 tone testing. Because the 20 GHz datastream could not be captured digitally, the output was instead measured by analogfiltering and measurement on a spectrum analyzer. There is consequently significanterror in the measurements. Beyond this point, the system resolution was well below thatexpected from simulations.

Third-Generation Delta-Sigma ADC

Subsequent to the design above, 2 additional design cycles of the A - Y ADC werepursued. The 2nd generation design and the third-generation design used similar circuitdesign improvements; the 2 designs differ primarily in that the 2nd generation design wasbased upon transferred-substrate HBT technology, while the 3rd generation design used amore conventional mesa HBT process. This 3rd-generation design was motivated bycontinuing difficulties in obtaining acceptable process yield in large ICs in thetransferred-substrate process. Indeed, the overall program progress was delayed bynumerous failures in IC processing. No 2nd-generation ICs were completed, hence thereport will focus on the 3rd generation design.

In order to obtain acceptable yield on the 3rd generation designs, a mesa HBT processwas employed. The objectives were to obtain high yield on devices, good RFperformance (200 GHz ft and fmax), and low Ccb. These devices use dimensions that had

11

earlier shown the best yield in the transferred-substrate technology (0.7 urn emitters). Toobtain acceptably low Ccb, a narrow base mesa (1.7 - 2.1 um width) is employed, andlow resistance Pd/Ti/Pd/Au base-ohmic contacts were used for reduced Rbb. Figure 11summarizes the mesa HBT technology performance circa Spring 2002. At that timetransistors with 200 GHz f, and fmax , high breakdown, and high current density, could

be fabricated.

InP/InGaAs/InP Mesa DHBTDevice Results

junction 0.6 *7um2

5 3=30-35 C

4-

v (v'o~s)

ScE,

5 ... 0'2.... 0'4 .0. ...... 0' ' . .........

Emitter metal 0.7 X 8 un?

40- junction 0.6 X 7 un?

h U V 1.2 V:J 2e5 Aicrn630S2 narrow 1.7 gm base mesa, 0.7 gm

20 emitter10 Jkik = 2e5 A/cm2 @ Vce = 0.7 V

0 10 100 f, = 200 GHz; fmax=205 GHzFrequency (GHz) 10 = 35; BVCEo = 6 V

Figure 11: Performance of narrow-mesa DHBT technology circa May 2002

12

IC wiring environment

Interconnect cross-section top view after plating ground-plane

-;ground plane

BCB

- resistors m metall m SiN , metal2

"* Thin-film-dielectric (5 ýtm BCB) microstrip wiring

"• Reduced ground via inductance, Minimal line - linecoupling

* 8 gm line gives controlled 50 Q impedance

Figure 12: Thin-film microstrip wiring environment and ground plane in Narrow-mesatechnology

The IC technology also employed a thin-film microstrip wiring environment (figure 12).This feature was carried over from the transferred-substrate process. Normal mixedsignal ICs use random wiring, which is simple to fabricated. This however givesuncontrolled line impedances and varying degrees of circuit coupling through groundbounce. The thin film environment provides and controlled and predictable Zo for allinterconnects, and eliminates circuit-circuit coupling through nonzero ground systemimpedance.

13

Effect of M-S-S latch on SNR* Additional stage of 0regeneration necessary to M-S lath

minimise metastability errors M-" latch

* Excess delay introduced bythe additional stage alters 60

quantizer input, output -80

spectrum and degrades SNR

- Loss in SNR fully recovered aby moving centroid of DAC to 120

original position Frequency (Hz)

addl. stage of regeneration CLK HM- S Idac

M-S latclt

latch

RTZ DAC A way to recover SNR

* RTZ DAC pushes centroid CLK

forward by Tclk/4 CLK

Zeroes of the loop can be MSac

adjusted to compensate for - - - -F- -- ,--the rest of the delay (Tclk/ 4 )

Idno IITTt

Ideal locatior , T _RTZ DAC L J

.-2 MSSlath; RTZOAC Tic changed.•' i

M-S-S latch t-I /-"\M, IRTZ DAC

10, 10' 10 10 10.Frequency (W-)

Figure 13: An MSS latch reduces metastability errors but degrades SNR throughincreased loop delay. This excess delay can be compensated for by addition of a gated

(RTZ) latch and additional zeros inserted into the loop transfer function.

14

One key change between the 1 st and 3rd generation design (fig. 13) was the method ofreducing metastability errors. In the 3rd generation design, this is provided throughaddition of a 2nd stage of regeneration in the form of an MSS latch. The excess delaythus introduced can degrade the SNR; this excess delay is reduced through use of an RTZDAC and partially compensated for by insertion of a zero in the loop transfer function.

Input Stage Design40 2........ ......

15020-

100 RL, RL

°150 N t r-80 -00

400 ",'\ -502Re 2 L :

"i, 10 e0 Neate res100-- 20

, , .q..-Y 0 38 dB DC gain, pole @ 30 MHz

"* Negative Resistance loads for high DC gain

"• Integrator bias current >> DAC current for high linearity ; E - Aloop overload occurs before integrator overload

"* Good compromise between transistor count and performance

"* Trading DC power for circuit complexity

Figure 14: Negative-resistance loading for high integrator gain at low frequencies.

A second significant design change was in the integrators. In the 3rd-generation design(Fig. 14) high gain at low frequencies is obtained by using negative-resistance loading ofthe Gm cells. This proved significantly less sensitive to power supply voltage than thecommon-mode feedback technique.

15

Final designs (10 GHz clock)

-20 c -20

E-40- -40.

T C60C o -60

-80. BO-0

S-ba .2 -Ei000

1 110 0 0 101Frequency (Hz) Frequency (Hz)

Figure 15: Completed 3rd-generation A - I ADCs with NRZ and RTZ DACs.

Figure 15 shows the completed 3rd-generation DACs (photographs taken beforedeposition of the ground planes) , showing designs both with and without the RTZ DAC.The ICs contain approximately 75 transistors.

16

SNR and # of bits of resolution

For an equivalentNyquist-rate ADC, SNR -20E

and effective # of bits of ZWresolution, ENOB, are ( -60

related by o 8o-

~ENOB =(SNR-1 .76)/6.02 0-120;o oFrequency (Hz)

Noise powe ripeasured at upper band edge Noise power integratedto signal frequencySignal Equivalent SNR, SNR, SNR, ENOB SNR, SNR, SNR, ENOBFrequency, Sampling dB dB dB dB dB dBHz rate, S/s 61 kHz 1 Hz Nyquist 61 kHz 1 Hz Nyquist

6.25e7 1.25e8 85.37 133.23 55.3 8.89 87.54 135.39 57.4 9.25

1.25e8 2.5e8 81.3 129.16 48.2 7.71 84.8 132.65 51.7 8.29

2.5e8 5e8 70.7 118.56 34.6 5.45 76.3 124.15 40.2 6.38

Figure 16: Tabulation of measured performance

Because the clock rate was reduced to 8 GHz in the 3rd generation design, the digitaloutput could be captured using commercially available high speed digital electronicsdeveloped for the 10 Gb/s optical fiber transmission market. The data is then captured ona logic analyzer, downloaded to a PC, and the FFT computed. Measurement results aresummarized in figure 16. At a signal frequency of 125 MHz (equivalent to a Nyquistconverter operating at 250 Megasamples per second), an effective resolution of 8.3 bitswas obtained.

Staff supported

S. Jaganathan (Ph.D. 2000)

Sundararajan Krishnan (Ph.D. 2002)

Thomas Mathew (Ph.D. 2001)

C. Serhan (M.S. 2000)

17

Publications associated with contract1 1999 M.J.W. Rodwell, Q. Lee, D. Mensa, J. Eleventh International Conference

Guthrie, Y. Betser, S.C. Martin, R.P. Conference on Indium PaperSmith, S. Jaganathan, T. Mathew, P. Phosphide and Related (Invited)Krishnan, C. Serhan, and S. Long, Materials, Davos,"Transferred-Substrate Heterojunction Switzerland, pp. 1-6,Bipolar Transistor Integrated Circuit May 16-20.Technology."

2. 2000 S. Jaganathan, D. Mensa, T. Mathew, 22nd Annual IEEE GaAS ConferenceY. Betser, S. Krishnan. Y. Wei. D. Scott, IC Symposium 2000, PaperM. Urteaga, M. Rodwell, "A 18 GHz Seattle, WA, NovemberContinuous Time I - A Modulator 5-8.Implemented in InP Transferred SubstrateHBT Technology."

3. 2001 M. Urteaga, D. Scott, M. Dahlstrom, Y. 2001 GOMAC ConferenceBetser, S. Lee, S. Krishnan, T. Mathew. S. Conference, San PaperJaganathan. Y. Wei, M.J.W. Rodwell, Antonio, Texas, March 5- (Invited)"Ultra High Speed Heterojunction Bipolar 8.Transistor Technology."

4. 2001 M. Urteaga, D. Scott, M. Dahlstrom, Y. 2001 GOMAC ConferenceBetser, S. Lee, S. Krishnan, T. Mathew. S. Conference, San PaperJaganathan. Y. Wei, M.J.W. Rodwell, Antonio, Texas, March 5- (Invited)"Ultra High Speed Heterojunction Bipolar 8.Transistor Technology."

5. 2001 M.J.W. Rodwell, M. Urteaga, Y. Betser, International Journal of Journal PaperD. Scott, M. Dahlstrom, S. Lee, S. High Speed ElectronicsKrishnan, T. Mathew. S. Jaganathan. Y. and Systems, Vol. 11,Wei, D. Mensa, J. Guthrie, R. Pullela, Q. No. 1, pp. 159-215.Lee, B. Agarwal, U. Bhattacharya, S.Long "Scaling of InGaAs/InAIAs HBTsfor High Speed Mixed-Signal and mm-Wave ICs"

6. 2001 S. Jaganathan, S. Krishnan, D. Mensa, T. IEEE Journal of Solid Journal PaperMathew, Y.Betser, Y. Wei, D. Scott, State Circuits, Vol. 36,M. Urteaga, M. Rodwell. "An 18 GHz No. 9, pp. 1343-1350,continuous time sigma-delta analog-digital September.converter implemented in InP transferredsubstrate HBT technology"

7. 2001 M. Rodwell, S. Long, M. Urteaga, T. 2 8/h International ConferenceMathew, D. Scott, S. Lee, Y. M. Kim, Y. Symposium on PaperWei, N. Parthasarathy, M. Dahlstrom, H.J. Compound (Invited)Kim, Z. Griffith, "High Speed InP-Based Semiconductors 2001Heterojunction Bipolar Transistors." (1SCS2001), Komaba

Campus, University ofTokyo, October 1-4.

18

8. 2001 M.J.W. Rodwell, Miguel Urteaga, D. IEEE Transactions on Journal PaperMensa, Q. Lee, J. Guthrie, Y. Betser, S.C. Electron Devices, Vol. (Invited)Martin, R.P. Smith, S. Jaganathan, T. 48, No. 11, p. 2606-2624,Mathew, P. Krishnan, November.S. Long, R. Pullela, B. Agarwal, U.Bhattacharya, L. Samoska, Denis Scott,Mattias Dahlstrom, "Submicron Scaling ofHBTs."

9. 2003 Sundararajan Krishnan, Dennis Scott, To be published ConferenceMiguel Urteaga, Zachary Griffith, Yun International Microwave PaperWei, Mattias Dahlstrom, Navin Symposium, Philidelphia,Parthasarathy, Mark Rodwell, "An 8-GHz June 8-10.Continuous-Time Sigma-Delta Analog-Digital Converter in an InP-based DHBTTechnology."

10 2003 Sundararajan Krishnan, Dennis Scott, Submitted to IEEE-MTT JournalMiguel Urteaga, Zachary Griffith, Yun transactions PaperWei, Mattias Dahlstrom, NavinParthasarathy, Mark Rodwell, "An 8-GHzContinuous-Time Sigma-Delta Analog-Digital Converter in an InP-based DHBTTechnology."

19

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