Repaso examen 2mtoledo/4207/F2011/review_ex2.pdfQ p1 and Q p2 are cuto and can be removed from the...

Repaso examen 2INEL 4207 - Fall 2011

Monday, October 17, 11

Subjects

• Pass-transistor Logic / Transmission gates

• Dynamic / Domino Logic

• Emitter-coupled Logic

• BiCMOS


Sources• Textbook’s 5th ed.:

◦ PTL: 10.5 ◦ Dynamic/Domino Logic: 10.6 ◦ ECL: 11.7

◦ BiCMOS: 11.8

• 6th Ed.: chapter 15th (int’l), 14th (USA)

• Slides and examples on courses’ web page

• Your lecture notes

• Practice problems: 1, 2, 5, 6, 8-10, 12-14, 17, 21, 24-27, 30, 35, 36 & 39


Figure 15.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the

function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).

Pass-Transistor Logic


Figure 15.6 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.


Figure 15.7 A basic design requirement of PTL circuits is that every node have, at all times, a low resistancepath to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in

(b) through switch S2.


Figure 15.8

For NMOS switch, load capacitor charges to vC - Vt

Body effect -> Vt


NMOS switch discharges capacitor completely


For PMOS switch, C charges to vC and discharges to Vt


Figure 15.11 The CMOS transmission gate and its circuit symbol.

CMOS switch - C charges to vC and discharges to 0


Figure 15.12


Transmission gate resistance empirical for-mula (for submicron technologies) (eq. 15.36)

RTG =12.5

(W/L)nk�


Figure 15.14 (a) A transmission gate connects the output of a CMOS inverter to the input of another. (b) Equivalent circuit for the purpose of analyzing the propagation delay of the circuit in (a).


Figure 15.15 A three-section RC ladder network.

Elmore delay formula (eq. 15.37):

tp = 0.69 [C1R1 + C2 (R1 + R2) + C3 (R1 + R2 + R3)]


Figure 15.16 Realization of a two-to-one multiplexer using pass-transistor logic.


Figure 15.17 Realization of the XOR function using pass-transistor logic.


Figure 15.18 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic, or CPL. Note that both the output function and its complement are generated.


Figure 15.19 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.

Dynamic / Domino Logic


Figure 15.20 Circuits for Example.

Assume VDD = 1.8V , Vt = 0.5V , µnCox = 4µpCox = 0.3mA/V 2, (W/L)n =

0.27µm/0.18µm (including Qe), (W/L)p = 0.54µm/0.18µm (for Qp), CL =

20fF .

a) For the pre-charge operation, with Qp’s gate at 0V and if CL is fully

discharged at t = 0, find the time for vY to rise from 10% to 90% of VDD.

b) For A = B = C = D = 1, find tPHL


Figure 15.21 (a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge sharing problem at the expense of static power dissipation.


Figure 15.22 Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase CL2 will partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction.

Figure E 15.10

Cascading dynamiclogic gates

By the time vY1 drops to Vt, CL2 can loose a significant amount of charge causing vY2 to

can be significantly reduced.


Consider the circuit as the evaluation phase begins: at t = 0, vY 1 = vY 2 =VDD and v� = vA = VDD. Qp1 and Qp2 are cuto⇥ and can be removed fromthe equivalent circuit. Replace series combinations of Q1 � Qe1 and Q2 � Qe2

by equivalent devices.Consider the interval �t during which vY 1 falls from VDD to Vt, at which

time Qeq2 turns o⇥ and CL2 stops discharging. Assume (W/L)n = 4µm/2µmand CL1 = CL2 = 40fF . Assume VDD = 5V , Vt0 = 1V , µnCox = 2.5µpCox =50µA/V 2, (W/L)n = 4µm/2µm.

Find

a) (W/L)eq1 and (W/L)eq2.

b) an average iD1, iD1,av, from iD1(vY 1 = VDD) and iD1(vY 1 = Vt).

c) �t using iD1,av

d) iD2,av obtained when vY 1 is halfway through its excursion (i.e. vY 1 = 3V ).Hint: Qeq2 is in saturation.

e) Use �t found in (c) and iD2,av to estimate the reduction in vY 2 and itsfinal value.


Figure E 15.10


Figure 15.23 The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0-to-1 transition (to VDD).


Figure 15.24 (a) Two single-input Domino CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase.


Figure 15.25 The basic element of ECL is the differential pair. Here, VR is a reference voltage.

ECL


Figure E15.12


Figure 15.26 Basic circuit of the ECL 10K logic-gate family.


Figure 15.27 The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the “ringing” that would otherwise corrupt the logic signals. (See Section 15.4.6.)


Figure 15.28 Simplified version of the ECL gate for the purpose of finding transfer characteristics.


Figure 15.30 Circuit for determining VOH.


fig. 15.32 (international, 6th edition)


Figure 15.36 The wired-OR capability of ECL.


Name: INEL4207 Digital Electronics - A2

Student #: Sec.: December 21, 2010

This exam has 3 problems. Each problem counts for 1/3 of the exam grade.

1. For the ECL inverter shown in the following sketch, the high voltage level is VH = −1.7V andthe average power dissipated when the input is high 50% of the time is P = 5mW . Determinethe source’s current IEE, the low voltage level VL, the reference voltage level VREF and thevalue of resistance R3.

-5.2V-3.3V

VREFvin

2k�

2k�

IEE

Q1 Q2

Q3

voutR3


2. El siguiente diagrama muestra una red de transmision:

+5V

+5V +5V +5V

a bc

CL

Los parametros son: VT0 = 0.75V , γ = 0.55√

V , 2φF = 0.6V , y Kn = 100µA/V 2.

a) (15 puntos) Determine el voltaje en los nodos a, b, y c si se desprecia el body effect.b) (20 puntos) Repita la parte (a) tomando en cuenta el ”body effect.”Debe analizar el circuito y

mostrar el procedimiento que conduce al resultado.


Name: Student number:

2. Find VL, VH and VREF for the following circuit. Neglect base currents and assumeVBE = 0.7V if a transistor is ON. (25 points)

-2V-5V

1kΩ

1kΩ

VREFvINvOUT

4kΩ

Q1

Q2


Figure 15.37 Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of QN and QP of the CMOS inverter. (b) The circuit in (a) can be thought of as utilizing these composite devices.

(c) To reduce the turn-off times of Q1 and Q2, “bleeder resistors” R1 and R2 are added. (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R1 to the output node.

BiCMOS


Figure 15.38 Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances present at the output node.


Figure 15.39 A BiCMOS two-input NAND gate.


The diagram shows the charging of a load capacitance C by the pull-up section of a BiCMOS.

Find tPLH (the time it takes vO to reach VDD/2 if the cap is initially discharged) if VDD = 5V, vbe = 0.7V, kP = 100 µA/V2, C = 1pF and R1 = 20kΩ.


The diagram shows the charging of a load capacitance C by the pull-up section of a BiCMOS.

Find tPLH (the time it takes vO to reach VDD/2 if the cap is initially discharged) if VDD = 5V, vbe = 0.7V, kP = 100 µA/V2, C = 1pF and R1 = 20kΩ.

i = iE + iR1

i = (� + 1) (iD � iR1) + iR1

= (� + 1)iD � �iR1

i = CdvOdt

The average current method can be used to estimate tPLH .


Repaso examen 2mtoledo/4207/F2011/review_ex2.pdfQ p1 and Q p2 are cuto and can be removed from the...

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