Fundamentals of Computer SystemsSequential Logic

Martha A. Kim

Columbia University

Fall 2014

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Bistable Elements

Q Q

Q

Q

Equivalent circuits; right is more traditional.

Two stable states:

0

1

1

0

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RS Latch

R

S

Q

Q

Q

Q

R

S

R S Q Q

0 00 11 01 1

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RS Latch

R

S

Q

Q

0

1

1

0

Q

Q

R

S

R S Q Q

0 00 1 1 0 Set (Q = 1)1 01 1

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RS Latch

R

S

Q

Q

1

0

0

1

Q

Q

R

S

R S Q Q

0 00 1 1 0 Set (Q = 1)1 0 0 1 Reset (Q = 0)1 1

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RS Latch

R

S

Q

Q

0

0

Q

Q

(0+Q) = Q

(0+Q) = Q

Q

Q

R

S

R S Q Q

0 0 Q Q Hold previous value0 1 1 0 Set (Q = 1)1 0 0 1 Reset (Q = 0)1 1

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RS Latch

R

S

Q

Q

1

1

0

0

Q

Q

R

S

R S Q Q

0 0 Q Q Hold previous value0 1 1 0 Set (Q = 1)1 0 0 1 Reset (Q = 0)1 1 0 0 Bad. Do not use.

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RS Latch

S

R

Q

Q

Q

Q

S

R

R S Q Q

0 0 1 1 Bad. Do not use.0 1 0 1 Reset (Q = 0)1 0 1 0 Set (Q = 1)1 1 Q Q Hold previous value

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D Latch

Q

Q

D

CQ

Q

D

C

C D Q Q

0 X Q Q1 0 0 11 1 1 0

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A Challenge: Build a traffic light controller

Want the lights to cycle green-yellow-red.

DC

Q

DC

Q

DC

Q

R

Y

G

Does this work?

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Positive-Edge-Triggered D Flip-Flop

Master Slave

DC

Q DC

QDD’ Q

CM CS

C

D Q

C

D

CM

D′

CS

Q

transparent

opaque

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Positive-Edge-Triggered D Flip-Flop

Master Slave

DC

Q DC

QDD’ Q

CM CS

C

D Q

C

D

CM

D′

CS

Q

transparent

opaque

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Positive-Edge-Triggered D Flip-Flop

Master Slave

DC

Q DC

QDD’ Q

CM CS

C

D Q

C

D

CM

D′

CS

Q

transparent

opaque

opaque

transparent

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Positive-Edge-Triggered D Flip-Flop

Master Slave

DC

Q DC

QDD’ Q

CM CS

C

D Q

C

D

CM

D′

CS

Q

transparent

opaque

opaque

transparent

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Positive-Edge-Triggered D Flip-Flop

Master Slave

DC

Q DC

QDD’ Q

CM CS

C

D Q

C

D

CM

D′

CS

Q

transparent

opaque

opaque

transparent

transparent

opaque

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Positive-Edge-Triggered D Flip-Flop

Master Slave

DC

Q DC

QDD’ Q

CM CS

C

D Q

C

D

CM

D′

CS

Q

transparent

opaque

opaque

transparent

transparent

opaque

opaque

transparent

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The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.

D Q

D Q

D Q

CLK

R

Y

G

CLK

R

Y

G

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The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.

D Q

D Q

D Q

CLK

R

Y

G

CLK

R

Y

G

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The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.

D Q

D Q

D Q

CLK

R

Y

G

CLK

R

Y

G

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The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.

D Q

D Q

D Q

CLK

R

Y

G

CLK

R

Y

G

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The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.

D Q

D Q

D Q

CLK

R

Y

G

CLK

R

Y

G

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The Traffic Light Controller with Reset

D Q

D Q

D Q

CLK

RESET

R

Y

G

CLK

RESET

R

Y

G

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The Traffic Light Controller with Reset

D Q

D Q

D Q

CLK

RESET

R

Y

G

CLK

RESET

R

Y

G

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The Traffic Light Controller with Reset

D Q

D Q

D Q

CLK

RESET

R

Y

G

CLK

RESET

R

Y

G

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The Traffic Light Controller with Reset

D Q

D Q

D Q

CLK

RESET

R

Y

G

CLK

RESET

R

Y

G

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The Traffic Light Controller with Reset

D Q

D Q

D Q

CLK

RESET

R

Y

G

CLK

RESET

R

Y

G

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The Traffic Light Controller with Reset

D Q

D Q

D Q

CLK

RESET

R

Y

G

CLK

RESET

R

Y

G

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D Flip-Flop with Enable

D Q Q01D

C

E

C E D Q

↑ 0 X Q↑ 1 0 0↑ 1 1 10 X X Q1 X X Q

D QEC

DQ

What’s wrong with thissolution?

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Asynchronous Preset/Clear

D QPRE

CLR

CLK

D

PRE

CLR

Q

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The Traffic Light Controller w/ Async. Reset

D QPRE

CLR

D QPRE

CLR

D QPRE

CLR

CLKR

Y

G

RESET

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The Synchronous Digital Logic Paradigm

Gates and Dflip-flops only

Each flip-flopdriven by thesame clock

Every cyclicpath containsat least oneflip-flop

CLSTATE

NEXT STATE

INPUTS OUTPUTS

CLOCK

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Cool Sequential Circuits: Shift Registers

A

Q0 Q1 Q2

Q3

CLK

A Q0Q1Q2Q3

0 X X X X1 0 X X X1 1 0 X X0 1 1 0 X1 0 1 1 00 1 0 1 10 0 1 0 10 0 0 1 01 0 0 0 10 1 0 0 0

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Universal Shift Register

S1S0

0123

D0Q0

0123

D1Q1

0123

D2Q2

0123

D3Q3

CLK

R

L

S1 S0 Q3 Q2 Q1 Q0

0 0 R Q3 Q2 Q10 1 D3 D2 D1 D01 0 Q3 Q2 Q1 Q01 1 Q2 Q1 Q0 L

S1 S0 Operation

0 0 Shift right0 1 Load1 0 Hold1 1 Shift left

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Cool Sequential Circuits: Counters

Cycle through sequences of numbers, e.g.,

00 01 10 11

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Flip-Flop Timing

CLK

D

Q

tsu

Setup Time: Time beforethe clock edge after whichthe data may not change

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Flip-Flop Timing

CLK

D

Q

tsu th

Setup Time: Time beforethe clock edge after whichthe data may not change

Hold Time: Time after theclock edge after whichthe data may change

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Flip-Flop Timing

CLK

D

Q

tsu th

tp(min)

Setup Time: Time beforethe clock edge after whichthe data may not change

Hold Time: Time after theclock edge after whichthe data may change

Minimum PropagationDelay: Time fromclock edge to when Qmight start changing

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Flip-Flop Timing

CLK

D

Q

tsu th

tp(min)

tp(max)

Setup Time: Time beforethe clock edge after whichthe data may not change

Hold Time: Time after theclock edge after whichthe data may change

Minimum PropagationDelay: Time fromclock edge to when Qmight start changing

MaximumPropagation Delay:Time from clock edgeto when Qguaranteed stable

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Timing in Synchronous Circuits

CL· · · · · ·Q D

CLK

CLK

Q

D

tc

tc: Clock period. E.g., 10 ns for a 100 MHz clock

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Timing in Synchronous Circuits

CL· · · · · ·Q D

CLK

CLK

Q

D

tp(min,FF) tp(min,CL)

Sufficient Hold Time?

Hold time constraint: how soon after the clock edge canD start changing? Min. FF delay + min. logic delay

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Timing in Synchronous Circuits

CL· · · · · ·Q D

CLK

CLK

Q

D

tp(max,FF)tp(max,CL)

Sufficient Setup Time?

Setup time constraint: when before the clock edge is Dguaranteed stable? Max. FF delay + max. logic delay

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Clock Skew: What Really Happens

CL· · · · · ·Q D

CLK1

CLK

CLK2

CLK1

CLK2

Q

Dtp(min,FF) tp(min,CL)

tskew

Sufficient Hold Time?

CLK2 arrives late: clock skew reduces hold time

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Clock Skew: What Really Happens

CL· · · · · ·Q D

CLK1

CLK

CLK2

CLK1

CLK2

Q

Dtp(max,FF) tp(max,CL)

tskew

Sufficient Setup Time?

CLK2 arrives early: clock skew reduces setup time

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