Reiner Hartenstein University of Kaiserslautern

Enabling Technologies for

Reconfigurable Computing

Enabling Technologies for Reconfigurable Computing Part 4:FPGAs: recent developments

Wednesday, November 21, 16.00 – 17.30 hrs.

Reiner Hartenstein

University ofKaiserslautern

November 21, 2001, Tampere, Finland

© 2001, [email protected] http://www.fpl.uni-kl.de2

University of Kaiserslautern

Xputer Lab

Schedule

time slot

08.30 – 10.00

Reconfigurable Computing (RC)

10.00 – 10.30

coffee break

10.30 – 12.00

Stream-based Computing for RC

12.00 – 14.00

lunch break

14.00 – 15.30

Resources for RC

15.30 – 16.00

coffee break

16.00 – 17.30

FPGAs: recent developments



Xputer Lab>> Configware Market

• Configware Market

• FPGA Market

• Embedded Systems (Co-Design)

• Hardwired IP Cores on Board

• Run-Time Reconfiguration (RTR)

• Rapid Prototyping & ASIC Emulation

• Evolvable Hardware (EH)

• Academic Expertise

• ASICs dead

• Soft CPU

• HLLs

• Problems to be solved



Xputer LabConfigware heading for mainstream

• Configware market taking off for mainstream• FPGA-based designs more complex, even SoC• No design productivity and quality without good configware

libraries (soft IP cores) from various application areas. • Growing no. of independent configware houses (soft IP core

vendors) and design services • AllianceCORE & Reference Design Alliance• Currently the top FPGA vendors are the key innovators and

meet most configware demand.



Xputer Labbleeding edge designs

•Infinite amount of gates not yet available on a chip

•3 mio gates (10 mio in 2003 ?) far away from "infinite"

•Bleeding edge designs only with sophisticated EDA tools

•Excessive optimization needed

•Hardware epertise is inevitable for the designer.

•improve and simplify the design flow the user

•provide rich configware libraries of soft IP cores,

•control appl., networking, wireless telecommunication, data communication, embedded and consumer markets.



Xputer LabConfigware (soft IP Products)

• For libraries, creation and reuse of configware

• To search for IPs see: List of all available IP

• The AllianceCORE program is a cooperation between Xilinx and third-party core developers

• The Xilinx Reference Design Alliance Program

• The Xilinx University Program

• LogiCORE soft IP with LogiCORE PCI Interface.

• Consultants



Xputer LabEDA as the Key Enabler (major EDA vendors)

•Select EDA quality / productivity, not FPGA architectures•EDA often has massive software quality problems •Customer: highest priority EDA center of excellence

– collecting EDA expertise and EDA user experience– to assemble best possible tool environments – for optimum support design teams– to cope with interoperability problems – to keep track with the EDA scene as a rapidly moving target

•being fabless, FPGA vendors spend most qualified manpower in development of EDA, IP cores, applications , support

•Xilinx and Altera are morphing into EDA companies.



Xputer LabOS for FPGAs

• separate EDA software market, comparable to the compiler / OS market in computers,

• Cadence, Mentor, Synopsys just jumped in.

• < 5% Xilinx / Altera income from EDA SW

• Changing EDA Tools Market • Major configware EDA vendors – Altera – Cadence – Mentor Graphics – Synopsys– Xilinx



Xputer LabEDA Software for Xilinx

•Full design flow from Cadence, Mentor, & Synopsys

•Xilinx Software AllianceEDA Program: –Alliance Series Development System.–Foundation Series Development Systems.–Xilinx Foundation Series ISE (Integrated Synthesis Environment)–free WebPOWERED SW w. WebFitter & WebPACK-ISE–StateCAD XE and HDL Bencher–Foundation Base Express–Foundation ISE Base Express



Xputer LabFoundation ISE Base Express

• ModelSim Xilinx Edition (ModelSim XE)

• Forge Compiler

• Modular Design

• Chipscope ILA

• The Xilinx System Generator

• XPower

• JBits SDK

• The Xilinx XtremeDSP Initiative

• MathWorks / Xilinx Alliance

• System Generator

• Wind River / Xilinx alliance



Xputer LabAltera EDA

•Altera was founded in June 1983

•EDA: synthesis, place & route, and, verification

•Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families

•MAX+PLUS II: FLEX, ACEX & MAX families

•Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity deliver a design design software to support Altera SOPC solutions.

•Mentor: only EDA vendor w. complete design environment f. APEX II incl. IP, design capture, simulation, synthesis, and h/s co-verification

•Configware: Altera offers over a hundred IP cores

•Third party IP core design services and consultants



Xputer LabCadence

•FPGA Designer: top-down FPGA design system,

•high-level mapping, architecture-specific optimization,

•Verilog,VHDL, schematic-level design entry.

•Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer

•FPGAs simulated by themselves using Cadence's Verilog-XL or Leapfrog VHDL simulators and

•simulated w. rest of the system design w. Logic Workbench board/system verification env‘ment.

•Libraries for the leading FPGA manufacturers.



Xputer LabMentor Graphics

• System Design and Verification.

• PCB design and analysis:

• IC Design and Verification

• shifts ASIC design flow to FPGAs (Altera, Xilinx) – by FPGA Advantage with IP support – by ModuleWare, – Xilinx CORE Generator – Altera MegaWizard integration,



Xputer LabSynopsys

• FPGA Compiler II

• Version of ASIC Design Compiler Ultra

• Block Level Incremental Synthesis (BLIS)

• ASIC <-> FPGA migration

• Actel, Altera, Atmel, Cypress, Lattice, Lucent, Quicklogic, Triscend, Xilinx



Xputer Lab>> FPGA Market


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer LabTop 4 PLD Manufacturers 2000

Xilinx42%

Altera37%

Lattice15%

Actel6%

Top 4 PLD Manufacturers 2000$3.7 Bio



Xputer LabFPGA market 1998 / 1999

3832Atmel8

4030Quicklogic7

4341Cypress6

120100Lucent5

172154Actel4

410206Lattice3

837654Altera2

899629 Xilinx1

19991998

global sales (mio $)1999 rank

Source: IC Insights Inc.

Meanwhile,

Xilinx acquired Philips' MOS

PLD business,

Lattice purchased

Vantis..



Xputer Lab.... into every application

• [Dataquest] PLD market > $7 billion by 2003.

• „ fastest growing segment of semiconductor market.“

• IP reuse and "pre-fabricated" components for the efficiency of design and use for PLDs

• FPGAs are going into every type of application.



Xputer Lab

.... going into every type of application[Gordon Bell]



Xputer LabXilinx

•fabless FPGA semi vendor, San Jose, Ca, founded 1984

•key patents on FPGAs (expiring in a few years)

•Fortune 2001: No. 14 Best Company to work for in (intel: no. 42, hp no. 64, TI no. 65).

•DARPA grant (Nov‘99) to develop Jbits API tools for internet reconfigurable / upgradable logic (w. VT)

•Less brilliant early/mid 90ies (president Curt Wozniak): 1995 market share from 84% down to 62% [Dataquest]

•As designs get larger, Xilinx losed its advantage (bugfixes did not require to burn new chips)

•meanwhile, weeks of expensive debug time needed



Xputer LabXilinx Flexware

• Virtex, Virtex-II, first w. 1 mio system gates. – Virtex-E series > 3 mio system gates.

• Virtex-EM on a copper process & addit. on chip memory f. network switch appl.

• The Virtex XCV3200E > 3 million gates, 0.15-micron technology,

• Spartan, Spartan-XL, Spartan-II– for low-cost, high volume applications as ASIC replacements– Multiple I/O standards, on-chip block RAM, digital delay lock loops – eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers

• XC4000XV, XC4000XL/XLA, CPLD: low-cost families – rapid development, longer system life, robust field upgradability– support In-System Programming (ISP), in-board debugging,– test during manufacturing, field upgrades, full JTAG compliant

interface

• CoolRunner: low power, high speed/density, standby mode.• Military & Aerospace: QPRO high-reliability QML certified• Configuration Storage Devices



Xputer LabAltera Flexware

• Newer families: APEX 20KE, APEX 20KC, APEX II, MAX 7000B, ACEX 1K, Excalibur, Mercury families.

– Apex EP20K1500E (0.18-µ), up to 2.4 mio system gates,

– APEX II (all-copper 0.13-µ) f. data path applications, supports many I/O standards. 1-Gbps True-LVDS performance

– wQ2001, an ARM-based Excalibur device

• Altera mainstream: MAX 7000A, 3000A; FLEX 6000, 10KA, 10KE; APEX 20K families.

• Mature and other : Classic, MAX 7000, 7000S, 9000; FLEX 8000, 10K families.



Xputer LabTriscend CSoC

Digital Filter Display Interface

Viterbi A/D Interface

CSI Socket

ARM

Configurable system logic

Configurable System Interconnect (CSI) Bus

Other System ResourcesMemory

[Kean]



Xputer Lab>> Embedded Systems (Co-Design)


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs


© 2001, [email protected] http://www.fpl.uni-kl.de


Xputer Lab

25

Goal: away from complex design flow

Placeand

Route NetlistSchematics/

HDL Netlister

Bitstream

CompilerHLL

[à la S. Guccione]



Xputer Lab

26

Overcome traditional separate design flow

UserCode Compiler Executable

Netlister NetlistPlaceand

Route..

Bitstream

Schematics/HDL

HLL Compiler

[à la S. Guccione]



Xputer Lab

27

Overcome traditional co-processing design separate flow -> JBits Design

Flow

UserJavaCode

JavaCompiler

JBitsJBitsAPI

Executable

UserCode Compiler Executable

Netlister NetlistPlaceand

Route..

Bitstream

Schematics/HDL

[à la S. Guccione]



Xputer Lab

28

Embedded hardw. CPU & memory cores on chip.

HLL Compiler

CPUcore

FPGA core

Memorycore

HLL Compiler

[à la S. Guccione]



Xputer Labnew directions in application

development• new directions in application development.

• aut. partitioning compilers: designer productivity

• like CoDe-X (Jürgen Becker, Univ. of Karlsruhe),

• supports Run-Time Reconfiguration (RTR), a key enabler of error handling and fault correction by partial re-routing the FPGA at run time, as well as remote patching for upgrading, remote debugging, and remote repair by reconfiguration - even over the internet.



Xputer Lab>> Run-Time Reconfiguration

(RTR) • Configware Market

• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer Lab

31

CPU use for configuration management

• on-board microprocessor CPU is available anyhow - even along with a little RTOS

• use this CPU for configuration management

CompilerHLL

RTR System Design



Xputer Lab

32

hard CPU & memory core on same chip

CPUcore

FPGA core

Memorycore

CompilerHLL

CompilerHLL

RTR System Design



Xputer Lab

33

Converging factors for RTR

UserJavaCode

JavaCompiler

JBitsJBitsAPI

Executable

•Converging factors make RTR based system design viable

•1) million gate FPGA devices and co-processing with standard microprocessors are commonplace

•direct implementation of complex algorithms in FPGAs.

•This alone has already revolutionized FPGA design.

•2) new tools like Xilinx Jbits software tool suite directly support coprocessing and RTR.



Xputer LabRTR

•divides application into a series of sequentially executed stages, each implemented as a separate execution module.

•Partial RTR partitions these stages into finer-grain sub-modules to be swapped in as needed. •Without RTR, all conf. platforms just ASIC emulators. •needs a new kind of application development environments. •directly support development and debugging of RTR appl.•essential for the advancement of configurable computing•will also heavily influence the future system organization•Xilinx, VT, BYU work on run-time kernels, run-time support, RTR debugging tools and other associated tools.

•smaller, faster circuits, simplified hardware interfacing, fewer IOBs; smaller, cheaper packages, simplified software interfaces.



Xputer LabRun-time Mapping

•run-time reconfigurable are: Xilinx VIRTEX FPGA family•RAs being part of Chameleon CS2000 series systems •Using such devices changes many of the basic assumptions in the HW/SW co-design process:

•host/RL interaction is dynamic, needs a tiny OS like eBIOS, also to organize RL reconfiguration under host control

•typical goal is minimization of reconfiguration latency (especially important in communication processors), to hide configuration loading latency, and,

•Scheduling to find ’best’ schedule for eBIOS calls (C~side).



Xputer Lab>> Rapid Prototyping & ASIC

Emulation


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer LabASIC emulation: a new business model ?

•ASIC emulation / Rapid Prototyping: to replace simulation

•Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor)

•from rack to board to chip (from other vendors, e. g. Virtex and VirtexE family (emulate up to 3 million gates)

•Easy configuration using SmartMedia FLASH cards

•ASIC emulators will become obsolete within years

•By RTR: in-circuit execution debugging instead of emulation



Xputer Lab>> Evolvable Hardware (EH)


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer LabEH, EM, ...

•"Evolvable Hardware" (EH), "Evolutionary Methods" (EM), „digital DANN“, "Darwinistic Methods", and biologically inspired electronic systems

•new research area, also a new application area of FPGAs

•revival of cybernetics or bionics: stimulated by technology

•„evolutionary“ and „DNA“ metaphor create awareness

•EM sucks, also thru mushrooming funds in the EU, in Japan, Korea, and the USA

•EM-related international conference series are in their stormy visionary phase, like EH, ICES, EuroGP, GP, CEC, GECCO, EvoWorkshops, MAPLD, ICGA



Xputer LabEH, EM, ...

•Shake-out phenomena expected, like in the past with „Artificial Intelligence“

•should be considered as a specialized EDA scene, focusing on theoretical issues.

•Genetic algorithms suck - often replacable by more efficient ones from EDA

• It is recommendable to set-up an interwoven competence in both scenes, EM scene and the highly commercialized EDA scene

•EH should be done by EDA people, rather than EM freaks.



Xputer Lab>> Academic Expertise


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer LabBRASS (1)

•UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek

•The Pleiades Project, Prof. Jan Rabaey, ultra-low power high-performance multimedia computing through reconfiguration of heterogeneous system modules, reducing energy by overhead elimination, programmability at just right granularity, parallellism, pipelining, dynamic voltage scaling.

•Garp integrates processor and FPGA; dev. in parallel w. compiler - software compile techniques (VLIW SW pipelining): simple pipelining schema f. broad class of loops.

•SCORE, a stream-based computation model - a unifying computational model. Fast Mapping for Datapaths: by a tree-parsing compiler tool for datapath module mapping



Xputer LabBRASS (2)

•HSRA. new FPGA (& related tools) supports pipelining, w. retiming capable CLB architecture, implemented in a 0.4um DRAM process supporting 250MHz operation

•OOCG. Object Oriented Circuit-Generators in Java

•MESCAL (GSRC), the goal is: to provide a programmer's model and software development environment for efficient implementation of an interesting set of applications onto a family of fully-programmable architectures / microarchitectures.



Xputer LabBerkeley claiming (1)

•SCORE, a stream-based computation model: the BRASS group claims having solved the problem of primary impediment to wide-spread reconfigurable computing, by a unifying computational model.

•Remark: clean stream-based model introduced ~1980: Systolic Array

•1995: Rainer Kress. Introduces reconfigurable stream-based model

• Fast Mapping for Datapaths (SCORE): BRASS claims having introduced 1998 the first tree-parsing compiler tool for datapath module mapping ." Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity."



Xputer LabBerkeley claiming (2)

•Remark: The DPSS (Data Path Synthesis System) using tree covering simultanous datapath placement and routing has been published in 1995 by Rainer Kress

•„Chip-in-a-Da2 Bee Project. Prof. Dr. Bob Broderson‘s „radical rethink of the ASIC design flow aimed at shortening design time, relying on stream-based DPU arrays.“ [published in 2000]

•Remark: the KressArray, a scalable rDPU array [1995] is stream-based



Xputer Lab.... Stream Processors - MSP-3

•3rd Workshop on Media and Stream Processors (MSP-3)• http://www.pdcl.eng.wayne.edu/msp01

• in conj. w. 34th Int‘l Symp. on Microarchitecture (MICRO-34) • http://www.microarch.org/micro34

•Austin, Texas, December 1-2, 2001•Topics of interest include, but are not limited to:

– Hardware/Compiler techniques for improving memory performance of media and stream-based processing

– Application-specific hardware architectures for graphics, video, audio, communications, and other media and streaming applications

– System-on-a-chip architectures for media & stream processors– Hardware/Software Co-Design of media and stream processors– and others ....



Xputer LabBerkeley: „Chip-in-a-Day“ Bee

Project

• Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting a radical rethink of the ASIC design flow aimed at shortening design time. Relying on stream-based DPU arrays (not rDPU and related EDA tools. Davis: „ „... 50x decrease in power requ. over typical TI C64X design.“

• New design flow to break up the highly iterative EDA process, allowing designers to spend more time defining the device and far less time implementing it in silicon. „... developers to start by creating data flow graphs rather than C code,„

• It is stream-based computing by DPU array (hardwired DPA)

• For hardwired and reconfigurable DPU array and rDPU array



Xputer LabStanford thru BYU

•Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs.•no activities seen other than YAFA (yet another FPGA application)•UCLA: Prof. Jason Cong, expert on FPGA architectures and R& P algorithms. 9 projects, mult. sponsors under California MICRO Program

•Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs„, a new routing architecture, architecture-aware CAD, IP-aware SPS compiler

•USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable computing: MAARC project, DRIVE project and Efficient Self-Reconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation of scalable multiprocessors.

•DEFACTO proj.: compilation - architecture-independent at all levels•MIT. MATRIX web pages removed `99. „RAW project“: a conglomerate•VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w. Prof. Brad Hutchings, BYU on programming approaches for RTR Systems

•BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware Description Language) and compilation of JHDL sources into FPGAs.



Xputer LabToronto thru Karlsruhe

•U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg.

•The group has dev. Transmogrifier C, a C compiler creating netlist for Xilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs.

•Founder of Right Track CAD Corporation acquired by Altera in 1999

•Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff Arnold) – Project Streams-C: programming FPGAs from C sources.

•Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins, methods for MPEG-4 like multimedia applications on dynamically reconfigurable platforms, & on reconf. instruction set processors.

•University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker: hardware/software co-design, reconfigurable architectures & rel. synthesis for future mobile communication systems & synthesis w.

•distributed internet-based CAD methods, partitioning co-compilers



Xputer Lab>> ASICs dead ?


• FPGA Market







• ASICs dead ?

• Soft CPU

• HLLs




Xputer Lab(When) Will FPGAs Kill ASICs?

[Jonathan Rose]

ASICs Are Already Dead

They Just Don’t Know It Yet!

My Position [Jonathan Rose]



Xputer Lab Why? [Jonathan Rose]

1. You have to fabricate an ASIC Very hard, getting harder

2. An FPGA is pre-fabricated A standard part immense economic advantages



Xputer LabMaking ASICs is Damn Difficult

[Jonathan Rose]

• Testing• Yield• Cross Talk• Noise• Leakage• Clock Tree Design• Horrible very deep submicron effects we don’t

even know about yet



Xputer LabDid I Mention Inventory? [Jonathan Rose]

• ASIC users must predict # parts– 2 or 3 months in advance!

• Never guess the Right Amount– Make Too Many – You Pay holding costs– Make Too Few – Competitor gets the

Sale

[Jonathan Rose]



Xputer Lab[Jonathan Rose] FPGAs Give You

• Instant Fabrication– Get to Market Fast– Fix ‘em quick

• Zero NRE Charges– Low Risk– Low Cost at good volume



Xputer Lab FPGAs: “Too Pricey & Too Slow ?”

[Jonathan Rose]

• Custom IC Designer Can Make Logic– 20x Faster, – 20x Smaller than Programmable

• 9 Times Out of 10– You make can the thing fast by breaking it into multiple parallel

slower pieces



Xputer LabWhat’s Wrong with This Picture?

1.Still Have to Make the Chip2.Need Two Sets of Software to Build It

– The ASIC Flow– The PLD Flow

3.Have No Idea What to Connect the PLD Pins to – Chances Are, You Are Going to Get It Wrong!

Embedded FPGA Fabric

[Jonathan Rose]

What About PLD Cores on

ASICs ?



Xputer LabWhat’s Right with This Picture!

1.Pre-Fabricated2.One CAD Tool Flow!3.Can Connect Anything to Anything

PLDs are built for general connectivity

Embedded CPU Serial Link,Analog, “etc.”

[Jonathan Rose]



Xputer Lab>> Soft CPU


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer LabFree 32 bit processor core



Xputer LabProcessors in PLDs: Excalibur

•High-Speed Processors Integrated with PLDs

ARM 922T Core

ARM 922T Core

General PurposePLD General PurposePLD

Dual-Port RAM

Dual-Port RAM

Single-Port RAM

Single-Port RAM

Available Today!Available Today!

[Jonathan Rose]



Xputer Lab

62

Soft CPU: new job for compilers

softCPU

FPGA

MemorycoreFPGA

CompilerHLL



Xputer LabSome soft CPU core examples

Spartan-II16 bit DSPDSPuva16

FLEX10K30 or EPF6016

i8080AMy80

32-bit gr1050

16-bitgr1040

Altera – Mercury

8 bitNios

Altera 22 D-MIPS

32-bit instr. set

Nios 50 MHz

Altera Mercury

16-bit instr. set

Nios

Xilinx up to 100 on one FPGA

32 bit standard RISC32 reg. by 32 LUT RAM-based reg.

MicroBlaze 125 MHz 70 D-MIPS

platformarchitecturecore

SpartanXLRISC integer Cxr16

old Xilinx FPGA Board

16-bit RISC, 2 opd. Instr.

YARD-1A

1 Flex 10K20Acorn-1

Altera, Lattice, Xilinx

8 bit CISC1Popcorn-1

Lattice 4 isp30256, 4 isp1016

12 bit DSPReliance-1

2 XILINX 3020 LCA

8 bits Instr. + ext. ROM

REGIS

200 XC4000E CLBs

CISC, 32 reg.uP1232 8-bit

ARMARM7 clone

SPARCLeon25 Mhz

platformarchitecturecore



Xputer LabNios Architecture (Altera)



Xputer Labfree DSP or Processor Cores

VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

VHDL

Mentor GraphicsVHDLanother i8051 clonei8051

Synopsys8-bit micro-controlleri8051

AMD 2910 bit sliceAMD 2910

AMD 2901 4-bit sliceAMD 2901

i8085 cloneGL85

Generic 32-bit RISC CPUDLX2

SynopsysGeneric 32-bit RISC CPUDLX

6502 compatible coreFree-6502

Xilinx XC4000A 16-bit Harvard DSP with 5 pipeline stages.

16-bit DSP

Max2PlusII+ 1 Altera 10k20small 8 bit CISCAcorn 1

1 Lattice CPLD isp3256-90Verilogsmall 8 bit CISCPopCorn 1

Viewlogic 7 Lattice CPLDsSchematic12bit DSP and peripheralsReliance 1

ImplementationLanguageDescriptionCPU core



Xputer LabFPGA CPUs in teaching and

academic research

• UCSC: 1990! • Märaldalen University,

Eskilstuna, Sweden • Chalmers University,

Göteborg, Sweden• Cornell University• Gray Research• Georgia Tech • Hiroshima City University,

Japan

• Michigan State• Universidad de

Valladolid, Spain• Virginia Tech• Washington

University, St. Louis • New Mexico Tech• UC Riverside • Tokai University, Japan



Xputer LabXilinx 10Mg, 500Mt, .12 mic



Xputer Lab

68

Soft rDPA feasible ?

rDPUArray

rDPUArray

[à la S. Guccione]



Xputer Lab

69

Array I/O examples

rDPUArray

rDPUArray

data streams, or, from / to embedded memory banks

data streams,

or,from / to

embedded memory

banks

1

10

100

1000Performance

1980 1990 2000

µProc60%/yr..

DRAM7%/yr..

Processor-MemoryPerformance Gap:(grows 50% / year)

DRAM

CPU

[à la S. Guccione]



Xputer Lab

70

HLL 2 Soft Array

Memorysoft CPU

miscellanous

soft

soft

DPUDPU

arra

y

arra

ysoft

soft

DPUDPU

arra

y

arra

y

HLL Compiler

[à la S. Guccione]



Xputer Lab

71

HLL 2 „flex“ rDPA

MemoryCPU

miscellanous

rDPU

rDPU

arra

y

arra

yrD

PUrD

PU

arra

y

arra

y

HLL Compiler

[à la S. Guccione]



Xputer Lab>> HLLs


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer Lab

73

HLLs for Hardware Design vs. System Design vs. RTR System

Design

HLL Compiler

System Design

CompilerHLL

RTR System Design[à la S. Guccione]



Xputer Lab

74


Design

HLL Compiler

System Design

CompilerHLL

RTR System Design

CompilerHLL

[à la S. Guccione]



Xputer Lab

75

CPU and memory on Chip

CPUcore

FPGA core

Memorycore

CompilerHLL

CompilerHLL

RTR System Design

[à la S. Guccione]



Xputer Lab

76

Jbit Environment

RTP CoreLibrary

JRouteAPI

DeviceSimulator

UserCode

BoardScopeDebugger

XHWIF

JBitsAPI

TCP/IP

[à la S. Guccione]



Xputer Lab

77


Design

CompilerHLL

HLL Compiler

System Design

[à la S. Guccione]



Xputer Lab

78

Embedded System Design

HLL Compiler

CPUcore

FPGA core

Memorycore

HLL Compiler

softCPU

FPGA

MemorycoreFPGA

[à la S. Guccione]



Xputer Lab>> Problems to be solved


• FPGA Market







• ASICs dead

• Soft CPU

• HLLs




Xputer LabWhy Can’t Reconfig. Software

Survive?

• Resource constraints/sizes are exposed:– to programmer– in low-level representation (netlist)

• Design revolves around device size– Algorithmic structure– Exploited parallelism



Xputer Lab

Schedule

time slot

08.30 – 10.00

Reconfigurable Computing (RC)

10.00 – 10.30

coffee break

10.30 – 12.00

Stream-based Computing for RC

12.00 – 14.00

lunch break

14.00 – 15.30

Resources for RC

15.30 – 16.00

coffee break

16.00 – 17.30

FPGAs: recent developments

17.30 end of seminar: thank you for attending

Reiner Hartenstein University of Kaiserslautern

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Transcript of Reiner Hartenstein University of Kaiserslautern