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Transcript of Reiner Hartenstein, University of Kaiserslautern, · PDF fileUniversity of Kaiserslautern...
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
Enabling Technologies for
Reconfigurable Computing
Enabling Technologies for Reconfigurable Computing Part 3: Resources for RC Wednesday, November 21, 14.00 – 15.30 hrs.
Reiner Hartenstein
University of Kaiserslautern
November 21, 2001, Tampere, Finland
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
2
Schedule
time slot
08.30 – 10.00 Reconfigurable Computing (RC)
10.00 – 10.30 coffee break
10.30 – 12.00 Stream-based Computing for RC
12.00 – 14.00 lunch break
14.00 – 15.30 Resources for RC
15.30 – 16.00 coffee break
16.00 – 17.30 FPGAs: recent developments
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
3
>> Configware Industry
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
4
Configware heading for mainstream
• Configware market taking off for mainstream • FPGA-based designs more complex, even SoC • No design productivity and quality without good
configware libraries (soft IP cores) from various application areas.
• Growing no. of independent configware houses (soft IP core vendors) and design services
• AllianceCORE & Reference Design Alliance • Currently the top FPGA vendors are the key
innovators and meet most configware demand.
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
5
OS for PLDs
• separate EDA software market, comparable to the compiler / OS market in computers,
• Cadence, Mentor, Synopsys just jumped in.
• < 5% Xilinx / Altera income from EDA SW
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
6
Xilinx Alliances
• The Software
AllianceEDA Program
• ... Xilinx Inc.'s
Foundation...
• free WebPACK
downloadable tool
palette
• The Xilinx XtremeDSP
Initiative (with Mentor
Graphics)
• MathWorks / Xilinx
Alliance.
• The Wind River / Xilinx
alliance
•#
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
7
The Software Alliance EDA Program
provides a wide
selection of EDA tools
Acugen Software,
Agilent
EEsof EDA,
Aldec,
Aptix,
Auspy Development,
Cadence,
Celoxica,
Dolphin Integration,
Elanix,
Exemplar,
Flynn Systems,
Hyperlynx,
IKOS Systems,
Innoveda,
Mentor
Graphics,
MiroTech,
Model Technoloy,
Protel International,
Simucad,
SynaptiCAD,
Synopsys,
Synplicity,
Translogic,
Virtual Computer Corporation.
helps leading EDA
vendors to integrate
Xilinx Alliance software
tightly into their tools
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
8
The Xilinx AllianceCORE program a cooperation between Xilinx and third-party core developers, to produce a broad selection
of industry-standard solutions for use in Xilinx platforms. - Partners are:
Amphion Semiconductor, Ltd. ARC Cores CAST, Inc. DELTATEC Derivation Systems, Inc. Dolphin Integration (Grenoble) Eureka Technology Inc. Frontier Design Inc. GV & Associates, Inc. inSilicon Corporation iCODING Technology Inc. Loarant Corporation Mindspeed Technologies - A Conexant Business (formerly Applied Telecom) |
MemecCore Mentor Graphics Inventra NewLogic Technologies, Inc. (Europe) NMI Electronics Paxonet Communications, Inc. Perigee, LLC Rapid Prototypes Inc. sci-worx GmbH (Hannover, Germany) SysOnChip TILAB (Telecom Italia Lab) VAutomation Virtual IP Group, Inc. XYLON.
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
9
The Xilinx Reference Design Alliance Program
The Xilinx Reference Design Alliance Program helps the development of multi-component reference designs that incorporate Xilinx devices and other semiconductors.
The designs are fully functional, but no warranties, no liability. Partners are:.
ADI Engineering Innovative Integration
JK microsystems, Inc. LYR Technologies NetLogic Microsystems
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
10
The Xilinx University Program
The Xilinx University Program provides
• Xilinx Student Edition Software, • Professor Workshops, • a Xilinx University User Group, • Presentation Materials and Lab Files, • Course Examples, • Research, • Books, etc.
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
11
Altera offers over a hundred IP cores (1)
• modulator, • synchronizer, • DDR SDRAM controller, • Hadamar transform, • interrupt controller, • Real86 16 bit microprocessor, • floating point, • FIR filter, • discrete cosine, • ATM cell processor, • and many others.
• controller, • UART, • microprocessor, • decoder, • bus control, • USB controller, • PCI bus interface, • viterbi controller, • fast Ethernet • MAC receiver or transmitter,
Altera offers over a hundred IP cores like, for example:
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
12
Altera offers over a hundred IP cores (2)
from Altera | AMIRIX Systems, Inc. Amphion Semiconductor, Ltd. Arasan Chip Systems, Inc. CAST, Inc. Digital Core Design Eureka Technology Inc. HammerCores Innocor Ktech Telecommunications, Inc. Lexra Computing Engines Mentor Graphics - Inventra
Modelware Ncomm, Inc. NewLogic Technologies Northwest Logic Nova Engineering, Inc. Palmchip Corporation Paxonet Communications PLD Applications Sciworx Simple Silicon Tensilica TurboConcept.
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
13
Altera IP core design services
Altera IP core design services are available from:
• Northwest Logic
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
14
Altera Certified Design Center (CDC) Program
Certified Design Center (CDC) Program:
• Barco Silex
• El Camino GmbH
• Excel Consultants
• Plextek
• Reflex Consulting
• Sci-worx
• Tality
• Zaiq Technologies.
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
15
The Altera Consultants Alliance Program (ACAP):
The Altera Consultants Alliance Program (ACAP): lists
•41 offices in North America and
•29 in the rest of the world.
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
16
Devlopment boards
Devlopment boards are offered from:
• Altera
• El Camino GmbH
• Gid'el Limited
• Nova Engineering, Inc.
• PLD Applications
• Princeton Technology Group
• RPA Electronics Design, LLC
• Tensilica.
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
17
Consultants and services not listed by Xilinx nor Altera (index)
Algotronix, Edinburgh,
Andraka Consulting Group
Arkham Technology, Pasadena, CA
Barco Silex, Louvain-la-Neuve, Belgium,
Bottom Line Technologies, Milford, NJ
Codelogic, Helderberg, South Africa,
Coelacanth Engineering, Norwell, MASS
Comit Systems, Inc., Santa Clara, CA
EDTN Programmable Logic Design Center
Flexibilis, Tampere, Finland,
Geoff Bostock Designs, Wiltshire, England,
Great River Technology, Alberquerque, NM,
New Horizons GB Ltd, United Kingdom,
North West Logic
Silicon System Solutions, Canterbury, Australia,
Smartech, Tampere, Finland,
Tekmosv, Austin, Texas,
The Rockland Group, Garden Valley, CA
Nick Tredennick, Los Gatos, California, Vitesse,
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
18
Consultants and services not listed by Xilinx nor Altera (1)
Algotronix, Edinburgh, Reconfigurable Computing and FPL in software radio, communications and computer security
Andraka Consulting Group high performance FPGA designs for DSP applications
Arkham Technology, Pasadena, low cost IP cores for Xilinx and Atmel, embedded processor, DSP, wireless communication, COM / CORBA / DirectX, client-server database programming, software internationalization, PCB design
Barco Silex, Louvain-la-Neuve, Belgium, IP integration boards for ASIC and FPGA, consultancy, design, sub-contracting
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
19
Consultants and services not listed by Xilinx nor Altera (2)
Bottom Line Technologies, Milford, New Jersey, FPGA design, training, designing Xilinx parts since 1985
Codelogic, Helderberg, South Africa, consulting, FPGA design services
Coelacanth Engineering, Norwell, Massachusetts, design services, test development services, in wireless communication, DSP-based instrumentation, mixed-signal ATE
Comit Systems, Inc., Santa Clara, California, DSP, ASIC, networking, embedded control in avionics -- FPGA / ASIC design and system software
EDTN Programmable Logic Design Center
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
20
Consultants and services not listed by Xilinx nor Altera (3)
FirstPass, Castle Rock, Colorado
Vitesse, ASIC design
Flexibilis, Tampere, Finland, VHDL IP cores for Xilinx products
Geoff Bostock Designs, Wiltshire, England, FPGA design services
Great River Technology, Alberquerque, New Mexico, FPGA design services in digital video and point-to-point data transmission for aerospace, military, and commercial broadcasters
New Horizons GB Ltd, United Kingdom, FPGA design and training, Xilinx specialist
North West Logic; FPGA and embedded processor design in digital communications, digital video
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
21
Consultants and services not listed by Xilinx nor Altera (4)
Silicon System Solutions, Canterbury, Australia, VHDL IP cores for the ASIC and FPGA/CPLD/EPLD markets
Smartech, Tampere, Finland, ASIC and FPGA design
Tekmosv, Austin, Texas, Multiple Designs on a Single Gate Array, HDL synthesis, design conversions, chip debug, test generation
The Rockland Group, Garden Valley, California, a TeleConsulting organization about logic design for FPGAs
Nick Tredennick, Los Gatos, California, investor and consultant
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
22
>> Terminology
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
23
Terminology
Paradigm Platform Programming
source
“von Neumann” Hardware Software
Soft Machine (w. soft datapaths)
Coarse grain
Flexware
high level
Configware
RL (FPGA etc.) fine grain Flexware netlist level
Configware
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
24
Terminology & Acronyms
• Software (SW): procedural sources* • Configware (CW): structural sources • Hardware (HW): hardwired platforms • ASIC: customizable hardwired platforms • Flexware (FW): reconfigurable platforms • FPGA: field-programmable gate array • FPL: field-programmable logic
• RC: reconfigurable computing • RL: reconfigurable logic
*) note: firmware is SW !
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
25
Stream-based Computing (2)
terms:
• DPU: datapath unit
• DPA: datapath array
• rDPU: reconfigurable DPU
• rDPA: reconfigurable DPA
• stream-based computing: using complex pipe network (super-systolic: Kress et al.)
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
26
Confusing Terminology
Computer Science and EE as well as ist R&D and applicatgion areas suffer from a babylonial confusion.
Communication not only between Computer Science and EE, but also between ist special areas, even between ist different abstrac tion levels is made difficult – mainly because of immature terminology in relation to reconfigurable circuits and their applications.
Terms are rarely standardized and often used with drastically different meanings – even within then same special area.
Often terms have been so badly coined, that they are not self-explanatory, but mesleading. A demonstratory example is the comparizon of terms used used in VHDL and Verilog.
Ideal are "intuitive" terms. But often Intuition yields the wrong idea. Whenever a new term appears in teaching, I often have to tell the students, that the term does not mean, what he believes.
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
27
Terms (1)
.
Term Meaning Example
Hardware hardwired Processor, ASIC
Flexware Reconfigurable (structurally programmable)
FPLA, FPGA, KressArray
Firmware Microprogramme (rarely used after introduction of RISC proc.)
IBM 360 Computer Family
Software procedural programs (sequentially executable by a CPU)
Word, C, OS, Compiler, etc.
Configware structural programs, soft IP cores, personalizing CPLD, FPGA, or other Flexware
for rDPA FPGA configuration, e. g. as a logic circuit, state machine, datapath, function
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
28
Terms (2)
.
Term Meaning Example
data objects of computing “data” property depends on the moment of watching
Bits, numbers, operands, results, any text (also compiler input) lists, graphs, tables, images, ...
data stream ordered, also parallel data word lists, obtained by scheduling
I/O data streams for systolic or other arrays
programming personalisation by loading programm code
procedural code or structural code: for (re)configuration
program source text or object code for programming
procedural oder structural
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
29
Terms (3)
.
Term Meaning Example
boot program simple program to enable programming - usually saved in non-volatile memory
comparable to the starter of the motor of a car
booting load and execute a boot program
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
30
Hardware Terms (1)
Term Meaning Example
machine execution unit, driven by deterministic sequencer
von Neumann machine
„dataflow machine“
not a machine, since without a deterministic sequencer (exotic concept)
(sleeping research area)
CPU Instruction Set Processor ("von Neumann”): program counter (instruction sequencer) and DPU - mode of operation: deterministically instruction-driven
ARM, Pentium core,
[à la Ingo Kreuz]
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
31
Hardware Terms (2)
Term Meaning Example
DPU data path unit, processes operands - no CPU since without sequencer - no maschine
ALU with registers, multiplexers etc.
Computer CPU with RAM and interfaces
Parallel Computer
ensemble of several Computers
Xputer deterministically data-driven Machine, (transport-triggered) - data counter(s) used instead of a program counterm
MoM architectures (Kaiserslautern)
dataflow machine
indeterministically data-driven (execution sequence unpredictable)
(sleeping research area)
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
32
Terms on Parallelism (1)
Term Meaning Example
parallelism several levels of parallelism distinguished
parallel processes, parallelism at instruction set level, pipelines,
concurrent parallel processes run on different CPUs of a parallel computer - may occasionally exchange signals or data
weather prognisis, complex simulations, etc.
ISP (instruction set parallelism)
several CPUs run in parallel by clocked synchronization
VLIW (very long instruction word) computer
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
33
Terms on Parallelism (2)
Term Meaning Example
pipelining several uniform or different DPUs running simultaneously - connected to a pipeline by buffer registers.
pipelined CPUs, pipe networks, systolic, etc.
chaining several uniform or different DPUs running simultaneously - connected to a pipeline without buffer registers
Schaltnetze, komplexe arithmetische Operatoren
Pipe network Ensemble of DPUs, also multiple pipelines, also with irregular or wild structures
systolisc arrays, stream-based computing arrays
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
34
Terms on Parallelism (3)
Term Meaning Example
Systolic Array Pipe network with only linear (straight-on, no branching), uniform pipelines (all DPUs hardwired and with same functionality) pipelines
Matrix computation, DSP, DNA sequencing, etc.
stream-based computing arrays (super-systolic arrays)
pipe network, configured before fabrication
image processing, DSP, complex functions and algorithms
(coarse grain) reconf. stream-based arrays
stream-based arrays, configurable after fabrication
KressArray
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
35
Counterparts
category property counterpart
programing mode
procedural (classical)
structural (synthesis, design) - „field-programmable“, PLA „programming“, etc.
machine: principle of operation
controlflow-driven (instruction-driven): v. Neumann
Data-driven: Xputer machine
system: principle of operation
instruction-flow-driven (parallel computer etc.)
Data-stream-based (systolisc array, DPU array, KressArray)
Set-up time (datapaths switched thru)
during run time; (instruction-driven)
before run time: FPGA (at compile time) Gate Array (at fabrication)
[à la Ingo Kreuz]
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
36
>> MoPL data-procedural language
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
37
Fundamental Ideas available (1)
• Data Sequencer Methodology
• Data-procedural Languages (Duality w. v. N.)
• ... supporting memory bandwidth optimization
• Soft Data Path Synthesis Algorithms
• Parallelizing Loop Transformation Methods
• Compilers supporting Soft Machines
• SW / CW Partitioning Co-Compilers
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
38
Fundamental Ideas available (2)
• Programming Xputers
• Similarities to programming computers
• How not to get confused by similarities
• What benefits vs. Computers ?
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
39
Programming Language Paradigms
language category Computer Languages Xputer Languages
both deterministic procedural sequencing: traceable, checkpointable
operation sequence driven by:
read next instruction, goto (instr. addr.),
jump (to instr. addr.), instr. loop, loop nesting
no parallel loops, escapes, instruction stream branching
read next data item, goto (data addr.),
jump (to data addr.), data loop, loop nesting, parallel loops, escapes, data stream branching
state register program counter data counter(s)
address computation
massive memory cycle overhead overhead avoided
Instruction fetch memory cycle overhead overhead avoided
parallel memory bank access interleaving only no restrictions
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
40
Similar Programming Language Paradigms
language category Computer Languages Xputer Languages
both deterministic procedural sequencing: traceable, checkpointable
sequencingdriven by:
read next instruction, goto (instruction addr.), jump (to instruction addr.), instruction loop, instruction loop nesting no parallel loops, instruction loop escapes, instruction stream branching
read next data object, goto (data addr.), jump (to data addr.), data loop, data loop nesting, parallel data loops, data loop escapes, data stream branching
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
41
JPEG zigzag scan pattern
x
y
EastScan is step by [1,0] end EastScan;
SouthScan is step by [0,1] endSouthScan;
-> Declarations
NorthEastScan is loop 8 times until [*,1] step by [1,-1] endloop end NorthEastScan;
SouthWestScan is loop 8 times until [1,*] step by [-1,1] endloop end SouthWestScan;
HalfZigZag is EastScan loop 3 times SouthWestScan SouthScan NorthEastScan EastScan endloop end HalfZigZag;
goto PixMap[1,1]
HalfZigZag; SouthWestScan uturn (HalfZigZag)
HalfZigZag
HalfZigZag
data counter data counter
data counter data counter
1
3
2
4
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
42
>> Xputer architecture and circuitry
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
43
GAG =
Address Generator
Generic GAG Scheme
Limit Stepper
Base Stepper
GAG
Address Stepper
B0 DA L0
A
D A L B 0
[ ] | | | |
limit
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
44
GAG: Address Stepper
GAG =
Address
Generator
Generic
+ / –
Escape
Clause End
Detect
Step Counter
=o
L A D A
init tag
A
Address endExec
maxStepCount
0 B Limit Base stepVector
[ ] | |
D A L B 0
[ ] | | | |
limit
GAG: Address Stepper
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
45
Generic Sequence Examples
a) b)
c)
d) e) f) g)
Limit Slider
Base Slider
GAG
Address Stepper
B0 DA L0
A
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
46
floor
F
address
ceiling
C
Slider Operation Demo Example
yx
B 0 L0
DLDB
DA
DB DL
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
47
MoM Xputer Architecture
rDPA Multiple RAM banks
Smart memory interface
Scan Window „Cache“
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
48
MoM Architecture Features
• Scan Cache Size adjustable at run time
• Any other shape than square supported
• 2-dimensional memory space
• Supports generic „scan patterns“
– Subject of parallel access transformations
– compare Francky Cathoor et al .
• Supports visualization
Enabling Technologies for System-on-Chip Development,
November 19-20, 2001, Tampere, Finland
http://www.cs.tut.fi/soc/
Reconfigurable Computing Architectures and Methodologies for System-on-Chip;
Reiner Hartenstein, Monday, November 19, 10:15 - 11:00 hrs.
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
49
Herz‘ MoM Xputer Architecture
Multiple RAM banks
KressArray
smart memory interface
Scan Window „Cache“
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
50
MoM Application Examples
• Image Processing
• Grid-based design rule check [1983*] – 4 by 4 word scan cache – Pattern-matching based – Our own nMOS „DPLA“ design – design rule violation pixel map automatically
generated from textual design rules – 256 M&C nMOS, 800 single metal CMOS – Speed-up > 10000 vs. Motorola 68000
*) „machine“ not yet discovered
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
51
Schedule
time slot
08.30 – 10.00 Reconfigurable Computing (RC)
10.00 – 10.30 coffee break
10.30 – 12.00 Stream-based Computingfor RC
12.00 – 14.00 lunch break
14.00 – 15.30 Resources for RC
15.30 – 16.00 coffee break
16.00 – 17.30 FPGAs: recent developments
© 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
52
>>> Coarse Grain
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