Reference Manual HelioView 1p00

7/18/2019 Reference Manual HelioView 1p00

http://slidepdf.com/reader/full/reference-manual-helioview-1p00 1/41

2013/10/29 © Macnica, Inc. 380 Stevens Ave. Suite 206

Solana Beach, CA 92075

http://www.macnica-na.com

Reference Manual

Helio ViewRevision 1.0

2013/10/29

This document describes the hardware features of the Helio View board.



Helio View

2 Reference Manual - Helio View © Macnica, Inc.

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Helio View

Reference Manual - Helio View 3© Macnica, Inc.

Index

1. Ensuring Safe Use __________________________________________________________ 5

1.1 Legend ......................................................................................... ........................................... 5

1.2 Cautions ....................................................... ................................................................. .......... 5

1.3 Manufacturer Information .......................... ................................................................. .......... 7

2. IMPORTANT INFORMATION __________________________________________________ 8

3. Unboxing _________________________________________________________________ 9

4. Introduction ______________________________________________________________ 10

4.1 Key Specifications ................................................... .............................................................. 10

4.2 Helio View Sub-Units ......................................................... ................................................... 10

4.3 Primary Component Quick-Reference ............................................................... ................... 12

4.4 Reference Designs ............................................................. ................................................... 12

5. Helio View PCB ___________________________________________________________ 14

5.1 Block Diagram ......................................................... .............................................................. 14

5.2 Physical Views ................................................................................................. ...................... 15

6. Functional Reference _______________________________________________________ 16

6.1 Altera MaxV CPLD (U10) .................................................................................... ................... 16

6.1.1 Transmit Multiplex ............................................................................................................ 17

6.1.2 Receive Multiplex ............................................................................................................. 20

6.1.3 Non-Multiplexed I/O ......................................................................................................... 23

6.2 HDMI Transmitter (U5) ................................................................ ......................................... 23

6.2.1 Video Data Format (4:2:2 YCrCb) ...................................................................................... 23

6.2.2 Low Power Mode .............................................................................................................. 24

6.2.3 I2C Configuration / Drivers ............................................................................................... 24

6.2.4 Pinout and Connectivity .................................................................................................... 24

6.3 HDMI Receiver (U13) ......................................................................................... ................... 26

6.3.1 Video Data Format (4:2:2 YCrCb) ...................................................................................... 26

6.3.2 Low Power Mode .............................................................................................................. 26

6.3.3 I2C Configuration / Drivers ............................................................................................... 26

6.3.4 Pinout and Connectivity .................................................................................................... 26

6.4 LCD Sub-Assembly ............................................................. ................................................... 28

6.4.1 Display .............................................................................................................................. 29

6.4.2 Multi-Touch Controller ..................................................................................................... 29

6.5 Connectors .................................................. ................................................................. ........ 30

6.5.1 HSMC Connector (J7) ........................................................................................................ 31



Helio View


6.5.2 HDMI TX/RX (J3, J5) .......................................................................................................... 32

6.5.3 Display Connector (J8) ...................................................................................................... 32

6.5.4 TouchPanel Connector (J9) ............................................................................................... 32

6.5.5 PicoModule Expansion Connectors (J1, J2) ....................................................................... 32

6.5.6 Power Connector (J4)........................................................................................................ 32

6.5.7 JTAG Connector (J6) .......................................................................................................... 32

6.6 Power................................................................................ .................................................... 32

6.6.1 Local Power Generation (U1, U3, U12) ............................................................................. 33

6.6.2 Remote Power Generation (U2) ....................................................................................... 33

6.6.3 Backlight Current (U9) ...................................................................................................... 34

6.6.4 Voltage Supervisor (U4) .................................................................................................... 34

6.7 Serial Management Bus ........................................................................................................ 34

6.8 Clock Generation (Y1, Y2) ....................................................................... .............................. 36

6.9 Reset Distribution (U6, U7, U8) .............................................................. .............................. 36

6.10 PushButtons .................................................................................................................... 37

6.10.1 RESET (SW2) ...................................................................................................................... 37

6.10.2 CPLD_SW1 / CPLD_SW2 (SW4/SW5) ................................................................................ 37

6.11 LEDs ............................................ ................................................................. ................... 38

7. Appendix ________________________________________________________________ 39

7.1 Restoring/Updating the Factory CPLD Image ....................................................................... 39

8. Document Revision History __________________________________________________ 41



Helio View


1. Ensuring Safe Use

Be sure to follow the instructions given in this reference manual; they are intended to prevent harm

to the user, to others, and to the unit itself.

1.1 Legend

DangerIndicates an imminent hazardous situation which if not avoided will

result in death or serious injury.

WarningIndicates a potentially hazardous situation which if not avoided could

result in death or serious injury.

CautionIndicates a potentially hazardous situation which if not avoided mayresult in minor or moderate injury or in property damage.

1.2 Cautions

Caution

Do not apply strong impacts or blows to the kit.

Doing so may cause the kit to emit heat, explode, or ignite, or the

equipment in the kit to fail or malfunction. This may also cause fire.

Do not wrap the main unit that is in use with cloth or other materials

that are likely to allow heat to build up inside the wrapping.

This will cause heat to build up inside the wrapping which may causethe main unit to ignite or malfunction.

Do not use the kit in places subject to extremely high or low

temperatures or severe temperature changes.

Doing so may cause the kit to fail or to malfunction.

Always be sure to use the kit in a temperatures ranging from 5°C to

35°C and a humidity range of 0% to 85%.

When disposing of the main unit, do not dispose of it along with general

household waste.

Throwing the main unit into fire may cause it to explode. Dispose of the

main unit following the laws, regulations, and ordinances governing

waste disposal.

Do not use the kit in places subject to extremely high or low

temperatures or severe temperature changes.

Doing so may cause the kit to fail or to malfunction.

Always be sure to use the kit in a temperatures ranging from 5°C to

35°C and a humidity range of 0% to 85%.

Do not unplug the power plug with wet or moist hands.

This might cause injuries or equipment malfunctions or failures due to

electrical shock.



Helio View


Caution(Continued from previous page)

Plug the power plug securely into the outlet.

If the power plug is not securely plugged into the outlet, it may cause

accidents involving electrical shock or fire due to heat emitted.

Do not connect many electrical cords to a single socket or connect an AC

adapter to an outlet that is not rated for the specified voltage.Failing to do so may cause the equipment to malfunction or fail, or lead

to accidents involving electrical shock or fire due to heat emitted.

Periodically remove any dust accumulated on the power plug and

around the outlet (socket).

Do not use a power plug with dust accumulated on it because doing so

will lead to insulation failure due to moisture which may lead to fire.

Remove any dust on the power plug and around the outlet with dried

cloth.

Do not place any containers such as cups or vases filled with water or

other liquid on this Board.

If this Board is exposed to water or other liquids it may cause the Board

to malfunction or lead to accidents involving electrical shock. If you

spilled water or other liquid on this Board, immediately stop using the

Board, turn off the power, and unplug the power plug. If you have any

requests for repairs or technical consultation, please contact the

Manufacturer.

Do not place the kit on unstable places such as shaky stands or tilted

locations.

Doing so may cause injuries or cause this Board to malfunction if the

Board should fall.

Do not attempt to use or leave the kit in places subject to strong directsunlight or other places subject to high temperatures such as in cars in

hot weather.

Doing so might cause the kit to emit heat, break, ignite, run out of

control, warp, or malfunction.

Also, some parts of the equipment might emit heat causing burn

injuries.

Unplug the power supply cable when carrying out maintenance of

devices in which the main unit is embedded.

Failure to do so may lead to accidents involving electrical shock.

Do not place this Board in locations where excessive force is applied to

the Board.

Failure to do so may cause the PC board to warp, leading to breakage of

the PC board, missing parts or malfunctioning parts.

When using the kit together with expansion boards or other peripheral

devices, be sure to carefully read each of their manuals and to use them

correctly.

Manufacturer does not guarantee the operation of specific expansion

boards or peripheral devices when used in conjunction with this Board

unless they are specifically mentioned in this Manual or their successful

operation with this Board has been confirmed in separate documents.



Helio View


Caution(Continued from previous page)

Be sure to turn off the power switch when moving this Board to connect

to other devices.

Failure to do so may cause this Board to fail or lead to accidents

involving electrical shock.

Do not clean this Board by using a rag containing chemicals such asbenzine or thinner.

Failure to do so will likely to cause this Board to deteriorate. When

using a chemical cloth be sure to comply with any directions or

warnings.

Do not immediately turn on the power if you find that water or moisture

had condensed onto the main unit after removing the board from the

package.

Condensation might occur on this Board when taking it out of the box, if

the board is cool yet the room temperature is warm.

Do not apply power to the Board while water or moisture has condensed

on it because the moisture may cause the Board to break or may shorten

the service life of the parts.

When you first take this Board out of the box be sure to leave it at room

temperature for a while before using it. If condensation or moisture has

occurred on this Board, first wait for the moisture to fully evaporate

before installing or connecting the Board to other devices.

Do not disassemble, dismantle, modify, alter, or recycle parts unless they

are clearly described as customizable in this Manual.

Although this kit is customizable, if parts not specified in this Manual as

customizable are modified in any way, then the overall product

operation cannot be guaranteed.Please consult with Manufacturer beforehand if you wish to customize

or modify any parts that are not described in this Manual as

customizable.

1.3 Manufacturer InformationThe Manufacturer of this product is:

Macnica America380 Stevens Ave. Suite 206Solana Beach, CA 92075

http://www.macnica-na.com



Helio View


2. IMPORTANT INFORMATION

READ FIRST: READ this Reference Manual before using this product.

KEEP the Reference Manual handy for future reference.

Purpose of the product: The Helio View is designed as a display expansion to the Helio SoC Evaluation Kit. The

primary expansion features of the Helio View are:

WVGA (800x480) TFT LCD with capacitive, multi-touch

HDMI input

HDMI output Two PicoModule expansion sites

Precautions to be taken when using this product: In no event shall Macnica Americas be liable for any consequence arising from the use of

this product.

This product is to be used for development and evaluation only. It cannot be included in a

user's end product or mass produced.

In general, each brand name carried in this reference manual is each maker's trademark or

registered trademark.

Improvement Policy: Macncia Americas pursues a policy of continuing improvement in design, performance, and

safety of the product. Macnica Americas reserves the right to change, wholly or partially,

the specifications, design, reference manual, and other documentation at any time without

notice.

Warranty: Macnica Americas will replace units determined as defective for a period of 12 months from

original purchase. If you are considering a warranty claim, please contact Macnica

Americas for technical support before physically returning a unit.

Macnica Americas reserves the right to deny warranty under the following conditions:

(1) Misuse, abuse of product or use under additionally abnormal condition

(2) Remodeling and repair

(3) Fire, earthquake, fall, or other accident

Figures: Some figures in this reference manual may show items different from your actual system.



Helio View


3. Unboxing

Package ComponentsTable 3-1-1 lists the packaging contents of the Helio View. Confirm all physical components

listed are included. Note that many design elements are supplied via Altera’s SoC Open

Source Portal: www.RocketBoards.org

Table 3-1-1: Packing list

Getting Started document

The Helio View unit

Micro SD card

Reference Manual (this document)Download these files from the Helio

section of Altera’s SoC Open Source

Portal:

www.RocketBoards.org

Helio View schematics

Helio View bill-of-materials

Helio View layout and PCB data

Reference Designs

If there is any question or doubt about the packaged product, contact your local distributor.

http://www.rocketboards.org/









Helio View


4. Introduction

This document describes the hardware features of the Helio View expansion board including most

component reference information required to create custom FPGA designs leveraging the expanded

hardware platform. When appropriate, users are referred to component datasheets and/or

reference designs for information beyond the scope of this document.

The primary interface of the Helio View is the HSMC flex cable assembly. The HSMC interface is a

specification created by Altera to promote compatibility between base (aka host) and expansion (aka

mezzanine) cards within their development kit ecosystem. For information on the HSMC interface

beyond that provided in this document, refer the Altera’s own documentation here:

High Speed Mezzanine Card (HSMC) Specification.

The Helio View was designed specifically as an expansion to the Helio SoC Evaluation Kit and has a

form-factor enabling assembly of both into a single unit. Connectivity of the Helio View with a

different hardware platform offering HSMC connectivity is possible, but design examples targeting

the Helio platform specifically should not be expected to operate without modification.

4.1 Key Specifications

Altera HSMC Interface

WVGA (800x480) TFT LCD with Capacitive Multi-Touch

HDMI Input

HDMI Output

PicoModule Expansion (x2)

4.2 Helio View Sub-Units

The Helio View is comprised of three sub-units:

1. The LCD Assembly

2. The PCB (the primary focus of this document)

3. The HSMC Flex Assembly

These three sub-units are always shipped pre-mated into a single entity. Most users will never

need to physically separate the three sub-units of the Helio View.

Figure 4-2-1 illustrates the three sub-units of the Helio View and it is the form in which it is received

to most end users. Refer to the Helio View Getting Started document for instructions on assembly

of a Helio View and Helio SoC Evaluation Kit into a single unit. Figure 4-2-2 illustrates a

completed assembly.

http://www.altera.com/literature/ds/hsmc_spec.pdf




Helio View


Figure 4-2-1: Sub-assemblies of the Helio View

Figure 4-2-2: Helio View + Helio SoC Evaluation Kit combined into a single unit



Helio View


4.3 Primary Component Quick-ReferenceThe primary hardware components of the Helio View are listed in Table 4-3-1.

Table 4-3-1: Key components

Component Supplier Function Part number

Display Assembly GoldenVision 800x480 5" LCD with cap touch GVT800480-500CDT11CT

HSMC Flex Assembly Terasic Extend HSMC connectivity S0005

CPLD Altera Multiplex HSMC signaling 5M1270ZF256C5N

HDMI TX NXP Transmit HDMI signaling TDA19971BHN/C1

HDMI RX NXP Receive HDMI signaling TDA19988BHNC1

MEMS 50MHz 2.5V) SiLabs 50MHz clock source SI510GBB50M0000BAGR

MEMS 27MHz 2.5V) SiLabs 27MHz clock source SI510KBB27M0000BAGR

IC Volt Supervisor Linear Technology Power supervisor LTC2915CTS8-1

Synchronous Buck Linear Technology Lower power regulation LTC3621IMS8E-2

Charge Pump Linear Technology Remote power regulation LTC3200ES6-5

White LED Driver Linear Technology Backlight Current Source LT3591EDDB

2-Wire Bus Buffer Linear Technology I2C buffering LTC4315CMS

HMSC Connector Samtech Primary expansion interface ASP-122952-01-MKT

JTAG Connector Molex JTAG cable access WM4634-ND

PicoModule Connectors Samtech Future use MEC1-120-02-L-D-RA1-SL

4.4 Reference DesignsThe purpose of this reference manual is limited to description of the Helio View hardware platform

and not necessarily all aspects of design targeting this platform. Detail beyond the scope of this

reference manual can be found in separate documentation for reference designs targeting the Helio

platform.

At initial launch, reference designs are provided demonstrating:

Software rendering using DirectFB:

This design uses a simple LCD controller by Macnica to continuously output the contents of a

video buffer in memory to the Helio View display. The popular Linux software library

DirectFB is used in the ARM A9 cores of the HPS to perform software rendering on the videobuffer in memory. The HDMI interfacing is unused.

Hardware rendering using Altera VIP Suite:

This design uses the Altera Video and Image Processing Suite (VIP) to create a multi-path

video processing chain in hardware. Two sources (video buffer in memory and the

HDMI-RX) are mixed into a picture-in-picture output to the Helio View display. Hardware

functions demonstrated include Chroma Resampling, Color Space Conversion, Alpha

Blending, Scaling, and TestPatterns.



Helio View


Complete reference design source code and documentation can be retrieved from the Macnica Helio

SoC Evaluation Kit product portal at the Altera SoC Open Source Community Site

RocketBoards.org.

www.RocketBoards.org






Helio View


5. Helio View PCB

This section provides detail on the Helio View PCB itself with conceptual block diagrams and

illustrations of the physical layout.

5.1 Block DiagramFigure 5-1-1 shows a block diagram Helio View PCB. All primary components and their

connectivities are depicted. Chapter 6 provides detailed functional reference for each block shown.

Figure 5-1-1: Helio View PCB Block Diagram



Helio View


5.2 Physical ViewsFigure 5-2-1: PCB Top

The bottom of the PCB is typically not visible due to mating with the LCD sub-unit. Figure 5-2-2

depicts the bottom of the PCB with LCD removed.

Figure 5-2-2: PCB Bottom (typically hidden)

.



Helio View


6. Functional Reference

In this chapter, every major design component is identified by reference designator with its

functionality in the Helio View described. Emphasis is not on reproducing the datasheet for any

particular component, but providing information on how that component is operating within the

Helio View design.

6.1 Altera MaxV CPLD (U10)

An Altera MaxV CPLD (5M1270ZF256C5N) is the connectivity center of the Helio View design.

Figure 6-1-1 illustrates a high-level view of the CPLD design. Table 6-1-1 is a summary of the portsand functions in the CPLD design

Figure 6-1-1: CPLD Block Diagram

.



Helio View


Table 6-1-1: CPLD Signaling

Group Description: Count I/O

Standard

TransmitMultiplex

HSMC-TX pins being multiplexed 28 2.5VLCD-TX signals being multiplexed 28 3.3V

HDMI-TX signals being multiplexed 28 2.5V

Transmit Mux Control Signal 1 2.5V

Receive

Multiplex

HSMC-RX pins being multiplexed 25 2.5V

HDMI-RX signals being multiplexed 25 2.5V

PicoModule signals being multiplexed 25 2.5V

Transmit Mux Control Signal 1 2.5V

Non-Multiplexd

LCD

LCD Standby Control

LCD Reset

2 3.3V

Non-MultiplexdHDMI-TX

HDMI-TX Interrupt 1 2.5V

Non-Multiplexd

HDMI-RX

HDMI-RX Interrupt

HDMI-RX Reset

2 2.5V

Non-Multiplexed

Expansion

PicoModule1 Clock (1) 1 2.5V

GPIO User Pushbuttons 2 2.5V

Status LEDs 5 3.3V

Global

Signaling

Clock 1 2.5V

Reset 1 2.5V

Total 178Note 1: PicoModule2 Clock is in the Receive Multiplex

A primary function of the CPLD is to multiplex two large groups of HSMC pins between two

functions. Multiplexing is required because there is not enough pin capacity in the HSMC interface

to simultaneously connect all components of the Helio View to the host module.

Each multiplex function has an independent control signal which is asserted by the host module via

the HSMC interface. The following sections define each multiplex function in depth including

signaling and pinout.

6.1.1 Transmit Multiplex

The Transmit Multiplex function is so named because its function is to multiplex a single set of

HSMC pins transmitting data from the host module to either the HDMI-TX or LCD Display.

Note that the CPLD does not actually perform any colorspace conversion and is just

multiplexing the HSMC connections to one of two destinations. It is the responsibility of the

host board to which the Helio View is connected to both present the proper video data format

and properly assert the control signal controlling the transmit multiplex function.



Helio View


As a convenience, the HSMC connector is defined as “LEFT” and the HDMI-TX and LCD

Display are defined as “RIGHT” in the Transmit Multiplex function. Figure 6-1-2 illustrates the

Transmit Multiplex function and the directional conventions.

Figure 6-1-2: The Transmit Multiplex Function

Table 6-1-2 defines the signal controlling the Transmit Multiplex function of the CPLD. When

the control signal is asserted (logic 1), connection is between the HSMC and LCD Display.

When the control signal is de-asserted (logic 0), connection is between HSMC connector and

HDMI-TX.

Table 6-1-2: Transmit Multiplex Control

Description: Schematic Name

(HSMC PIN)

CPLD Port

(CPLD PIN)

Transmit Multiplex

Control

HSMA_D2_4A (43) HSMA_D2_4A (L1)

Table 6-1-3 provides a mapping between function, schematic signal name, HSMC pin number,

CPLD ports, and CPLD pin numbers when the Transmit Mux Control is asserted (logic 1).

This can also be thought of as TX-LCD Mode, as the HSMC parallel data is connected to the

LCD Display. When the Transmit Multiplex control is asserted (logic 1) all CPLD Port Right

outputs for the HDMI-TX are driven to logic 0.



Helio View


Table 6-1-3: TX-LCD Mode (Transmit Mux Control Asserted)


(HSMC Pin)

CPLD Port Left

(CPLD Pin)

CPLD Port Right

(CPLD Pin)

Display Clock HSMA_CLK_OUT0_5B (39) HSMA_CLK_OUT_5B (J5) VID_DISP_PCLK (R11)Green Color

Data[7:0]

HSMA_RX_D_P4_4A (72)

HSMA_RX_D_M4_4A (74)







HSMA_RX_D_P4_4A (K3)

HSMA_RX_D_M4_4A (K6)



HSMA_RX_D_P6_4A (J4)

HSMA_RX_D_M6_4A (J3)

HSMA_RX_D_P7_4A (H2)

HSMA_RX_D_M7_4A (H4)

VID_DISP_G[7] (T13)

VID_DISP_G[6] (P6)

VID_DISP_G[5] (R13)

VID_DISP_G[4] (T5)

VID_DISP_G[3] (R14)

VID_DISP_G[2] (R5)

VID_DISP_G[1] (T15)

VID_DISP_G[0] (T4)

Blue Color

Data[7:0]

HSMA_TX_D_P0_4A (47)

HSMA_TX_D_M0_4A (49)







HSMA_TX_D_P0_4A (K2)

HSMA_TX_D_M0_4A (K1)

HSMA_TX_D_P1_4A (J2)

HSMA_TX_D_M1_4A (J1)

HSMA_TX_D_P2_4A (F6)

HSMA_TX_D_P2_4A (G6)


HSMA_TX_D_M3_4A (H1)

VID_DISP_B[7] (P11)

VID_DISP_B[6] (T7)

VID_DISP_B[5] (T12)

VID_DISP_B[4] (R7)

VID_DISP_B[3] (R12)

VID_DISP_B[2] (T6)

VID_DISP_B[1] (P12)

VID_DISP_B[0] (R6)

Horizontal Sync HSMA_TX_D_P4_4A (71) HSMA_TX_D_P4_4A (G1) VID_DISP_HS (T11)

Vertical Sync HSMA_TX_D_M4_4A (73) HSMA_TX_D_M4_4A (G4) VID_DISP_VS (T8)

Data Enable HSMA_TX_D_P5_4A (77) HSMA_TX_D_P5_4A (F4) VID_DISP_DE (P10)

Table 6-1-4 provides a mapping between function, schematic signal name, HSMC pin number, CPLD

ports, and CPLD pin numbers when the Transmit Mux Control is de-asserted (logic 0). This can

also be thought of as TX-HDMI Mode, as the HSMC parallel data is connected to the HDMI

transmitter. When the Transmit Multiplex control is de-asserted (logic 0) all CPLD Port Right

outputs for the LCD-TX are driven to logic 0.

Table 6-1-4: TX-HDMI Mode (Transmit Mux Control De-Asserted)

Description: Schematic Name(HSMC Pin)

CPLD Port Left(CPLD Pin)

CPLD Port Right(CPLD Pin)

Pixel Clock HSMA_CLK_OUT0_5B (39) HSMA_CLK_OUT_5B (J5) nVID_TX_PCLK (B11)

Luminosity

Data[7:0]













HSMA_RX_D_P6_4A (J4)

HSMA_RX_D_M6_4A (J3)

HSMA_RX_D_P7_4A (H2)

HSMA_RX_D_M7_4A (H4)

nVID_TX_Y[7] (B9)

nVID_TX_Y[6] (C9)

nVID_TX_Y[5] (A8)

nVID_TX_Y[4] (B8)

nVID_TX_Y[3] (C8)

nVID_TX_Y[2] (A7)

nVID_TX_Y[1] (B7)

nVID_TX_Y[0] (A6)



Helio View


Unused HSMA_TX_D_P0_4A (47)


HSMA_TX_D_P0_4A (K2)

HSMA_TX_D_M0_4A (K1)

Audio Channel Data HSMA_TX_D_P1_4A (53)




HSMA_TX_D_P1_4A (J2)

HSMA_TX_D_M1_4A (J1)


HSMA_TX_D_P2_4A (G6)

nAUD_TX_SD[3] (E11)

nAUD_TX_SD[2] (E12)

nAUD_TX_SD[1] (D12)

nAUD_TX_SD[0] (E13)

Audio Word Select HSMA_TX_D_P3_4A (65) HSMA_TX_D_P3_4A (F5) nAUD_TX_WS (D13)

Audio Clock HSMA_TX_D_M3_4A (67) HSMA_TX_D_M3_4A (H1) nAUD_TX_ACLK (E14)

Horizontal Sync HSMA_TX_D_P4_4A (71) HSMA_TX_D_P4_4A (G1) nVID_TX_HS (D15)

Vertical Sync HSMA_TX_D_M4_4A (73) HSMA_TX_D_M4_4A (G4) nVID_TX_VS (E16)

Data Enable HSMA_TX_D_P5_4A (77) HSMA_TX_D_P5_4A (F4) nVID_TX_DE (E15)

6.1.2 Receive Multiplex

The Receive Multiplex function is so named because its function is to multiplex a single set of

HSMC pins to either the HDMI-RX or the PicoModule Expansion header for purposes of

receiving dagtg. It is the responsibility of the host board to which the Helio View is connected

to properly assert the control signal of the receive multiplex function.

As a convenience, the HSMC connector is defined as “LEFT” and the HDMI-RX and PicoModule

Expansion Headers are defined as “RIGHT” in the Receive Multiplex function. Figure 6-1-3

illustrates the Receive Multiplex function and the directional conventions.

Figure 6-1-3: The Transmit Multiplex Function



Helio View


Table 6-1-5 defines the signal controlling the Receive Multiplex function of the CPLD. When

the control signal is asserted (logic 1), connection is between the HDMI-RX and the HSMC

connector. When the control signal is de-asserted (logic 0), connection is between thePicoModule Expansion Headers and the HSMC connector.

Table 6-1-5: Receive Multiplex Control


(HSMC PIN)

CPLD Port

(CPLD PIN)

Receive Multiplex

Control

HSMA_TX_D_M5_4A (79) HSMA_TX_D_M5_4A (E6)


CPLD port, and CPLD pin number when the Receive Multiplex Control is asserted (logic 1).

This can also be thought of as RX-HDMI Mode, as the HSMC interface is connected to the

HDMI receiver.

Table 6-1-6: RX-HDMI Mode (Receive Mux Control Asserted)


(HSMC Pin)

CPLD Left-Port

(CPLD Pin)

CPLD Right-Port

(CPLD Pin)Pixel Clock HSMA_CLK_IN0_3B (40) HSMA_CLK_IN0_3B (L5) nVID_RX_PCLK (H5)

Chroma-Blue

Chroma-Red

Color Data

(8 bits)

HSMA_RX_D_P8_3B (102)

HSMA_RX_D_M8_3B (104)







HSMA_RX_D_P8_3B (G2)

HSMA_RX_D_M8_3B (H3)

HSMA_RX_D_P9_3B (F2)

HSMA_RX_D_M9_3B (G3)

HSMA_RX_D_P11_3B (E2)

HSMA_RX_D_M11_3B (F3)

HSMA_RX_D_P12_3B (D2)

HSMA_RX_D_M12_3B (E3)

nVID_RX_CBCR[7] (D7)

nVID_RX_CBCR[6] (C7)

nVID_RX_CBCR[5] (E7)

nVID_RX_CBCR[4] (F7)

nVID_RX_CBCR[3] (A10)

nVID_RX_CBCR[2] (C10)

nVID_RX_CBCR[1] (D10)

nVID_RX_CBCR[0] (A9)

Green

Color Data

(8 bits)





HSMA_TX_D_P10_3B (113)

HSMA_TX_D_M10_3B (115)



HSMA_RX_D_P13_3B (C2)

HSMA_RX_D_M13_3B (D3)


HSMA_RX_D_M16_3B (B3)

HSMA_TX_D_P10_3B (D6)

HSMA_TX_D_M10_3B (D1)

HSMA_TX_D_P11_3B (C4)

HSMA_TX_D_M11_3B (C5)

nVID_RX_Y[7] (B9)

nVID_RX_Y[6] (C9)

nVID_RX_Y[5] (A8)

nVID_RX_Y[4] (B8)

nVID_RX_Y[3] (C8)

nVID_RX_Y[2] (A7)

nVID_RX_Y[1] (B7)

nVID_RX_Y[0] (A6)

Horizontal Sync HSMA_TX_D_P12_3B (125) HSMA_TX_D_P12_3B (B1) nVID_RX_HS (A4)

Vertical Sync HSMA_TX_D_M12_3B (127) HSMA_TX_D_M12_3B (B4) nVID_RX_VS (A5)

Data Enable HSMA_TX_D_P13_3B (131) HSMA_TX_D_P13_3B (A2) nVID_RX_DE (B5)

Unused HSMA_TX_D_M13_3B (133) HSMA_TX_D_M13_3B (C6) Logic 0



Helio View


Audio Data Channels HSMA_TX_D_P8_4A (101)


HSMA_TX_D_P8_4A (E1)

HSMA_TX_D_M8_4A (E4)

nAUD_RX_SD[1] (F10)

nAUD_RX_SD[0] (E9)

Audio Word Select HSMA_TX_D_P9_4A (107) HSMA_TX_D_P9_4A (D4) nAUD_RX_WS (D8)

Audio Clock HSMA_TX_D_M9_4A (109) HSMA_TX_D_M9_4A (D5) nAUD_RX_ACLK (E8)


CPLD ports, and CPLD pin numbers when the Receive Multiplex Control is de-asserted (logic

0). This can also be thought of as RX-EXP Mode, as the HSMC interface is connected to the

PicoModule Expansion headers.

Table 6-1-7: RX-EXP Mode (Receive Mux Control De-Asserted)

Description: Schematic Name(HSMC Pin)

CPLD Left-Port(CPLD Pin)

CPLD Right-Port(CPLD Pin)

Expansion 2

Clock

HSMA_CLK_IN0_3B (40) HSMA_CLK_IN0_3B (L5) EX2_CLK (H5)

Expansion 2

GPIO[12:1]













HSMA_RX_D_P8_3B (G2)

HSMA_RX_D_M8_3B (H3)

HSMA_RX_D_P9_3B (F2)

HSMA_RX_D_M9_3B (G3)

HSMA_RX_D_P11_3B (E2)

HSMA_RX_D_M11_3B (F3)

HSMA_RX_D_P12_3B (D2)

HSMA_RX_D_M12_3B (E3)


HSMA_RX_D_M13_3B (D3)


HSMA_RX_D_M16_3B (B3)

EX2_GPIO[12] (J16)

EX2_GPIO[11] (K12)

EX2_GPIO[10] (K14)

EX2_GPIO[9] (K11)

EX2_GPIO[8] (G11)

EX2_GPIO[7] (H16)

EX2_GPIO[6] (H15)

EX2_GPIO[5] (G13)

EX2_GPIO[4] (G14)

EX2_GPIO[3] (F14)

EX2_GPIO[2] (G12)

EX2_GPIO[1] (F13)

Expansion 1

GPIO[7:0]






HSMA_TX_D_M12_3B (127)HSMA_TX_D_P13_3B (131)


HSMA_TX_D_P10_3B (D6)

HSMA_TX_D_M10_3B (D1)

HSMA_TX_D_P11_3B (C4)


HSMA_TX_D_P12_3B (B1)

HSMA_TX_D_M12_3B (B4)HSMA_TX_D_P13_3B (A2)


EX1_GPIO[7] (H14)

EX1_GPIO[6] (K15)

EX1_GPIO[5] (H13)

EX1_GPIO[4] (L14)

EX1_GPIO[3] (G15)

EX1_GPIO[2] (J15)EX1_GPIO[1] (F15)

EX1_GPIO[0] (J14)

Expansion 2

GPIO[0]

HSMA_TX_D_P8_4A (101) HSMA_TX_D_P8_4A (E1) EX2_GPIO[0] (F12)

Expansion 1

GPIO[10:9]




HSMA_TX_D_M8_4A (E4)

HSMA_TX_D_P9_4A (D4)

HSMA_TX_D_M9_4A (D5)

EX1_GPIO[10] (K13)

EX1_GPIO[9] (J13)

EX1_GPIO[8] (K16)



Helio View


6.1.3 Non-Multiplexed I/O

Table 6-1-8 provides a mapping between function, schematic signal name, CPLD port, and

CPLD pin number for non-multiplexed I/O.

Table 6-1-8: Non-Multiplexed I/O

Description: Schematic Name CPLD Port

(CPLD Pin)

Direction

LCD Standyby STBYn_DISP STBYn_DISP (P7) Output

LCD Reset RSTn_SOC_TP RSTn_SOC_TP (N9) Output

HDMI-TX Interrupt INTn_TX INTn_TX (B10) Input

HDMI-RX Interrupt INTn_RX INTn_RX (B6) Input

HDMI-RX Reset RSTn_SOC_RX RSTn_SOC_RX (F11) Output

PicoModule Clock1 EX1_CLK EX1_CLK (L15) Output

PushButton 1 CPLD_SW1 CPLD_SW1 (L12) Input

PushButton 2 CPLD_SW2 CPLD_SW2 (L13) Input

Status LED 3 CPLD_LED3 CPLD_LED3 (L7) Output

Status LED 3 CPLD_LED2 CPLD_LED2 (M7) Output

Status LED 3 CPLD_LED1 CPLD_LED1 (M6) Output

Status LED 3 CPLD_LED0 CPLD_LED0 (R1) Output

Clock PLD_50MHZ clk (H12) Input

Reset RESETn rst (L11) Input

6.2 HDMI Transmitter (U5) The Helio View implements HDMI transmission with the NXP TDA19988. The audio and video

signaling of HDMI transmission is multiplexed with signaling of the LCD Display by the MaxV

CPLD. The host module supporting the HSMC interface can only provide video signaling to either

the HDMI Transmitter or the LCD Display at any given time.

6.2.1 Video Data Format (4:2:2 YCrCb)

The NXP TDA19988 supports a variety of video data formats, but the Helio View is routed in

support of 4:2:2 YCrCb only. This data format was selected because it requires less signalingthan other modes of operation and signaling capacity in the HSMC connector was a primary,

design factor of limitation (refer to the HSMC mux functionality of the CPLD which is also a

result of signaling capacity).

More exactly, the NXP TDA19988 input ports VP[7:0] are not used in 4:2:2 YCrCb, grounded in

schematics, and therefore video data formats that require these ports are not supported by the

Helio View.



Helio View


6.2.2 Low Power Mode

The NXP TDA19988 supports a lower power mode where its core rail termed VDD(IO)(3V3) is

optionally connected to 2.5V. The Helio View implements this lower power option, so schematic

connections of TDA1997 ports labeled VDD(IO)(3V3) to 2.5VDC is not in error and correct bydesign.

6.2.3 I2C Configuration / Drivers

The NXP TDA19988 has an I2C interface to configure operation. This document defines the

base-address for I2C accesses, but information on a sub-addressing scheme and functional

definition are not publically available (refer to section 6.7).

Macnica does provide a pre-canned driver in reference designs targeting the Helio platform that

can be used without requiring full understanding of the NXP TDA19988 addressable I2C space.

Contact NXP directly for definition of the I2C address space beyond that shown in thisdocument or reference designs.

6.2.4 Pinout and Connectivity

Table 6-1-9 defines the pinout and connectivity of the NXP TDA19988 in the Helio View design.

Table 6-1-9: HDMI Transmit Pin assignments, Signal Names and Functions

Pin

Number

U13)

Description Schematic

Signal Name

Connected To

1 Transmit Video: Y[6] VID_TX_Y[6] CPLD (mux to HMSC)

2 Transmit Video: Y[5] VID_TX_Y5 CPLD (mux to HMSC)


4 Pixel Clock VID_TX_PCLK CPLD (mux to HMSC)

5 Core Supply (1.8V) 1.8VDC 1.8V Power Plane




9 Transmit Video: Y[0] VID_TX_Y0 CPLD (mux to HMSC)10 Transmit Video: CBCR[7] VID_TX_CBCR7 CPLD (mux to HMSC)

11 Transmit Video: CBCR[6] VID_TX_CBCR6 CPLD (mux to HMSC)








19 -- -- Ground



Helio View


20 Transmit Video: Data Enable VID_TX_DE CPLD (mux to HMSC)

21 Transmit Video: Vertical Sync VID_TX_VS CPLD (mux to HMSC)

22 Transmit Video: Horizontal Sync VID_TX_HS CPLD (mux to HMSC)

23 Transmit Audio: Clock AUD_TX_ACLK CPLD (mux to HMSC)

24 Transit Audio: Word Select AUD_TX_WS CPLD (mux to HMSC)

25 Transmit Audio: Serial Data Ch0 AUD_TX_SD0 CPLD (mux to HMSC)





30 HDMI consumer elec. control HDMI_TX_CEC HDMI-TX Connector

31 HDMI Hot plug detect HDMI_TX_HPD HDMI-TX Connector

32 HDMI DDC-bus serial data HDMI_TX_DDC_SDA HDMI-TX Connector

33 HDMI DDC-bus serial clock HDMI_TX_DDC_SCL HDMI-TX Connector

34 HDMI TMDS output swing adjustment -- 10k pull to Ground

35 Analog supply (1.8V) HDMI_TX(A)_1.8VDC Filtered 1.8V


37 HDMI clock channel (minus) HDMI_TX_Cm HDMI-TX Connector

38 HDMI clock channel (plus) HDMI_TX_Cp HDMI-TX Connector

39 HDMI data channel 0 (minus) HDMI_TX_D0m HDMI-TX Connector

40 HDMI data channel 0 (plus) HDMI_TX_D0P HDMI-TX Connector



43 HDMI data channel 1 (plus) HDMI_TX_D1p HDMI-TX Connector


45 HDMI data channel 2 (plus) HDMI_TX_D2p HDMI-TX Connector


47 PLL supply (1.8V) HDMI_TX(PLL)_1.8VDC Filtered 1.8V

48 PLL supply (1.8V) HDMI_TX(PLL)_1.8VDC Filtered 1.8V

49 Test Pin -- Ground

50 Interrupt (active low) INTn_TX CPLD (mux to HMSC)

51 I2C-bus serial clock HSMA_SDA_3A Multiple

52 I2C-bus serial data HSMA_SCL_3A Multiple

53 I2C-bus address LSB bit 0 -- Pullup via pop- option

54 I2C-bus address LSB bit 1 -- Pulldown via pop-option


56 Transmit Video: Unused in 4:2:2 YCrCb -- Ground










Helio View



6.3

HDMI Receiver (U13) The Helio View implements a HDMI Receive with the NXP TDA19971. The audio and video

signaling of the HDMI receiver is multiplexed with signaling of the PicoModule expansion sites by

the MaxV CPLD. The host module supporting the HSMC interface will only be presented with

HDMI receiver signaling or PicoModule expansion signaling at any given time.

6.3.1 Video Data Format (4:2:2 YCrCb)

The NXP TDA19971 supports a variety of video data formats, but the Helio View is routed in

support of 4:2:2 YCrCb only. This data format was selected because it requires less signaling

than other modes of operation and signaling capacity in the HSMC connector was a primary,

design factor of limitation (refer to the HSMC mux functionality of the CPLD which is also aresult of signaling capacity).

More exactly, the NXP TDA19971 output ports VP[7:0] are not used in 4:2:2 YCrCb,

unconnected in schematics, and therefore video data formats that require these ports are not

supported by the Helio View.

6.3.2 Low Power Mode

The NXP TDA1997 supports a lower power mode where its core rail termed VDD(IO)(3V3) is

optionally connected to 2.5V. The Helio View implements this lower power option, so schematic

connections of TDA1997 ports labeled VDD(IO)(3V3) to 2.5VDC is not in error and correct bydesign.

6.3.3 I2C Configuration / Drivers

The NXP TDA19971 has an I2C interface to configure operation. This document defines the

base-address for I2C accesses, but information on a sub-addressing scheme and functional

definition not publically available (refer to section 6.7)

Macnica does provide a pre-canned driver in reference designs targeting the Helio platform that

can be used without requiring full understanding of the NXP TDA19971 addressable I2C space.

Contact NXP directly for definition of the I2C address space beyond that shown in thisdocument or reference designs.

6.3.4 Pinout and Connectivity

Table 6-1-10 defines the pinout and connectivity of the NXP TDA19971 in the Helio View

design.



Helio View


Table 6-1-10: HDMI Receive Pin assignments, Signal Names and Functions

Pin

Number

U13)


Signal Name

Connected To

1 Reset (active low) RSTn_RX Reset Generation

2 Test Port (unused) GND Ground

3 Deep Color PLL supply (1.8V) HDMI_RX(A)_1.8VDC Filtered 1.8V

4 Hot plug detect HDMI_RX_HPD HDMI-RX Connector

5 HDMI-RX supply (5.0V) HDMI_RX_5.0VDC HDMI-RX Connector

6 HDMI DDC-bus serial data HDMI_RX_DDC_SDA HDMI-RX Connector

7 HDMI DDC-bus serial clock HDMI_RX_DDC_SCL HDMI-RX Connector

8 PLL supply (3.3V) HDMI_RX(A)_3.3VDC Filtered 3.3V

9 HDMI clock channel (minus) HDMI_RX_Cm HDMI-RX Connector

10 HDMI clock channel (plus) HDMI_RX_Cp HDMI-RX Connector11 HDMI data channel 0 (minus) HDMI_RX_D0m HDMI-RX Connector

12 HDMI data channel 0 (plus) HDMI_RX_D0p HDMI-RX Connector

13 HDMI data channel 1 (minus) HDMI_RX_D1m HDMI-RX Connector


15 HDMI data channel 2 (minus) HDMI_RX_D2m HDMI-RX Connector


17 HDMI consumer elec. control HDMI_RX_CEC HDMI-RX Connector

18 Analog supply (1.8V) HDMI_RX(A)_1.8VDC Filtered 1.8V

19 Termination resistor control -- Pullup to 3.3V

20 Debug Pin -- No Connect

21 No Connect -- No Connect

22 No Connect -- No Connect

23 HDMI analog supply voltage (3.3V) HDMI_RX(A)_3.3VDC Filtered 3.3V


25 Interrupt (active low) INTn_RX CPLD (mux to HMSC)

26 I2C-bus serial clock HSMA_SCL_3A Multiple

27 I2C-bus serial data HSMA_SDA_3A Multiple

28 Receive Video: Horizontal Sync VID_RX_HS CPLD (mux to HMSC)

29 Receive Video: Vertical Sync VID_RX_VS CPLD (mux to HMSC)

30 Receive Video: Data Enable VID_RX_DE CPLD (mux to HMSC)

31 Receive Video: Pixel Clock VID_RX_PCLK CPLD (mux to HMSC)


33 Receive Video: Unused in 4:2:2 YCrCb TP56 --









Helio View




42 Receive Video: Y[0] VID_RX_Y0 CPLD (mux to HMSC)









51 Receive Video: CBCR[0] VID_RX_CBCR0 CPLD (mux to HMSC)












63 Crystal Out (unused) -- --

64 Crystal In (27MHz) HDMI_RX_27MHZ 27MHz Source


66 Receive Audio: Clock AUD_RX_ACLK CPLD (mux to HMSC)

67 Receive Audio: Word Select AUD_RX_WS CPLD (mux to HMSC)

68 Receive Audio: Serial Data Ch0 AUD_RX_SD0 CPLD (mux to HMSC)




72 internal supply decoupling capacitor -- Ground through Cap

6.4 LCD Sub-AssemblyThe LCD Sub-Assembly is comprised of a display and a multi-touch controller. This section gives a

summary of the functionality of the display and multi-touch controller, but their respective

datasheets should be referenced for full specification.



Helio View


6.4.1 Display

The display of the LCD Sub-Assembly is model GVT800480-500CDT11 manufactured by USA

Golden Vision. Table 6-4-1 summarizes the electrical and mechanical specifications of the

Helio View display.

Table 6-4-1: LCD General Specifications

Feature Specification Unit

Electrical Size 5.0 Inchs

Resolution 800 x 400 Pixel

Interface RGB-24 Bits

Color Depth 16.7M Colors

Pixel Pitch 0.135 x 0.135 Millimeters

ViewingDirection

Six O’clock

Technology a-Si / TFT --

Pixel Config Vertical Stripe --

Display Mode Normally White --

Driver IC HX8264-D+HX8664-B --

Mechanical W x H x D 120.7 x 75.8 x 3.1 Millimeters

Active Area 108.0 x 64.8 Millimeters

Backlight 12 LEDs

Refer to the GVT800480-500CDT11 datasheet for detailed specification of the display beyondthe scope of this document. That said, reference designs targeting the Helio View platform are

provided to demonstrate operation and functionality. All reference designs are available in the

Macnica Helio Evaluation Kit area of Altera’s open-community portal for SoC devices,

www.RocketBoards.org.

6.4.2 Multi-Touch Controller

The multi-touch controller of the LCD Sub-Assembly is model FT5306DE4 manufactured by

FocalTech. The functions and data of the multi-touch controller are accessed by the board

hosting the Helio View design via an I2C serial interface. Figure 6-4-1 illustrates the generalsignaling of the multi-touch controller and Table 6-4-2 summarizes the key functions of the

multi-touch controller.






Helio View


Figure 6-4-1: Multi-Touch Controller Interfacing Diagram

Figure 6-4-2: Multi-Touch Controller Functional Summary

Function Description

Touch Circuits Transmit and receive AC signaling from

the touch panel

Microcontroller 8051 with some enhacements

External

Interface

I2C/SPI: interface for data exchange

INT: interrupt indicating touch data

available

WAKE: interrupt indicating request for

active mode from hibernate mode

RSTn: active low reset

WatchDog Timer Fault recovery timeout

Regulator Generate 1.8V from 3.3V supply

Refer to the FT5x06 datasheet for detailed specification of the Multi-Touch controller beyond

the scope of this document. That said, reference designs targeting the Helio View platform are

provided to demonstrate operation and functionality. All reference designs are available in theMacnica Helio Evalulation Kit area of Altera’s open-community portal for SoC devices,

www.RocketBoards.org.

6.5 ConnectorsThis section defines the connectors of the Helio View design.






Helio View


6.5.1 HSMC Connector (J7)

The HSMC interface is a specification created by Altera to promote compatibility between host

platforms and expansion cards within their development kit ecosystem. For complete information

on the HSMC interface beyond that provided in this document, refer the Altera’s own documentationhere:

High Speed Mezzanine Card (HSMC) Specification.

Figure 6-5-1 illustrate the HSMC banks and the approximate usage in the Helio View design. The

mezzanine connector is comprised of three banks:

Bank1: supports highest datarates (typically serial/CDR-based protocols) which are notused in the Helio View design and brought out to testpoints. Bank 1 also supportsJTAG signaling,clocking, and SMBUS.

Bank2: supports bulk interface CMOS and/or LVDS signaling. It also contains 3.3V

and 12V power. Bank3: supports bulk interface CMOS and/or LVDS signaling. It also contains 3.3V

and 12V power.

Figure 6-5-1: Approximate HSMC Connectivity






Helio View


Figure 6-6-1: Helio View Power Tree

6.6.1 Local Power Generation (U1, U3, U12)

The term “local” refers to consumption of power on the Helio View itself, and not by something

connected remotely (such as via the HDMI-TX header). The local rails are: 5V (from 12V), 2.5V

(from 3.3V), and 1.8V (from 3.3V). Each rail is generated using an LTC3621. This device by

Linear Technology provides 1A, synchronous, buck regulation at 95% efficiency in a monolithicmodule. The LTC3621 supports a Vin range of from 2.2V – 7V and a few trim resistors are used

to set the appropriate Vout for each local rail.

6.6.2 Remote Power Generation (U2)

The term “remote” refers to consumption of power external to the Helio View. More

specifically, this refers to power consumed by a device attached to the HDMI-TX connector

which supplies 5.0V to anything plugged into that interface. While 5.0V is available as a local

rail already, the Helio View creates a separate, remote rail using the Linear Technology

LTC3200 charge-pump.



Helio View


The LTC3200 is configured boost a 5.0V output from a 3.3V input. More importantly, unlike

the LTC3621 creating the local 5.0V rail, the LTC3200 has indefinite short-circuit protection

making it ideal to supply power within the HDMI-TX connector which is exposed to a user.

6.6.3 Backlight Current (U9)

Backlight current is supplied to the LCD Connector using a dedicated current source. The

Linear Technology LT3591 white LED driver provides this functionality with minimal board

area due to higher switching frequencies. The CPLD controls the backlight current, and thus

backlight intensity, with a single output that is pulse-width modulated.

Table 6-3-1: Backlight Current

Pin

Number


Signal Name

Connected To

U9 8) Backlight Control (PWM) PWM_DISP_LED CPLD

6.6.4 Voltage Supervisor (U4)

The 3.3V rail is monitored to within -5% of nominal using the Linear Technology LTC2915. Note

that there is no supervision of the 12.0V rail.

An error condition of the voltage supervisor results in a reset generation identical that which

can be applied by the user via the RESET pushbutton. Refer to section XXX for details ondistribution of the voltage supervisor reset throughout the Helio View design. The error

condition signal is also fed to the downstream synchronous buck regulators dependent on the

3.3V rail being monitored.

Table 6-3-2: Voltage Supervisor

Pin

Number


Signal Name

Connected To

U4 5) Fault Condition / Reset low assertion PGOOD Reset Distribution and

Downstream Buck Regulation

U4 2) Voltage Select1: set for 3.3V supervision -- Pull Up

U4 7) Voltage Select2: set for 3.3V supervision -- Pull Down

U4 3) Tolerance Select: set for -5% -- Pull Up

6.7 Serial Management BusThe Helio View supports serial management across the HSMC interface via an I2C master on the

hosting board. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported. The

CPLD, HDMI-RX, HDMI-TX, and TouchPanel all have serial management interfacing, but

connectivity to the CPLD is for future use and currently undefined.



Helio View


All I2C signaling is 2.5V except for the TouchPanel. A 2-wire buffer from Linear Technology

translates between 2.5V and the 3.3V leveling the TouchPanel requires. Figure 6-4-1 illustrates the

serial management bus of the Helio View design.

Figure 6-4-1: Serial Management Bus

Table 6-4-1 defines the serial management address map of the Helio View design. Note that the

address map includes the lowest address bit as R/W indication.

The HDMI-TX and HDMI-RX devices of NXP have base slave addresses for read and write access to

HDMI and CEC functions. However, these devices implement a sub-addressing scheme with

functional definition not publically available. Contact NXP directly for definition of the I2C address

space beyond that shown in table 6-4-1.

Table 6-4-1: I2C Address Space

Address Device Description

00-67 Unused Unused

68 HDMI-RX CEC Write Access

69 HDMI-RX CEC Read Access

6A HDMI-TX CEC Write Access

6B HDMI-TX CEC Read Access



Helio View


6C-6F Unused Unused

70 LCD Touch LCD Touch Write access

71 LCD Touch LCD Touch Read access

72-8F Unused Unused

90 HDMI-RX HDMI Write Access

91 HDMI-RX HDMI Read Access

92-E1 Unused Unused

E2 HDMI-TX HDMI Write Access

E3 HDMI-TX HDMI Read Access (1)

E4-FF Unused Unused

6.8

Clock Generation (Y1, Y2) Table 6-5-1 summarizes clock generation within the Helio View design. The Helio View uses SiTime

SI510 series MEMs technology devices for all clock generation. These devices are lower-cost than

crystal, higher MTBF than crystal, and require only simple/plastic packaging that support reflow

during assembly. Additionally, SiTime devices support one-time programming of any frequency to 6

decimal places. Refer to the linked SiTime whitepaper for more information on SiTime’s MEMs

technology vs traditional crystal-based osciallators: SiTime: MEMs Replacing Quartus Oscillators

Table 6-5-1: Clock Generation

Pin

Number


Signal Name

Connected To

Y1 3) 50MHz CPLD clock CPLD_50MHZ CPLD

Y2 3) 27MHz HDMI-RX clock HDMI_RX_27MHZ HDMI-RX

6.9 Reset Distribution (U6, U7, U8) The Helio View reset signals are generated by either a user push-button, power supervisor chip or

CPLD output. The user-pushbutton source and power supervisor are wire-OR’d and their combined

output passes through a Schmitt-trigger buffer (U8) to sharpen transitions and remove hysteresis.This pushbutton/power reset is then applied to the CPLD.

Two AND gates (U6, U7) are then used to create a logical OR-ing of the active-low pushbutton/power

reset with active-low CPLD generated resets for final application to the LCD Touch connector and

the HDMI-RX chip. Figure 6-9-1 illustrates the reset distribution circuit.

http://www.sitime.com/support2/documents/AN10010_MEMS_Replacing_Quartz_Oscillators_2-1.pdf





Helio View


Figure 6-9-1: Reset Distribution

6.10 PushButtonsThe Helio View has three pushbuttons available for simple user input.

6.10.1 RESET (SW2)

A momentary contact switch provides physical reset assertion to a user. The RESET switch is

normally-open, push-closed. When closed, the switch makes momentary connection to ground

overriding a weak pull-up resistor and creating an active-low reset signal. Refer to section 6.9

for details on distribution of the push button reset throughout the Helio View design.

6.10.2 CPLD_SW1 / CPLD_SW2 (SW4/SW5)

CPLD_SW1 and CPLDP_SW2 are two momentary contact switches provided for user input to

the MaxV CPLD. Each switch is normally-opened, push-closed and makes momentary contact

to ground to overcome a weak pull-up resistor.

In the factory-default CPLD design, these switches are primarily for future use as they have no

function other than illuminating status LEDs when depressed.



Helio View


6.11 LEDsThe Helio View contains many LEDs for quick identification of static status. Table 6-9-1

summarizes the diagnostic LEDs and their indication when illuminated.

Table 6-8-1: LEDs

Reference

Designator

Color Description When Lighted) Schematic

Signal Name

D2 Green HDMI-TX-Connector 5V Preset CP_5.0VDC

D9 Green HDMI-RX-Connector 5V Present HDMI_RX_5.0VDC

D11 Green HDMI-RX Pending Interrupt INTn_RX

D14 Green 3.3V Power Present 3.3VDC

D15 Red HDMI-RX Reset Not Asserted RSTn_RX

D16 Red TouchPanel Reset Not Asserted RSTn_TP

D18 Green CPLD Receive Mux = HDMI CPLD_LED3D19 Green CPLD Transmit Mux = LCD CPLD_LED2

D20 Green CPLD SW_1 pressed CPLD_LED1

D21 Green CPLD SW_2 pressed CPLD_LED0

D23 Green HDMI-TX Pending Interrupt INTn_TX

D24 Green TouchPanel Interrupt Pending INTn_TP



Helio View


7. Appendix

7.1 Restoring/Updating the Factory CPLD Image

Because the Helio View is designed as an expansion to the Macnica Helio Evaluation Kit, the

instructions of this section assume these two units have been mated into a single unit and that

components like cables and power adapters included with the Helio Evaluation Kit are available.

Table 7-1-1 lists the components necessary to restore or update the CPLD image of the Helio View design. The instructions for restoring the factory CPLD image and updating the CPLD are

identical except for the image data used. CPLD images are available in the Macnica Helio

Evaluation Kit area of Altera’s open-community portal for SoC devices, www.RocketBoards.org.

Table 7-1-1: Requirements for Restoring/Updating CPLD Image

Element Description

USB Blaster II Not Supplied with kits: purchased separately

Helio View

Assembled into a single unit

Helio Evaluation Kit

Power Adapter Supplied with Helio Evaluation Kit

Quartus Software Altera software package (version 13.0sp2 or later)

Computer w/USB port Installation target for Altera Quartus Software

CPLD Image Design to be loaded

Note that power necessary for programming is supplied by the Helio Evaluation Kit via the external

power supply provided with that kit. While it is possible to program the CPLD by powering the

Helio View uncoupled from a host module via power applied to the Helio View power connector, no

such power source is provided and using one is beyond the scope of these instructions.

Note also that programming requires a user to provide an external programmer (aka USB-Blaster)

which is the bridge between Quartus software controlling programming and the JTAG connector of

the Helio View. Unlike the Helio Evaluation Kit which has USB Blaster circuitry integrated so that

only a USB Micro cable is required, the Helio View has no integrated USB-Blaster circuit and thus

an external USB programmer is required. Figure 7-1-1 illustrates a typical external USB

programmer making connection.







Helio View


Figure 7-1-1: Typical External Programmer Connection

To restore or update the CPLD design, follow these steps:

1) Remove power from the Helio Evaluation Kit hosting the Helio View2) Connect the external programmer from computer running Altera Quartus software

to the Helio View JTAG header, observing pin1 orientation3) Apply power to the Helio Evaluation Kit hosting the Helio View. The USB Blaster

should be recognized by the O/S with driver installed. If not, refer to Altera’s own

documentation on installing driver for external programmer.4) Launch the Programmer of the Altera Software. A USB connection should be

shown as available in the available programming hardware. If not, refer to Altera’s own documentation on installing driver for external programmer.

5) Confirm operation by performing an “Auto Detect”. If successful, the Quartus

Programmer utility will show a diagram of the JTAG chain with CPLD deviceidentified.

6) Identify the configuration file to program with a right-click or double-click menu onthe line labeled CFM (the UFM is for user-flash-memory and not used in thisdesign).

7) Make the box selection to “program” and then select START.

Reference Manual HelioView 1p00

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