Reconfigurable Computing: Is it Ready for Industry?

Fadi J. KurdahiEECS Dept. UC Irvine

Some History

• Reconfigurable Computing research since late eighties

• DARPA’s Adaptive Computing Systems (1996) – over 60 projects in the US alone

• Significant penetration in the research community – (e.g. whole tracks in some conferences)

• But is it ready for industry to make money out of it?

What is Reconfigurable Computing?Temporal-Spatial Processing

RC

FPGA

ParallelProcessing

DSP

ASIC

RC Status today

• Thriving research activities in universities.• Industry is interested…. But:

– Still looking for RC’s value proposition– Global economy delaying new product launches– No sufficient R&D resources for Tech. Transfer

• Wrong architectures for the right applications• Intended users• Software tools!!!

What works?• Part of a solution, or the whole solution (i.e. Core

IP or Chip?)• What is RC intended to replace? ASIC or DSP?• No single size fits all

– Different application domains require different capabilities

– I/O and memory• Flexibility costs area, performance, power

– Some functions are still more efficiently implemented in ASIC blocks

• Target a programming paradigm familiar to intended users

The Ubiquitous Mobile

Standards are Many

Which 3G do you mean?

Standards are not really fixed

Not Only standards but applications also

Source: U. Ramacher, Infineon

Source: Intel Corp.

Architecture of MS1 CoreMS1-16 Core

Designed for use in 3G Base Stations

SequenceGenerator

I/OInterface

DataMemory

ContextMemory

2 Rows8 ColumnsrDSP fabric

Controller

InterleaverIQBuffer

SpecializedBlocks

SpecializedBlock

Software Structure

GNU Linker/loader

GNU Linker/loader

GCC/G++ Compiler

Simulation/Debug/JTAG

Morpho Standard Library

DCT

FIR8T

MS1 Tools

User C/C++ Code

User Development

Applications3G Device

Implementation with MS1

RAKE RcvrSpreading

Convolution EncoderViterbi DecoderTurbo EncoderTurbo Decoder

VoiceEnc/DecMPEG-4

Multiple functions require a single MS1 Core and Multiple functions require a single MS1 Core and uControlleruControllerrDSPrDSP provides flexibility for modificationsprovides flexibility for modificationsSmaller silicon areaSmaller silicon areaShorter timeShorter time--toto--marketmarket

MS1 Core

MACuController

ApplicationsExample: Forward Link WCDMA AMR Channel

Fully Implemented for the MS1-16 Development Board

RAKE Rcvr2nd

Deinterleaver1st

DeinterleaverDTX bitsRemoval

Demux

1/3 RateViterbi Dec

1/3 RateViterbi Dec

1/3 RateViterbi Dec

CRCCheck

Block CodeRemoval

DecodedBlock

Segmentation

EnhancedFull RateDecoder

D/A

MS-16 Chip

MS-16 Development BoardVOICE

IQ Samples

RAKE Finger N

ApplicationsExample: RAKE Receiver

Fully Implemented for the MS1-16 Core

↓ 8EarlyLatePunct

Despreader

Symbol Timing EstimationSymbol/Code Tracking

×I2 + Q2

Despreader

I2 + Q2

Phase OffsetCorrection

RSSIDPCH

PhaseCorrection

DDS

PhaseEstimation

Phase OffsetEstimation

AFC

×

RAKE Finger 1

RAKE Finger 2

CPICH

DPDCH

ChannelEstimation

PathSelection

τ

8-bit IQ samples8x oversampling

+

MRC

RSSICPICH

ApplicationsWCDMA Links on the MS1

AMR 12.2 Kbits/s Voice Channel

Rake Receiver Viterbi &Deinterleaver

downlink

ConvolutionalEncoderuplink

EFRDecoder

EFREncoder

10ms radio frame

42% headroom

Spreading

Overhead

Tasks are executed in a time-multiplexed fashion

ApplicationsWCDMA Links on the MS1

2-Branch Diversity 384 Kbits/s Data Channel

Rake ReceiverTurbo Decoder

R = 1/3 K = 4

downlink

Spreadinguplink TurboEncoder

% of 10ms radio frame

35% headroom

Rake Receiver

MPEG-4Decoder

MPEG-4Encoder

% of 10ms radio frame

35% headroom

RCF = Reconfigurable Compute Fabric

Generic SystemArchitecture

SDRAM

PQ II

SDRAM

DL TX IF

DL TX IF

UL RX IF

UL RX IF

UL RX IF

Ctrl Network IF

Trsp Network IF

Trsp Network IF

SDRAM

StarCore DSP DeviceMSC8126

RCF DeviceMRC6011

SDRAM useoptional

DL TX IF needs a 60x Bus IF Master

Source: Motorola SPS

Scenario 1: 128 AMR Users UL+DL, RACH

- 128 AMR Users for UL and DL, includes 1 Sector RACH Processing.- This scenario implies Worst Case load on the devices

MRC6011, #1Traffic Processing /

Path Profiling

Load: 88%

MSC8126 #1Traffic, PathProfiling, SRProcessing

Load: 87%

SDRAM

NetworkIF

MRC6011, #2Traffic Processing /

Path Profiling,RACH Processing

Load: 88%

MSC8126 #2Traffic, SRProcessing,DL/RACH

Load: 71%

PQII / PQ IIIL2/3

Processing

UL Antenna Inputs

MRC6011, #3Traffic Processing /

Path Profiling,RACH Processing

Load: 84%

DL output

DL output

Source: Motorola SPS

Scenario 3: 89 Ch AMR, 3 Ch 384 kbit/s, HSDPA

We now calculate a Scenario, where 30% Data Traffic is assumed to be the average load of the system. This translates roughly into 89 x AMR Channels and 3 x 384 kbit/s data channel. 2 HSDPA carriers with 18 Users of H-Set1 could be processed at zero additional cost, and still with a DSP System load of only 75%!

MSC8126 #1

Load: 66%

MSC8126 #2

Load: 66%

MRC6011, #1

Load: 89%

MRC6011, #3

Load: 12%(5 Cores Idle)

MRC6011, #2

Load: 89%

SDRAM

PQII / PQ IIIL2/3

Processing

DL output

DL output

Source: Motorola SPS

Channel Capacities for Different Services

12.2 Kbit/s

534 Kbit/s

384 Kbit/s

12.2 Kbit/s

Data Rate

144

144*

28

128

Number of Users

EDGE AMR4

3G HSDPA H-Set13

3G Data 3842

3G AMR 1

ServicesScenario

Assumes maximum no of Channels processed on the flexible proposed solution.* Example, does not refer to available capacity/code space

Source: Motorola SPS

What about Others?

Source: Intel Corp.

Other RC industry adoptions

• QuickSilver Technology recently announced that it has licensed its technology to Olympus for camera apps.

• Sony announced the latest Clie TG50 PDA incorporating a reconfigurable processor.

• Phillips acquired Systemonics for their Wi-Fi solution on RC

• Infineon acquired MorphICs

What was the press saying in 1998

And five years later…..

Source: Intel Corp.

Conclusion

• Reconfigurable Computing provides viable solutions to real problems

• Industry adoption of RC in some segments• Tools, tools, tools!