Real-Time Digital Systems for Control on Small Tokamaks

17th TM on Research Using Small Fusion Devices

Real-Time Digital Systems for Control on Small Tokamaks

Presented by: Bernardo B. Carvalho

Association Euratom/IST on behalf of the CFN Data Acquisition Group and ISTTTOK Team


Introduction:Traditional Architectures

• Small tokamaks usually rely on pre-programmed waveforms for open-loop control of plasma parameters

Tokamak:

Sensor(Magnetics)

Sensor(Interferometry)

WaveformGenerator #1

Actuator(Power Suplies)

Actuator(Gas Puffing)

WaveformGenerator #2

DATAACQUISITION

SYSTEM

“Trial-and-error” type operation

Hard to get similar discharges, as the plasma is a multivariable complex system

Reprogram of waveforms is normally an empiric and lengthy task•Data acquired needs to be correlated manually against control waveforms


Plasma Control

• Plasma close-loop control on medium/small tokamaks example:

Tokamak

Sensor(Magnetics)

Actuator(PSU)

Sensor(Pressure/

Interferometry)

Single-Input Single-Output (SISO) ANALOG controllers

Not easily Re-configurable Hard to Optimize Allows only simple control

schemes (e.g PID) Control of Plasma

Parameters is NOT coupled!

Actuator(Gas Puffing)

Controller #1(PID)

Controller #2(PID)

Sensor XActuator Y Controller #(PID)


Recent digital technologies and tools developed at IST enable a New Paradigm

LOCAL CONTROL

PROCESSOR

D. A

CQ

UN

ITS

D. A

CQ

UN

ITS

ACTUATOR CONTROL

REMOTE PARTICIPATION

TOKAMAKPLASMA

1/10 Gb Ethernet

Db SERVER

DATA ACQ

UNITS

REAL TIME NETWORK

Sensors/Diagnostics

CENTRALCODAC

PSU

GAS PUFFING

FW

FAST SWITCH UNIT

Integrated Digital Control System, Sensors-to-Actuator, based on available low-cost technologies

General Purpose Processors: Intel, PowerPC…

Open-Source Standards and Real-Time Operating Systems: XML, CORBA, SQL, RTAI

DSP - Digital Signal ProcessorsFPGA- Field Programmable Gate Arrays

MIMO Multiple Input- Multiple Output Controller Dedicated real-time synchronous network for

event and timing distribution


Application: The ISTTOK Plasma Control

PCI-TR-512 Acq. & Control Module 8 Diff. Channels @14 bit/

2 Msamples /secGalvanic Isolated. 512 Mbytes of SDRAM Synchronization of clock and

trigger among boards (Master-Slave)Integrated FPGA and DSP for data

processingDigital output for Control Purposes

See Poster 26

ISTTOK Plasma Control System• 12 Magnetic Probes on a poloidal circular section• Fast position determination code running on DSP (128 μs) using 8 signals• Two PWM controlled PSU for Vertical and Horizontal Equilibrium Fields• Data transmitted to PSU by optical connection


Next Step: Upgrade of ISTTOK Plasma Control

Present ISTTOK Tomography Diagnostic: Three pinhole camera Each camera with 10 active channels Two different reconstruction methods

Fourier-Bessel Algorithm (Faster ~40 μs)Neural-Network (~400 μs)

Reconstruction algorithms running and tested on a standard PC with RTAI OS

See Poster P13

Goal: Multi-Diagnostic Plasma Control System• Magnetic reconstruction using 12 probes(+), Vloop and Rogoswky coil• Tomography reconstruction used when magnetic reconstruction fails to give reliable results ( e.g. during current inversion in AC operation)

HFS

LFS


New system overview

GAS INJECTION

Gateway

Local Processing Node(ATX Motherboard/ PCIe)

WWW

Ethernet 1/10Gb Switch

Digitizer Boards

ATCA ChassisFIRESIGNAL SERVER

POWER SUPPLIES

\

Low Cost Controling Module

(dsPIC)

RS485

\

Low Cost Controling Module

(dsPIC)

RS485

POSTGRESSQL SERVER


ATCA-Based System

Why ATCA? Reliable mechanics (serviceability, shock and vibration)

High security and regulatory conformancesHighly configurableRobust power infrastructure and large cooling capacity (200W per board)Ease of integration of multiple functions and new featuresSupports 14 slots in 19” cabinet or smaller versions

Ability to host multiple controllers and storage on a shelf


ATCA Backplane Topologies

Advanced ATCA Interface Topologies

DUAL-STAR BACKPLANE FULL MESH BACKPLANE

Multi-protocol support for interfaces up to 20 Gb/sEach slot is interconnected through up to four 2.5 Gb/s links with an

actual throughput capacity of ~800 MByte/s per linkScalable aggregated shelf capacity to 2.5Tb/s


Low-Cost ATCA Controller-Processor Module

ATCA™ Processor Blade

ix86Intel®

multi-core

NORTH+

SOUTHbridges

DDR2 DRAM

10 GB/s

PCIeslot

GbitEthernet

port

RS-232port

ATMAdd-on

card

X16 8GB/s FDX

PCIeswitch

PCIeswitch

X8 4GB/s FDXX16 8GB/s FDX

12 ATCA channels(2 to 13)

X4 2GB/s FDXeach

ATCApower

ATCA Fabric channel

PCIeswitch

X16 PCIe female

connector

7-213-8

X8 4GB/s FDX

8GB/s8.5 GB/s

ATCA™ Processor Blade

Based on a PC plain ATX Motherboard with PCIe, assembled on a specially designed ATCA Carrier Board

Any Processor in the ix86 multi-core familyEasily upgraded to higher processing powerProcessing power over 40 GFLOPS and a set of SIMD instructionsPlain Linux or Real-time OS (RTAI)

Connected to the PCI Express™ switch fabric of the ATCA™ carrier by an ×16 full-duplex link (8 GB/s) directly from its Northbridge

Occupies 2 slots of the ATCA shelf


ATCA 32-Channel Digitizer Module

32x Clock

X4 PCI ExpressTM 2GB/s

XilinxVirtex4

FX60/FX100FPGA

ATCATM digitizer/(waveform generator)

Main board

DDR2SODIMM512MB

RS-232

11x AuroraTM 500MB/s

Gbit optical

8x GPIO

8x EIA-485

RTM connector

ATCA Fabric connector

carrier board connector

64x GPIO

Front panelstatus/ctrl

ATCATM power connector

ATCATM update channel & clocks

connector

IPMC

timing

32 Analogue differential Inputs ±32V dynamic range, 18-bit resolution Anti-aliasing filters and Galvanic isolation Simultaneous sampling at 2 MHz

programmable Decimation down to 1 kHz on the FPGA

Optional I/O Rear Transition Module: 8 analogue 16-bit/50MSPS8 digital input/output channels

(EIA-485)1 fiber optic port

(x1 full-duplex 500 MB/s) SFPRS-232 interface

Developed for JET Vertical Stabilization Enhancement Project EP2

ATCATM Digitizer/ Waveform Generator carrier board

ATCATM leds

32x Clock

64x GPIO

Front panelstatus/ctrl

Channel 32

ATCATM Front Panel

Signal conditioning

Reset

main board Connector

4x DB37 connector

32x isolateddifferential

analogInput±32v

ADC18-bit

2MSPS

1kVIsolation

Channel 2Channel 1 ADC module

Signal conditioning

1kVIsolation

ADC18-bit

2MSPS

Digitizer

Main board

DigitizerCarrier board

ATCA

BUS

Optional RTMI/O

ATCA MODULE


ATCA FAST Data Acquisition Module

SyncRef CLK

Analog inputs 4-7

ATCATM Backplane

ATCA Fabric Connector

PCI EXPRESS SWITCHPex 8516

Analog inputs 0-3

Clock Synthesis

XilinxTM FPGAVirtex 4

XC4VFX60-10FF1152

DDR 21 GB or 2 GB

4x 13bits

100 MHz

Clock Synthesis

Analog-to-Digital

Converter Block

4-channels Block #1

4-channels Block #2

Update channel & cloks

connector

4x ATCA clock

ATCA Power Connector

IPMB HAIPMC

channels 3-12

channels 1-2

5 x 1x Aurora

4 x MGTs

4 x MGTs

4x PCIe 2 GB/s

48 VATCA Compliant

200W Power Input Module

12v

Analog Power

Digital Power

ATCA Digitizer Module 8 channel with up to 250 MS/s@13bit

High Power FPGA Multi-rate filtering based on events Local Control algorithms Can Implement PHA and data reduction in

real-time Developed for JET Gamma Ray Spectroscopy

Enhancement Project EP2


Digital Link for the Actuators

ATCA SHELF REAR PANELS

SFP

DIGITAL LINKS

2.5 Gbit/s

ANALOGUEOUTPUTS

DIGITALIO

(RS485)

SFP

DIGITAL LINKS

2.5 Gbit/s

ANALOGUEOUTPUTS

DIGITALIO

(RS485)

SFP

DIN41612

62.5/125 um Duplex

Optical Fiber

BUFFERS

XILINXVIRTEX

2FPGA

T3P DIGITAL LINK CARD

Controller sub-rack

DB9

DIN41612

RS-485 INTERFACE CARD

OGSL Option

EHSL Option

DB-37 to DB-9 RS-485 cable

BUFFERSdsPIC

μP

TP3 - Hard real-time communications protocol for Trigger, Timing and data Transport (Developed under JET Vertical Stabilization Enhancement EP2 Project)

OGSL - Optical gigabit serial link• Transmits the control signals to the actuator units, enough to attain low loop delays (< 1us).• Developed for JET Vertical Stabilization Enhancement Project• Fiber optic SFP LC-Duplex connector (850 nm over 62.5/125 μm fiber)• Full-duplex communications with programmable signaling rate from 622 Mbaud to 3.125 Gbaud

EHSL - Electrical high-speed serial link• 2/4 wire RS-485 (ANSI TIA/EIA-485-A) • Up to 8 half-duplex or 4 full-duplex channels on a 37 pin D-sub connector• Programmable signaling rate up to 30 Mbaud


Firmware Tools• Hardware Level

– FPGA: Data Reduction, Pulse Processing, Timing, Event Detection and Distribution• VHDL, Verilog, (in future directly SCILAB, MATLAB, etc)

– DSP: Fast plasma position determination and PID control algorithms• C, Assembly

– dsPIC: PWM control of PSU• Assembly

Example 1: Block Diagram of real time sampling decimation

.....BLOCK #8BLOCK #2

BLOCK #1

64 BIT TIME TRIGGER REGISTER

DSP EMIFA ADDRESS

AND CONTROL

DUAL-PORT RAM8 X (2 x 256 16-bit words)

INTERRUPT LOGICDSP INTERRUPTS

FPGA XC3S2000

2 MHz clk

SYNCHRONIZATION LOGIC

CONTROL LOGIC

TIMING LOGIC

INTERFACE LOGIC

ADC SERIALDATA

DSP EMIFA64-BIT DATA

16 bit De-SERIALIZER

DECIMATION FIR (8↓)

DECIMATION FIR (8↓)

3:1 MUX

32 MHz clk

TRIGGER

SYNC

8 DECIMATION BLOCKS

Example 2: Block Diagram of real time PHA Implementation in FPGA for

Gamma Ray Spectroscopy


Software Tools

• Local Processor Node– RTOS: Real time multi-diagnostic reconstruction and control algorithms

• RTAI, C / C++– FIRESIGNAL “Node”: Data storage, parameter programming and integration in

the general control and acquisition system (FIRESIGNAL SERVER)• C++ Code/ CORBA• Event Based• Configuration data described in XML format • Standardized hardware description


Summary

Small tokamaks are adequate platforms to develop Control and Data Acquisition Systems using State-of-Art digital technologies and tools (PCIe, ATCA, RTAI, XML)

IST/CFN’s future work will build on previous developments towards ITER relevant solutions

New machines (or enhancements of the existent) represent crucial opportunities to explore new concepts compatible with ITER requirements with benefits to the ITER CODAC Specification

Common remote collaboration tools and unified data description methods will boost collaboration between Labs

Real-Time Digital Systems for Control on Small Tokamaks

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