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RD Collaboration Proposal:Development of pixel readout integrated circuits forextreme rate and radiation

ABSTRACT: The present hybrid pixel detectors in operation at the LHC represent a major achieve-ment. They deployed a new technology on an unprecedented scale and their success firmly es-tablished pixel tracking as indispensable for future HEP experiments. However, extrapolation ofhybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose anew RD collaboration specifically focused on the development of pixel readout Integrated Circuits(IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hitrates (1-2 GHz/cm2), unprecedented radiation tolerance (10 MGy), much higher output bandwidth,and large IC format with low power consumption in order to instrument large areas while keepingthe material budget low.We propose a collaboration to design the next generation of hybrid pixel readout chips to enablethe ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS mustuse the same exact pixel readout chip, as most of the development, test and qualification effortneeded is independent of the specific implementation of the final chips. Multiple implementationsare possible using the same technology foundation, which is the subject of this proposal. In orderto be effective, this collaboration is specifically focused on design of hybrid pixel readout chips,and not on more general chip design or on other aspects of hybrid pixel technology.The collaboration will have an institute board which will elect spokespersons to organize activitiesaround work groups. The following institutes are participating at the time of this proposal: fromATLAS: Bonn, CPPM, LBNL, LPNHE Paris, NIKHEF, New Mexico, UC Santa Cruz; from CMS:Bari, Bergamo-Pavia, Fermilab, Padova, Perugia, Pisa, PSI, also RAL, Torino; from both: CERN(also on CLIC) and RAL.

Contents

1. Introduction 2

2. ATLAS and CMS Phase 2 Upgrades 2

3. State of the Art of Hybrid Pixel Readout 4

4. ATLAS and CMS Phase 2 Pixel Detector Requirements 5

5. Chip Architecture and Design Elements 75.1 Data Rate and General Considerations 75.2 Logic Cell Library 95.3 Global Optimization and Simulation Framework 95.4 Analog Front End and Array 105.5 Command and Data Processing, and Input/Output 115.6 Low Power Design and Power Distribution 115.7 System Circuit Blocks 12

6. 65nm Technology 136.1 Radiation Tolerance 136.2 65nm Foundry Services Frame Contract (FSFC) 146.3 Design Flow and Tools 14

7. RD Collaboration Organization 15

8. Collaborators and Institutes 17

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2 ATLAS AND CMS PHASE 2 UPGRADES

1. Introduction

This document describes the motivation, challenges, and approach to form an ATLAS-CMS in-tegrated circuit R&D collaboration to develop the next generation of pixel readout chips, neededfor the High Luminosity LHC detector upgrades. This proposal was preceded by a letter of intentsubmitted in February 2013 [1]. The proposal is deliberately focused specifically on the design ofa hybrid pixel readout chip for the rate and radiation expected in the ATLAS and CMS phase 2upgrades. While there are close connections to other applications (such as future linear colliders),other aspects of hybrid pixel technology (such as sensors), and alternatives to hybrid technology(such as monolithic active pixels), as will be seen in the sections that follow, the requirements weaddress are extreme and vast enough to demand a focused effort.

We refer to pixel readout chips in terms of generations, with the present ATLAS and CMSdetectors containing 1st generation chips [2, 3]. 2nd Generation chips have been developed andfabricated and will start to see operation in the coming years. The development proposed herewould lead to the 3rd generation chips [4]. In terms of requirements, the difference between gen-erations can be appreciated in Table 3, where it is clear that a large step forward from the currentstate of the art is needed. A 3rd generation pixel chip will contain approximately 5×108 transistors,which is more than any single core computer processor ever had (only multi-core processors brokethe 1 billion transistor barrier). The state of the art, including prototypes aiming at 3rd generationdevelopment, is discussed in Section 3.

Section 2 provides the context of ATLAS and CMS Phase 2 upgrade plans, including triggeringconcepts. The requirements for the pixel detectors to be developed are summarized in Section 4,and they are carried through to chip design elements and concepts detailed in Section 5. Section 6discusses the 65 nm CMOS technology that we are proposing to use, with the caveat that furthercharacterization work is still needed to conclude that this technology can indeed meet the designrequirements. Such work is an important part of the scope of this proposal. Finally, the organizationof the proposed collaboration is described in Section 7, with a list of current collaborators given inSection 8. Section 7 includes a description of work groups and proposed milestones.

2. ATLAS and CMS Phase 2 Upgrades

The present ATLAS and CMS detectors have been designed for nominal operation at 1034 cm−1s−1

and 25 interactions per bunch crossing. During the 2012 run, the luminosity already approachedthe design value and, since the LHC operated with 50 ns between crossings, the pileup exceededthe design value. While both detectors operated well in these conditions, there were importantlessons learned for operation in the remainder of the decade, where the luminosity and pileup willsignificantly exceed design values and the experiments will take advantage of all available operatingmargin. But not all subdetectors have the same amount of design margin. In fact, the present pixeldetectors have the least amount of margin and therefore both experiments are installing or buildingnear-term pixel upgrades [5, 6] to meet requirements for the remainder of the decade. ATLAS isinstalling a 4th pixel layer (called IBL) just outside a new, smaller beam pipe, as well as upgradingthe readout bandwidth of the outer 2 pixel layers, while CMS is building a new, 4-layer pixeldetector with increased readout bandwidth. The rest of the trackers of ATLAS and CMS will be

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2 ATLAS AND CMS PHASE 2 UPGRADES

able to push operation to the needed level with only off-detector electronics improvements, but notbeyond [7, 8].

For the Phase 2 upgrades in the next decade, not only will the luminosity and pileup againdouble or more compared to the end of this decade, but the trigger rates will necessarily increaseas the experiments grapple with triggering on high pileup events that essentially all look alike(every event is to first order a collection of many uninteresting pileup interactions, with the physicssignals of interest being perturbations on top of that). An important lesson from the 8 TeV run isthat tracking can be used to build powerful tools to mitigate the effects of pileup in a wide rangeof objects measured by other subdetectors: jets, missing transverse energy, luminosity, lepton andphoton isolation, etc. Both experiments plan fundamental changes to their trigger and readoutstrategies in order to use tracking information in trigger decisions as early as possible [9, 10].Additionally, the Phase 2 detectors must withstand significantly higher levels of radiation. Finally,new physics analysis techniques have emerged that place new requirements on future trackers, thatwere not appreciated for the present generation. Techniques that concentrate on highly boostedjets require that track reconstruction work efficiently in very collimated particle jets, where particletracks remain close to each other over long distances. This demands small pixels and thin sensors,and not only for the inner layer: half of all 1 TeV QCD jets have 2 or more charged particles within10 mr of the jet axis.

The ideal tracking detector (pixels included) for Phase 2 would read out all information forevery single bunch crossing, perform fast reconstruction in near real time, and only then applytrigger criteria to filter events. However, full readout ATLAS and CMS tracking detectors is notthought possible on a Phase 2 timescale. Instead, both experiments aim to implement some formof on-detector data reduction in order to read out partial information either for every crossing, oron a high rate level 0 trigger (of order 1 MHz). Two different techniques are proposed for this datareduction. The region of interest (ROI) method reads out only parts of the detector for each level 0trigger. Which parts are defined by projections from the calorimeter or muon objects that triggeredthe level 0 in the first place. Assuming that just 10% of the detector is read out each time, thismethod can reduce the data volume by one order of magnitude. This is the method proposed in theATLAS letter of intent [9]. The self-seeded method uses interconnects between detector layers tocorrelate the hits from different layers in real time, in order to select only hits that are consistentwith tracks from near the interaction point above a pre-defined momentum threshold [11, 12, 13].Since most hits are due to low momentum particles, this method has the potential to reduce thedata volume by more than one order of magnitude, making readout of limited information forevery event feasible. This method is being considered as a primary option by CMS. Both methodsneed a further readout step (Level 1 trigger) where the full information from the whole detectoris retrieved for off-line analysis. The inclusion of pixel information in these trigger chains is notyet well defined. Early pixel information would allow powerful algorithms to be included in theLevel 1 decision (for example association of objects to a vertex), but both the ROI and self-seededmethods offer diminishing returns for data reduction in low radius pixel layers. In the case of ROI,since the interaction region (IR) is extended along the beam direction and all regions must coverthe full IR, the regions grow to a fraction of each layer much greater than 10% at small radius.For the self-seeded method, the momentum threshold that can be resolved decreases with radius,which means more and more hits become consistent with high momentum tracks (CMS has only

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3 STATE OF THE ART OF HYBRID PIXEL READOUT

proposed using the self-seeded method at radii greater than 20 cm). Therefore, potential inclusionof pixel information in a Level 1 decision rests on our ability to read out future pixel detectors withthe highest possible bandwidth.

The baseline pixel detector technology for Phase 2 ATLAS and CMS is hybrid pixels- thesame as for the present detectors and near-term upgrades. There is also interest and R&D intomonolithic active pixels (MAPS) as an alternative that could significantly reduce cost. While wedo not include investigation of MAPS in the scope, most of the work on this proposal would beapplicable to a MAPS solution. A MAPS pixel chip for ATLAS or CMS would either replacethe sensor only and not the readout chip [14] (therefore a readout chip must still be developed),or, in case of a truly monolithic solution, such a monolithic chip would need the same radiationtolerance, logic density, verification and simulation tools, etc., that are the subject of this proposal.in the former case of MAPS sensors used instead of diode sensors, the analog front end can begreatly simplified to receive digital signals from MAPS sensor subpixels, but the rest of the readoutchip would remain unchanged.

Much of the design foundation to be developed in this proposal would be applicable to otherlarge format pixel ASICs with complex functionality for future colliders. Although data rates,radiation levels, and trigger requirements are different, there is synergy with the development ofpixel detectors for future e+e− linear collider detectors. A hybrid pixel detector based on 65 nmCMOS readout is already under development for CLIC [15] and collaboration with this effort oncharacterization, certain circuit blocks, and simulation framework is foreseen within this proposal.

3. State of the Art of Hybrid Pixel Readout

The state of the art is embodied by the near term pixel upgrades under construction or advanceddesign for ATLAS and CMS, as well as by the Medipix [16] and Timepix [17] chips. Whilethe CMS pixel upgrade is based on a modified version of their present, 1st generation chip in250 nm CMOS [8], the other examples are all 2nd generation chips in 130 nm CMOS. A salientcharacteristic of 2nd generation chips is the use of synthesized digital logic within the pixel matrixfor the first time.

The most relevant example for the present proposal is the FE-I4 chip [18] being used to buildthe Insertable B-Layer upgrade of ATLAS. The FE-I4 improves upon the current ATLAS pixel de-tector in terms of 40% smaller pixel size, hit rate a factor of 5 higher, die area devoted to peripheryof 10% instead of 30%, full reticle die size (to minimize bump bonding cost), and higher radiationtolerance (requirement of 3.5 MGy). Important advances of FE-I4 include the use of commerciallogic cells fully synthesized as part of the pixel matrix, and a so-called “region” readout archi-tecture which combines all digital processing from every group of 4-pixels into one synthesizedlogic block. This block performs the analog to digital conversion, hit storage, and time look-backretrieval functions previously relegated to the chip periphery [19]. Thus about half the area and thegreat majority of the transistors within the pixel matrix consist of synthesized logic, permitting asmall periphery. Placing most digital processing within the pixel matrix allows to sustain higher hitrates while reducing digital power, because most hits are held within their respective region untilthe trigger latency expires, and then erased, with no need for high data bandwidth between pixelsand periphery. The price of local digital processing is that digital noise injection into the front end

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4 ATLAS AND CMS PHASE 2 PIXEL DETECTOR REQUIREMENTS

must be controlled, and clocks and trigger signals must be distributed throughout the pixel ma-trix. Power distribution and substrate isolation options available in the 130 nm CMOS process usedwere critical to achieve these goals, as were the excellent digital design tools available for modernprocesses.

A significant amount of preliminary work leading up to or relevant to this proposal has beencarried out by different groups over the past 2-3 years. A workshop was held at CERN in Nov.2012 [20] to collect the experience from such activities and in fact the concept for this collaborationoriginated in this workshop. Test devices have been produced to investigate radiation tolerance [21](discussed later). A small-scale analog pixel matrix to demonstrate analog performance and fea-sibility of scaling to the desired small pixel size has been produced [22] and radiation tested [23].Experience with 65 nm technology has also been gained from other test devices already producedor being produced [15, 20, 24].

4. ATLAS and CMS Phase 2 Pixel Detector Requirements

The requirements for phase 2 hybrid pixel detectors are similar for ATLAS and CMS but notidentical. They are driven by the same physics, the same need to trigger on high pileup events, thesame radiation exposure, etc. On the other hand they must respect different boundary conditionsand historic choices of the two experiments, on the magnetic field, the trigger and DAQ parametersand on the pixel geometry. A selection of important requirements is given in Tables 1 and 2. Thesetables are meant to show a snapshot of the present state of requirements, which are expected toevolve as the experiment designs become more refined. Interaction between chip design, sensorR&D, and trigger and data acquisition will help shape the final requirements. In many cases thereare different possible options and these are indicated by giving alternate values in parentheses, or inthe case of trigger and readout with A, B, and C labels. Both the desired pixel area and the readoutrate go well beyond the current state of the art in hybrid pixel readout chips, which was discussedin Section 3. Section 5 elaborates how these requirements translate to readout chip design, andwhat system concepts are the starting point for this proposal.

The Phase 2 pixel detector systems and ASICs will have to support the highest data rates inthe harshest radiation environment of any detector in a LHC experiment. At the same time theymust increase resolution over that achieved today while keeping power consumption the same orlower. Power consumption is constrained by the material and therefore cooling budgets, as wellas services. Therefore, designing electronics with minimum power dissipation becomes a vitalconstraint. The other severe design constraint is not merely surviving, but working reliably inan unprecedented radiation environment of 10 MGy Total Ionizing Dose (TID) and 1016 n.eq./cm2

over 10 years. This level of radiation tolerance is a unique requirement for this application. Adedicated effort is needed to investigate such high radiation tolerance and this will be a centralconcern of this collaboration.

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Parameter or Feature ATLAS CMSlayout

layers 4 (option 5) 4Barrel length 91 cm - 140 cm 55 cm

radii (mm) 38, 78, 155, 250 30, 68, 102, 160Disks 2 × 6 2 × 3 (option 2 × 5)

Endcap radial range 150–315 mm 45–161 mmZ range 877–1675 mm 391–516 mm

Pseudorapidity coverage 2.7 2.5 (option higher)Active area 8–12 m2 3–4 m2

ASIC size ≈ 4 cm2 ≈ 4 cm2

Number of readout chips 15k–25k 8k–12kinner barrel 1 × 2 chips 1 × 4 chips (1 × 2)

Module size other barrel 2 × 2 chips 2 × 4 chips (2 × 2)disks 2 × 2 chips (3 × 2) 2 × 4 chips (2 × 2)

Hit rates and radiationInteractions /25 ns 200 (140 w/leveling)

Particle flux inner barrel <500 MHz/cm2

≈ 1 GHz/cm2 ≈ 2 GHz/cm2

Pixel hit rate inner barrel (30 KHz/pixel 25×150 µm2) (50 KHz/pixel 25×100 µm2)(100 KHz/pixel 50×100 µm2)

10yr, 3 ab−1 TID 10 MGy1 MeV n. eq. 2×1016

SEU tolerance Re-configure <1 module/lyr/hr<0.1% hit data loss

SensorPolarity negative negative (TBC)

Signal MIP charge 10 Ke− 5-10 Ke−

Max. charge TBD linear up to 2 (4) MIPPixel max. capacitance 200 fF (<400 fF) 200 fF TBC

Pixel max. leakage current 20 nA (<100nA) 20 nA TBCReadout Chip

Hit loss at max rate <1% <1%minimum ≈ 1000e− ≈ 1000e−

Threshold dispersion (tuned) < 100e− < 200e− (100e−)variation w/time < 100e− < 200e− (100e−)

Min. thr. noise occupancy < 10−6 < 10−6

Hit time resolution 25 ns 25 ns4-8 bits

Charge measurement TBD Resolution to TBD bydetector simulations

Table 1: Part 1/2 of Pixel detector requirements for Phase 2 from ATLAS and CMS. Where differ-ent options exist alternate values are given in parentheses, or in the case of trigger and readout withA, B, and C labels. TBC (TBD) stands for To Be Confirmed (Determined).

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Parameter or Feature ATLAS CMSL0 trigger rate / max. latency A: 0.5 (1) MHz / 6.4 µs A: 0.1 (0.2) MHz / 6.4 µs(buffering in pixel regions) B: ROI at 1 MHz / 6.4 µs B: ROI at 1 MHz / 6.4 µs

C: 1 MHz, 20 µsL1 trigger rate / max. latency A: none A: none(buffering in regions or EOC) B: 200 KHz / 20 µs B: 100 KHz / 20 µs

C: noneReadout link A: 2-3 Gbps serial 320, 640, and 1280 Mbps

B: 320 or 640 Mbps serial e-links to LPGBTPower Budget 0.3 W/cm2 <0.4 W/cm2

Serial power option On-chip Shunt-LDO reg. On-chip Shunt-LDO reg.DC-DC option On-chip DC-DC ratio ≥4 On-chip DC-DC with

module DC-DC near-byOperating temperature Specs met -40◦C to +40◦C -40◦C to +80◦C

Basic functions to +80◦CControl interface ≥80 MHz 8b10b serial in 40/80 Mbps e-link from

clock recovered from above LPGBT; 40 MHz clock

Table 2: Part 2/2 of Pixel detector requirements for Phase 2 from ATLAS and CMS. Where differ-ent options exist alternate values are given in parentheses, or in the case of trigger and readout withA, B, and C labels. TBC (TBD) stands for To Be Confirmed (Determined).

5. Chip Architecture and Design Elements

5.1 Data Rate and General Considerations

For an assumed maximum pixel hit rate of the order 1-2 GHz/cm2, a 4 cm2 pixel ASIC must inter-nally handle a raw data rate of the order of 4 cm2× 1.5 GHz/cm2 x B bits, where B is the number ofbits per hit pixel needed to store all pertinent information about the hit. Since this information is tobe stored locally, the pixel location is known, so one must store just time (which bunch crossing)and charge. Taking B = 16 gives 100 Gb/s. Requiring on-chip data buffering during a 20 µs L1 trig-ger latency adds up to an information storage need of 2 Mb per chip with a refresh rate of 100 Gb/s.To accommodate without overflow local fluctuations in the data rate, the amount of memory needsto be a factor 6 to 8 times larger, getting to a required buffering capability of the order 16 Mb perchip. For a scenario with a 1 MHz trigger rate, the readout bandwidth per pixel chip will be ofthe order of 4 cm2 x 1.5 GHz/cm2× B′ bits × 25 ns × 1 MHz, before any compression/clusteringdone on chip. Taking B′ = 24 gives 3.6 Gb/s. A different number of bits, B′, is needed for outputbecause the pixel location must now be encoded, while time information can be suppressed as hitsare associated to a specific trigger. While these are order of magnitude estimates, data compressiontechniques to reduce the physical output bandwidth must clearly be studied. Table 3 compares theamount of hit memory per chip and data output bandwidth for different generations of pixel readoutchips.

The handling and processing of the high rate pixel hit information can be addressed with a dis-

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1st generation 2nd generation 3nd generationHit memory per chip 0.1 Mb 1 Mb 16 MbChip output bandwidth ≈40 Mb/s ≈320 Mb/s ≈3 Gb/s (*)

Table 3: Hit storage memory and output bandwidth needed for a third generation pixel chip com-pared to first and second generations. (*) Before advanced compression techniques to be developed.

tributed architecture as in FE-I4, which implies a tight and delicate integration with the low noiseanalog front-ends per pixel. A block diagram of a hierarchical chip organization based on this ar-chitecture is shown in Fig. 1. Acquired pixel hit information must be processed and stored reliablyin the hostile radiation environment. One can expect several digital storage elements (e.g. pixeldata, configuration data, state machines) on the chip will have its content corrupted by radiationinduced Single Event Upsets (SEU) every second.

Current generation LHC pixel detector chips have a power dissipation of the order of 0.3 W/cm2,which already in current pixel systems implies significant challenges for cooling and power distri-bution services for a low mass detector. Since a similar cooling performance is assumed in orderto keep mass low, a new phase 2 pixel chip must have a comparable power budget. This is a verychallenging constraint, when considering the extremely demanding requirements (2-4 times morepixels, 10 times the hit rate, 4 times latency, 10 times the readout rate).

The determination of pixel size is a critical and complex optimization between granularityneeded for physics, circuit density, functionality (e.g. charge measurement vs. binary), sensor de-sign and interconnect, and power consumption. This depends on many parameters which are notyet fully determined. Our design starting point is the smallest possible pixel area compatible withthe memory and functional requirements. While the inner pixel layer will use the finest availablegranularity, outer pixel layers may choose to use the same pixel chip with a coarser granularity sen-sor by only bonding one half or one quarter of the ASIC channels, with unused channels powereddown. Based on early prototyping, the initial goal set by the ATLAS/CMS pixel RD collaborationis to evaluate a 25 um × 100-150 um pixel size (or any other aspect ratio with same area).

We must also study the implementation of dedicated functions to enable the pixel detector tocontribute track information to a first or second level trigger. A self-seeded trigger method mayrequire dedicated high speed local communication between pixel layers and perhaps correlationlogic or associative memory within the pixel chip. While probably not a realistic approach for theinner layers (see Sec. 2), self-seeded triggering may be required for some outer pixel layers. Pixeldetector layers may alternatively be required to contribute extracted/compressed cluster informa-tion to an ROI trigger method. Both approaches must be studied within the context of the pixelchip architecture and system optimization.

Test, monitoring and (auto) calibration features must also be integrated in the system to enableits efficient use in a large and complex detector with no physical access when installed in the centerof the experiments. Finally, on-detector power conditioning (including regulation and DC-DCconversion) is by now a well established requirement for tracker upgrades in both experiments.Fully on-chip regulation and DC-DC conversion must be considered in the pixel chip design.

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5.2 Logic Cell Library

This is in a sense the “make or break” element that must be developed. Of the 5×108 transistorsin a 3rd generation chip, the vast majority will be synthesized by commercial tools using a logiccell library. A sufficiently radiation tolerant low power digital library must therefore be madeavailable to the collaboration. This is currently assumed to be a standard cell library from thesilicon foundry with some possible modifications to make it sufficiently radiation hard. In addition,specialized digital cells will be needed: Compact rad hard memories for data buffering, specializedSEU tolerant/immune storage cells, Low power clock distribution cells/network for the pixel array.It is possible that a fully custom logic library must be produced in order to meet radiation tolerancerequirements; this would represent a significant additional effort.

Figure 1: Diagram of pixel chip hierarchical organization, showing how pixels are grouped inregions, regions in columns, and pair of columns in a full matrix.

5.3 Global Optimization and Simulation Framework

As mentioned above, to handle such high data rate the hit information can be stored locally withinthe array as shown in Fig. 1. Storing information from multiple hits from the same cluster togethertranslates into significant savings in required storage resources. Sharing of latency buffers in partic-ular leads to compact circuitry and low power. The exact way in which the hit data are stored mustbe optimized for the new requirements and technology. What this means in practice is understand-ing how many pixels share storage logic (so-called regions), in what pattern, with what internalorganization, and how are region boundaries handled. FE-I4 uses 2×2 pixel regions that were theresults of an optimization carried out for that design. This optimization does depend on clustersize distributions, which in turn depend on sensor type and location in the detector, and on physicsinput. It is also necessary to consider the grouping of the sensitive analog circuits into well isolated

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“analog islands”, which will depend on the process options and on how power is distributed withinthe chip.

To effectively perform such complex optimizations at all levels of the architecture, a dedicatedpixel simulation and verification platform will be an indispensable development tool. This platformmust be capable of simulating alternative pixel chip architectures at increasingly refined level asthe design progresses. Automated verification functions must be part of such a framework to en-able extensive simulations of large sets of pixel hits and triggers to be performed in an automatedfashion for global architecture evaluations and for all incremental extensions and refinements ofa final design. Large data sets of realistic (and extreme) pixel hits and triggers can be generatedwith given constrained random distributions within the framework. Particle hits from external fulldetector/experiment Monte Carlo simulations and detailed sensor simulations can be imported andmixed with statistically generated hits. A simulation and verification framework tailored the highrate pixel detectors for the ATLAS/CMS upgrades could also be a highly valuable tool for otherHEP pixel detector systems and ASICs in general. CLIC foresees to participate in this develop-ment. Our community has started to look into available and appropriate programming languagesand tools to make such a simulation and verification framework with sufficient versatility. The Sys-tem Verilog language and related tools seem particular promising for this as it enables simulationsat both very high level and detailed gate level and it now has become a very well established toolkitcomponent for all the major CAE tool suppliers. A detailed System Verilog model of the pixelASIC can be synthesized directly into digital gates in the chosen technology using multiple syn-thesis tools from all the major CAE tool suppliers. Our community has initiated a training programamong the digital designers in this to get a head start on this as efficiently as possible. Establishingsuch a common framework is one of the first orders of business of the new collaboration.

5.4 Analog Front End and Array

The analog pixel front-end must be carefully optimized for the lowest possible power consumptionwith acceptable noise and detection thresholds. The sensor load capacitance and leakage currentdetermine not only the power but also the complexity of the amplifier. While this is well known,the design collaboration will stress this point with the sensor and system development efforts ofboth experiments. In addition to more power, a 400 fF load with 100 nA leakage current needsa very different and larger area front-end than 200 fF with 20 nA leakage, which in turn is verydifferent than sub 100 fF and negligible leakage. It is likely that there will be different front enddesigns developed targeting different requirements in addition to input load, for example for chargemeasurement method, sensor type, operation with multiple pixel granularities, etc. It is likelythat if ATLAS and CMS eventually fabricate different chips, they will have different front endcircuits. However, the replication of the analog front ends into an array, the distribution of powerand bias, the isolation methods, etc. can be solved by one common design. These are in factvery challenging problems that require tight coupling with the digital region design, the simulationframework and the layout hierarchy. Obtaining a low effective detection threshold (1000 e−) withgood uniformity across the whole pixel matrix in the presence of large amounts of digital logic isa main common challenge. Different approaches for signal amplification and charge digitization(Time Over Threshold or individual/shared ADC) will be studied and characterized to identify thebest compromises between flexibility, performance, power consumption, silicon area, etc.

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5.5 Command and Data Processing, and Input/Output

When hit/cluster information related to a trigger have been extracted from the localized data buffersin the pixel regions, they must be collected, merged, and formatted. This is generally done in threesuccessive stages: 1: pixel cells/regions in same column, 2: merging data from multiple columns inthe End Of Column area (EOC) and finally 3: between pixel chips on the same pixel module, to getdata into a single high speed readout link. In a third generation readout chip, significant processingwill be possible on-chip, after the data have been collected from all the columns. An interestingpossibility is to have user programmable logic and buffering that can allow for different operations.Examples of possible operations include: collecting all the data from the array with a level 0 trigger,buffering in the bottom of chip, and then selecting level 1 trigger data from it. Alternatively, highspeed inputs could bring external data to the chip to look for correlations with level 0 data, eitherwith lookup tables or associative memory. Clustering algorithms could be run on-chip in order tocompress the data and reduce readout bandwidth. One could search for unwanted types of clustersand discard them, or compress selectively depending on the cluster type.

Input configuration and commands to the chip can be standardized to minimize connectionsand maximize reliability. A common command decoding protocol with error correction and clockrecovery could be defined. Communication between multiple chips, including data aggregation,could also be standardized.

High speed serial output drivers will clearly be needed. Compatibility with the GBT projectwill be built in, but for output bandwidth of order 3 Gb/s a dedicated output protocol will be re-quired. Note that while the problem of high bandwidth must be solved for the inner layers ofATLAS and CMS, most of the pixels will be at higher radius, where the output bandwidth will bemuch lower. Thus the same chip should support different data output speeds.

5.6 Low Power Design and Power Distribution

As mentioned earlier, low power is a critical challenge of this proposal. This must be attackedboth at the individual circuit level and at the system level. For the digital part, power dissipationmust be extensively optimized for both static consumption (e.g. leakage currents) and dynamicconsumption minimizing the number of toggling nodes and their parasitic capacitances. Clockdistribution strategies can be used to lower average power, but can also introduce problems of theirown, and a dedicated study to define the power reduction strategy will be needed. This will be tiedto the simulation framework and the design methodology. There are important lessons from 2nd

generation chips that must be analyzed. For example, the FE-I4 chip used region clock gating toreduce the average digital power in the pixel matrix. As a result, when there are no hits the poweris very low, but as the hit occupancy increases so does the power. This non-constant power canlead to variations in the effective threshold of the pixels. Thus it may be preferable for the chip toconsume the maximum digital power all the time, even when there is no occupancy. This is thekind of question that must be studied in order to optimize the design. (Note that cooling systemsare designed for maximum power load, so there is no real benefit for the power to be occasionallylower than the maximum).

Delivering power to front-end ASICs in modern technologies is increasingly challenging asthey use low supply voltages (order 1 V), requiring problematic high currents to deliver a given

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power. The use of local (module and/or on-chip) power conversion or the use of serial poweringapproaches must be evaluated for the system and the pixel chip itself. Power conditioning circuitsincluding local DC-DC conversion, or voltage regulator for serial powering, linear regulators forthe sensitive analog front ends will be an integral part of a pixel ASIC design.There are also hereoptions to be studied. For example, one could consider local regulation distributed throughout thearray, rather than one or two large regulators at the bottom of chip. Distributed regulators wouldhelp with power distribution within the chip, which is a significant challenge in a large format (4cm2) where the inputs are only on one side.

5.7 System Circuit Blocks

Independently of the actual pixel chip architecture implementation and optimization, a number ofvital generic functions are required for a complete ASIC system. Despite that such functions (gen-erally called IP blocks) are relatively common functions found in modern commercial integratedcircuits, they have to be designed and optimized specifically for the pixel application because ofthe very hostile radiation environment with significant TID effects on the basic transistors and radi-ation induced single event upsets. Together they represent a large design effort, but one that ideallylends itself to sharing among collaborating groups. Typically each of these blocks will be designedby a single designer or team at a single institute. These blocks are independent from the possi-ble differences between the final chip implementations for the two experiments. By developingthem within the collaboration framework, we can ensure that they are all designed with uniformguidelines and compatibility and documentation requirements. Similarly, we can apply uniformqualification standards to all. A non-exhaustive list of these blocks follows:

• Current and voltage references. Must provide a stable reference independent of variations insupply voltage, temperature, IC process parameters, and of course radiation.

• Compact low speed (static) Digital to Analog Converters (DAC) are required for generatingadjustable analog biases.

• Analog to Digital Converters (ADC) are required for monitoring (e.g. Temperature, Supplyvoltage, etc).

• Temperature measurement circuit

• Adjustable (and self-calibrating) timing generators are required to align the sampling pointof the pixel detector to the bunch collisions and be capable of making timing sweeps ofcalibration pulses across the sampling clock period.

• Phase Locked Loops (PLL) are required for clock recovery from encoded input and for highspeed serial readout.

• High speed low power output drivers will be required to drive the local data link to thelocation of the final high speed serializer and driver for the optical link.

• Command decoder and clock recovery to process incoming serial input.

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• SEU hard static memory cells. This does not have to be a logic library element, but can bedesigned as an analog block in order to achieve the maximum possible tolerance for storageof configuration values.

• Voltage regulators and DC-DC converters.

• Programmable processors, for example a DSP (digital signal processor) or AM (associativememory block). These could be used for many things, not necessary for processing hit data.For example self testing or of the chip functions could be implemented.

• Analog test and calibration circuits. For example to obtain a chip-by-chip calibration of thecharge injection absolute scale.

6. 65nm Technology

The choice of IC technology is a delicate decision of utmost importance for such a long term andchallenging project. A large majority of the required building blocks have to be highly optimizedfor the specific application and the technology used for its implementation. It will be very difficultto change from one technology platform to another halfway through the project. The starting pointis the 65 nm Foundry Services Frame Contract (FSFC) discussed below, but this proposal is notcontingent on the FSFC. Tolerance to the unprecedented radiation level is one of the prime drivers,but the technology must meet several other specific requirements, which we believe are met by the65 nm node:

• Appropriate for highly integrated mixed analog/digital signal designs

• Sufficient circuit density for both analog and digital functions

• Low power consumption

• Well defined and well supported design kit for complex modern technology

• Flexible access by the HEP community

• Affordable for small prototype circuits and for the very large final pixel chips, and finally

• Long term availability from multiple vendors, as the qualification, design, prototyping, test-ing, and final production will stretch over a relatively long period of 5-10 years.

6.1 Radiation Tolerance

The chosen 65 nm technology (see below) has so far been extensively radiation tested up to a totaldose of 3 MGy with very promising results [21]. For the Phase 2 pixel projects the inner pixel layerthis characterization needs to be extended to 10 MGy. Initial, but very preliminary, indicationshave shown that certain P-MOS transistor parameters may experience a significant degradationabove the 3 MGy level. These studies need to also be extended as a function of temperature.Significant additional work is required to develop an understanding of such effects. In additionto single transistors, characterization must be extended to logic cell libraries. Depending on the

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actual degradation at very high radiation levels, different scenarios to deal with this have to beenvisaged. For a moderate and acceptable degradation, modified transistor simulation models mustbe extracted to allow the degradation to be taken into account during the design phase. However,this might require the creation of a full custom logic cell library. Characterizing and modelinga logic cell library with the precision needed for modern digital design flow is a significant job.The possibility that the technology can not keep sufficient performance after high radiation mustalso be considered. In this case the options will be to explore processes from different foundries,something which cannot be done at a late design stage, or to consider building detectors with lowerTID tolerance than currently desired. This would imply replacement of inner layer(s) at some pointduring Phase 2 operation. CMOS transistors are normally very resistant to Non Ionizing EnergyLoss (NIEL) effects from hadrons (e.g. neutrons). This though has to be verified for the very highflux of hadrons/neutrons expected for the inner layers of a HL-LHC pixel detector. Bipolar devices(diodes, parasitic bipolar transistors) used in certain basic building blocks (e.g. band-gap reference)will most likely become so affected that alternative circuits will have to be developed.

6.2 65nm Foundry Services Frame Contract (FSFC)

The HEP community has in the last few years been evaluating IC technologies to identify appro-priate technologies for the next generation HEP experiments. The current LHC experiments areprimarily based on a 250 nm CMOS technology and on-going developments for Phase 1 upgradeshave to a large extent moved to a 130 nm technology. The 65 nm CMOS technology node has beenidentified as a particular promising technology for long term Phase 2 developments. The 65 nmtechnology node has by several foundries been defined as a “strong technology node” that will beavailable for a long time. It is being used extensively for industrial and automotive applicationsthat require availability over extended periods (in contradiction to technologies for commercialelectronics that today have relatively short lifetimes). It is also a technology that has excellentlow power characteristics and has been shown to be well suited for the low noise analog functionsneeded in HEP applications. It is also the highest logic density node for which thin oxide gatedielectrics are used by all producers, while for higher density nodes manufacturers began switch-ing to thicker high-K dielectrics. Thin gate oxides are a key ingredient for radiation tolerance.Finally it is a technology node that is considered reasonably affordable for the small volume HEPcommunity. CERN has recently finalized a market survey and tender to get appropriate access to a65 nm CMOS technology from the TSMC-IMEC foundry in the form of a FSFC. TSMC (TaiwanSemiconductor Manufacturing Company) is one of the largest IC foundries in the world. IMEC,a well-known European IC research institute, has partnered with TSMC to provide access for Eu-ropean university and small business IC designers to TSMC fabrication facilities. The FSFC willassure reliable and affordable access to the chosen technology together with the required local sup-port. It also gives access to regularly scheduled and relatively low cost Multi Project Wafer (MPW)runs. This is vital for our community during the R&D phase where small test circuits must beproduced to verify functionality, radiation hardness and low power consumption.

6.3 Design Flow and Tools

To be capable of designing such large, complex very high density mixed signal integrated circuitsfor a pixel detector a well defined and powerful “design flow” is needed. The design flow must be

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7 RD COLLABORATION ORGANIZATION

based on available software design tools and must be developed and made available to the commu-nity. This must encompass IC design from low level detailed models of the transistors, includingradiation effects, layout and verification of full custom cells up to the level of global assemblyand verification of a full design with ≈ 5×108 transistors. In a pixel ASIC, full custom designedanalog blocks must be embedded in the globally digital design that has been synthesized from thebehavioral/register level model from the architecture optimization studies. Extensive verificationsand optimizations (design rule checking, timing verification, power distribution verification, powerconsumption modeling, analog to digital isolation, etc.) will be required. Such a large and complexchip should be fabricated with a minimum number of design iterations (Each full wafer iterationcosts 1MCH in a 65 nm technology). Such a design flow will be based on the basic design kit fromthe foundry, commercially available software design tools and additional utilities for verificationwith transistor parameters after radiation. A general design framework will be made available byCERN to the HEP community for the chosen 65 nm technology. Dedicated features and functionswill have to be added to this generic design framework for the design, place and route and verifi-cation of large pixel array chips with highly interleaved analog and digital circuits. To enable anefficient design methodology and exchange of designs between the different groups of the collab-oration, a common 65 nm chip design database will be setup at CERN using a sharing platformsuch as the SOS repository from Cliosoft, Inc. This is similar to a software repository, but devel-oped specifically for IC design, and has already been used successfully for distributed design ofFE-I4. All groups will share all design elements on this common database server. All groups willbe encouraged to use the same design software and 65 nm design kit, but different groups will haveaccess to and expertise with different tools. Such a repository can manage sharing with interfacesto different design tools.

7. RD Collaboration Organization

The proposed organization will have an Institute Board (IB) and Working Groups (WG) on as-pects that are similar or identical for any final chips produced, covering technology, design, andverification. Members from both experiments are expected to contribute to the full work program.Groups participating in other pixel projects (e.g. CLIC pixel) can also become active members ofthe collaboration and contribute actively to some of the WG (e.g 65nm radiation hardness, specificpixel building blocks or development tools).

Within the scope defined in this proposal, the IB will define further details of organization,including modification and/or addition to the WG structure listed here. The formation of an IBwill be the first step to follow within 1 month of formal approval of the collaboration. The IBwill make decisions where possible by consensus rather than voting. The management of thecollaboration activities will be done by two coordinators or spokespersons, one from ATLAS andone from CMS, elected by the IB. The WG’s will each have one coordinator to be chosen asspecified by the IB, and the spokespersons will have regular meetings with the WG coordinatorsto manage the activities. The inclusion of new institutes will be decided by the IB on a case bycase basis. The IB must also generate policies that are necessary for sharing IC design activities,including a publication policy and guidelines for working with intellectual property. These policieswill regulate sharing of information, results, circuit designs and building blocks, and will ensure

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7 RD COLLABORATION ORGANIZATION

appropriate recognition to the people and groups involved. The details of these conditions will becollected in a Memorandum Of Understanding (MOU), to be generated by the IB and signed byrepresentatives from each institute. The use of building blocks for other applications (e.g. possiblecommercial use) should be addressed in the MOU. An internal note category should be created withthe CERN CDS system in order to document technical information as needed, taking advantage ofthe information management structure already available. It is very important to be able to sharesensitive information in a protected way, such as data on radiation characterization and findingsabout technology or circuits protected by non-disclosure agreements.

The RD collaboration will primarily focus on the following aspects:

1. Radiation qualification and characterization of 65nm to very high radiation levels,

2. Development of tools and methodologies to design efficiently large, complex pixel chips,

3. Development and characterization of circuits and building blocks needed for pixel chips.

The main concern of the collaboration is to put in place all the infrastructure that is necessary toproduce a third generation pixel chip, and not to fabricate the final chips that the experiments willuse. Each experiment may require specific functions (e.g. participation to trigger), different inter-faces, different pixel geometry, etc., leading to experiment-specific final design implementations.The intent is that these will share the same basic building blocks when possible and maximize theuse of common chip submissions and radiation test campaigns. If appropriate, the collaborationmay choose to make an early simplified common pixel chip for the R&D program of radiation hardpixel sensors with small pixel size and for system development. A breakdown of the proposedinitial WG structure is given in Table 4, including proposed milestones for each activity.

The coordinator of each WG is expected to organize a detailed technical program and callregular meetings. WG coordinators will on a regular basis report to the IB on progress and theplanned work program. The WG coordinator and the spokespersons should minimize overlappingactivities across the participating institutes and encourage close technical collaboration and sharingin order to cover all the needed aspects completely and efficiently.

We do not anticipate formal financial obligations by members to the collaboration (althoughit is not excluded that the IB may choose to establish a common fund). Members are expectedto obtain support for R&D activities directly from their respective funding agencies. While thecollaboration will not directly fund activities, it will provide important savings by pooling resourcesfor new chip fabrications, as well as the sharing and distributing already existing devices. TheIB may establish methods to account for different contributions from the members in order todetermine cost sharing for chip submissions. These contributions may include irradiation facilitiesand campaigns, test boards and test systems, assembly, commercial software tools, etc.

The collaboration will hold workshops at least once a year with reports and discussions onprogress and evolution of the work program. The IB will also meet at least yearly at these work-shops or otherwise. The spokespersons and the working group coordinators are also expected toorganize specific training in particular domains as the need arises for the progress of the workprogram.

The proposed duration of the above activities is 3 years. It is expected that at that point theexperiments will move to produce final designs, subject to their final specifications and internal

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8 COLLABORATORS AND INSTITUTES

Title Scope Year 1 Year 2 Year 3WG1 Qualification of technology to 10 MGy TID, 1016 n.eq./cm2 IR FR

Radiation transistor simulation models after irradiation FDevaluation of logic cell libraries after irradiation IR FR(*)

WG2 Design methodology & verification of 5×108 transistor IC P FDTop Level Analog integration in large digital chip, power distribution P P FD

Design Synthesis constraints, clock distribution and optimization P P FDWG3 System Verilog simulation and Verification framework P FD

Simulation Optimization of global architecture/pixel regions/pixel - FRTest Bench External system and external physics data - P FD

Verification of test chips and evolving designs - OA OAWG4 Definition of readout and control interfaces (e.g LPGBT) IR FRI/O Definition of standardized I/O protocols and performance IR FR

Implementation of readout and control interface blocks - P PWG5 Evaluate and compare alternate amplifier designs - IR FR

Analog Evaluate and compare charge ADC techniques - IR FRDesign vs. number of bits (TOT, shared ADC, etc.)

Define common requirements for IP block design FRWG6 Evaluate, document, and keep library of IP blocks - OA OA

IP Blocks Generate overview and recommendations IR IREach block will have its own prototyping milestones P P P

Milestone Key: IR=Interim Report, FR=Final Report, P=Prototype, FD=Final deliverable,OA=Ongoing Activity.(*) Add 1 year if a custom logic library must be developed

Table 4: Definition of Work Group activities and milestones. Prototypes don’t necessarily refer tophysical devices, but could be design or software prototypes.

review process. While a common chip design for both experiments is not excluded, the defaultpath is separate designs. Even for separate designs, this collaboration will need to remain in placeduring the final design phase (beyond 3 years), but in a support role rather than an R&D mode.The tools, expertise, documents, and circuit blocks developed would be used by both experimentsand the by then established sharing mechanism will be needed for this. At this point the R&DWG’s may be replaced by a lighter weight structure to be defined. Could be simply a support teamsupported by shared resources.

8. Collaborators and Institutes

A list of physicists and IC designers from currently participating institutions is given below. Thename listed first is the point of contact or PI, while IC designers are followed by a (D) and Ph.D.graduate students by (S). Many institutes will have additional Ph.D. and other students who are notyet identified and therefore not listed. A matrix connecting institute interests to WG’s is given in

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8 COLLABORATORS AND INSTITUTES

Table 5.

• INFN Bari and Politecnico di Bari (CMS group)F. Loddo (D), F. Corsi (D), G. De Robertis (D), F. Licciulli (S), C. Marzocca (D).

• Bonn University (ATLAS group)H. Krüger, Y. Fu (D), L. Gonella, M. Havranek (D), T. Hemperek (D), F. Hügging, I.Kishishita (D), P. Rymazewski (D), N. Wermes.

• CERN (AATLAS, CCMS, LCLIC)J. ChristiansenC (D), D. AbbaneoC, N. Alipour-TehraniL, D. DannheimL, D. DobosA, L.LinssenL, H. PerneggerA, P. ValerioL (D).

• CERN Microelectronics section: PH-ESE-ME will provide support to all users of 65 nmtechnology, including customizing a design kit complete with a customized digital libraryand certain IP blocks, to go along with the FSFC. The members of PH-ESE-ME are notlisted as part of this proposal, but there will be clear synergy as this RD collaboration will beon of the largest “customers” for 65 nm.

• CPPM Marseille (ATLAS group)A. Rozanov, M. Barbero, D. Fougeron (D), R. Gaglione1 (D), F. Gensolen (D), S. Godiot-Basolo, M. Menouni (D), P. Pangaud, A. Wang (D).1 also LAPP

• Fermilab (CMS group)D. Christian, G. Deptuch (D), F. Fahim (D), J. Hoff (D), R. Lipton, T. Liu, T. Zimmerman(D).

• LBNL (ATLAS group)M. Garcia-Sciveres, D. Gnani (D), A. Mekkaoui (D).

• LPNHE Paris (ATLAS group)G. Calderini, M. Bomben, F. Crescioli (D), J.F. Genat (D), O. Le Dortz (D), G. Marchiori.

• NIKHEF (ATLAS group)N. Hessey, R. Kluit, V. Zivkovic (D), V. Gromov (D).

• U. of New Mexico (ATLAS group)S. Seidel, I. Gorelov, M. Hoeferkamp, K. Toms.

• INFN Padova and University of Padova (CMS group)D. Bisello, N. Bacchetta, M. Bagatin, M. Dall’Osso (S), S. Gerardin, A. Neviani (D), A.Paccagnella, D. Vogrig (D,S), J. Wyss.

• INFN Pavia, University of Pavia and University of Bergamo (CMS group)V. Re, F. De Canio (D), L. Gaioni (D), A. Manazza (D), M. Manghisoni (D), L. Ratti (D), G.Traversi (D), S. Zucca (D).

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8 COLLABORATORS AND INSTITUTES

• INFN Pisa and University of Pisa (CMS group)F. Palla, R. Beccherle (D), R. Bellazzini, L. Fanucci, G. Magazzù (D), M. Minuti, F. Morsani(D), A. Rizzi, S. Saponara.

• INFN Perugia and University of Perugia (CMS group)G. Bilei, E. Conti (S,D), M. Menichelli, D. Passeri (D), P. Placidi (D).

• PSI (CMS group)R. Horisberger, H-C Kaestli (D), B. Meier (D).

• RAL (IC group serving both ATLAS and CMS)M. Prydderch (D), S. Bell (D), L. Jones (D), M. Key-Charriere (D).

• U.C. Santa Cruz (ATLAS group)A. Grillo, J. DeWitt (D).

• INFN Torino and University of Torino (CMS group)N. Demaria, G. Mazza (D), L. Pacher (S,D), A. Rivetti (D), M. Rolo (D).

Institute WG1 WG2 WG3 WG4 WG5 WG6Radiation Top level Simulation I/O Analog IP blocks

Bari C A ABergamo-Pavia A C A BBonn C A A B B ACERN B (*) (*) A C (*) A B (*)CPPM A B C C B AFermilab A B ALBNL B A B B A ALPNHE Paris A B A ANIKHEF A A ANew Mexico APadova A APerugia B A BPisa B A A APSI B A C A ARAL B B A CTorino C B C B A AUCSC C B C A

(*)Indicates core competencies of the CERN PH-ESE-ME section

Table 5: Matrix of institute intersts in WG activities. “A” denotes a core capability of the group,“B” high interest, and “C” ability to help if needed.

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REFERENCES

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