RASEDA 2012 - ADC BIST - Ridgetop Group.pdf

Built-In Self-Test Circuit for Total Ionizing Dose Radiation Effects in Analog-to-Digital Converters

Esko O. Mikkola1, Viraj S. Pandit2, Byoung Uk Kim1, and Andrew Levy1* 1Ridgetop Group, Inc., USA

2 Novellus Systems, Inc., USA * Presenter

Presented at: RASEDA, Tsukuba, Japan, December 12, 2012

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

A.Levy RASEDA 2012 Tsukuba, Japan December 12 2012

Outline

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Introduction and ADC BIST Overview

TID Radiation Effects

ADC BIST Operation

Tested ADC

Simulation with TID Models

Ridgetop Group Overview

Summary

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Introduction and ADC BIST Overview (1)

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Innovative Built-In Self-Test (BIST) circuit for monitoring Total

Ionizing Dose (TID) radiation effects in Analog-to-Digital

Converters (ADC)

• Monitors changes in most important ADC performance

metrics affected by TID: • DNL

• INL

• Gain error

• Offset error

• Missing codes

• Designed in a commercial 0.25 nm CMOS process



Introduction and ADC BIST Overview (2)

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• Simulated and verified through VHDL, VHDL-AMS, and

SPICE

• Parts of the system, such as the DAC and ADC have been

fabricated and verified on silicon

• Radiation effect simulations – performed in VHDL-AMS to

prove the effectiveness of the BIST circuit in capturing the

TID-induced parameter drifts in a commercial 8-bit ADC

• The main challenge has been to design the rad-hard, low-

power, area-efficient circuit blocks that create the highly

linear voltage ramp test input used in the BIST



TID Impact on Integrated Circuits

Accumulated charge trapped in semiconductor oxides over time

Measured in rads

Causes gradual IC performance degradation

VT Shift in NMOS/PMOS Devices

Causes offset in analog circuitry

Not generally a concern below 180 nm CMOS

Leakage Current in NMOS Devices

From silicon inversion next to insulation trench oxides

Reduced effect in modern CMOS fabrication processes

Still a concern for analog/mixed signal & I/O circuits

Studies: COTS ADCs useless after 5-60 krads

TID Radiation Effects

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ADC BIST Operation and Block Diagram

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Operation Principle

• Radiation hardened 12-bit counter and

12-bit delta sigma ADC create a highly

linear voltage ramp that is the test input

for the ADC during the calibration cycle

• Digital Averager circuit calculates the

average of 64 -128 output words of the

ADC that operates at the nominal clock

speed

• The averaged value is then stored onto

an on-chip or external rad-hard memory.

• The data in the memory is parallel-to-

serial converted and read out using

JTAG bus



Averager Block Diagram

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Averager computes the

arithmetic average of

64-128 consequent

ADC conversion results

Stores average into an

on-chip 4 kilobyte

radiation-hardened

SRAM memory



Tested ADC

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Sub-ranging, 2-step, analog-to-digital converter.

Flash-type ADC



Simulation with TID Models

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Simulation with TID models show

that the ADC output is severely

distorted by missing codes after

500 krads of TID stress.

The codes stored in the SRAM during

the BIST cycle show exactly the same

distortion effects as observed in the

output of the ADC (Fig. 3), proving the

functionality of the BIST system.



Ridgetop Group Overview

• Arizona-based firm, founded in 2000, with focus on

products and design services for critical applications

• Two divisions: Semiconductor & Precision

Instruments (SPI) and Advanced Diagnostics &

Prognostics (ADP)

• Technology leader in high accuracy ADCs for harsh

environment applications

• Wide range of commercial and government

customers, including NASA, DOE, and DoD Agencies.

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• Worldwide nanotechnology R&D

partners in industry and academia

• Foundation and focus in physics-of-

failure for complex electronic systems

3580 West Ina Road,| Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

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Summary

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• The BIST circuit can be used to monitor TID-induced

performance degradation effects in ADCs, such as

missing codes, increased DNL and INL, and increased

gain error and offset error.

• Functionality of the designed BIST circuits and the

effectiveness of the system in monitoring TID effects in a

commercial ADC were verified through rigorous electrical

and radiation effect simulations in SPICE and VHDL-AMS.



Questions

Thank You!

[email protected]

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RASEDA 2012 - ADC BIST - Ridgetop Group.pdf

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