Radeon R700 - Rochester Institute of Technologymeseec.ce.rit.edu/551-projects/winter2011/3-2.pdf ·...
Transcript of Radeon R700 - Rochester Institute of Technologymeseec.ce.rit.edu/551-projects/winter2011/3-2.pdf ·...
Radeon R700
By: Jin Li & Sonny Adadi
Overview
• Background
• History• R500
• R600
• R700 Architecture
What is Radeon R700?
• Series of Graphic Processing Units(GPU) by Advanced Micro Devices(AMD)
• Released in 2008
• Foundation chip codenamed RV770
• Radeon HD 4000 series tier list:o Budget ‐ 4300s, 4500s
o Mid ‐ 4600s, 4700s
o Performance ‐ 4700s, 4800so Uber ‐ 4800 X2
What is a GPU?
• A processor optimized for 2D/3D graphics
• Highly parallel, multicored, multithreaded
Input Stage
Vertex-Shader
Geometry-Shader
Setup/Rasterizer Stage
Pixel-Shader
Output
Type of Shaders
•Pixel shader o Compute color and other attributes of each pixel.
•Vertex shaders o The main purpose of this shader is to convert 3D position in virtual space to 2D coordinate that appear on the screen (including the depth value Z‐buffer).
•Geometry shaderso Generates different kinds of graphic primitives such as points, lines and triangles.
o Executed after the vertex shaders. Take vertices as input
Vertex processing flow
Vertex Shader EngineTriangle mesh
Position,coordinate, etc
Pre-Vertex Data
Vertex Shader Instruction
Position “ texture”coordinate
color
Pixel processing flow
Pixel Shader Engine
Texture Light color , shadow etc
Texture coordinate color
Color , Multi‐render target
Pixel Shader Instruction
History Lesson - R520
• Radeon X1000 series
• Released 2005‐2006
• Focus on efficiency
• Architectural improvements:o Ultra‐Threaded Dispatch Processor
o Ring Bus Memory Controller
R520 - Architecture
Input Stage
Vertex-Shader
Geometry-Shader Setup Stage
Pixel-Shader
Output
R520 - Memory• Ring Bus
• Two internal 256‐bit rings
• Eight 32‐bit external channels(256‐bit link)
• Reduces routing complexity
• Permits higher clock speeds
History Lesson - R600
• Radeon HD 2000 & 3000 series
• Released 2006‐2007
• Architectural improvements:o Unified Shader Architectureo Superscalar Very‐Large‐Instruction‐Word(VLIW)o Improved Ring Bus
Unified Shader Architecture
R600 - ArchitectureInput Stage
Vertex/Geometry/Pixel-Shaders
Setup Stage
Output
R600 - Memory• Improved Ring Bus
• Internal 512‐bits in both directions
• Eight 64‐bit channels(512‐bit link)
• Fully distributed memory controller
Back to R700
• Same unified shader architecture... Just more of it
• Different memory subsystemo Ring bus replaced with something elseo Support GDDR5
R700 - Architecture
Input Stage
Vertex/Geometry/Pixel-Shaders
Setup Stage
Output
R700 Memory Controller• Ring bus gone!!!
• Switched hub architecture
• Reduced latency
• Reduced power
Specification ComparisonGPU HD4870 HD3870 X1950
GPU Frequency 750 MHz 775 MHz 650 MHz
Memory Frequency
900 MHz 1125 MHz 2000 MHz
Memory Type GDDR5 GDDR4 GDDR3
Memory Bandwidth
115.2 GB/s 72.0 GB/s 64.0 GB/s
Number of transistors
956 million 665 million 384 million
Process Technology
55 nm 55 nm 90 nm
SIMD Engines 10 4 Separate Processor
SIMD Engine - R700
•10 SIMD Engines
•One SIMD Engine oSet of "Steam Cores"
o16 KB local data cache
•Stream cores oFive way Very Long Instruction Word (VLIW) processor
Stream Core - R700Base on VLIW (Very Long Instruction Word) five‐way superscalar architecture
Total 160 VLIW five‐way superscalar shader processor
10 SIMD x 16 Shader Processor x 5 Stream processing unit
Result : 800 Stream Processor
Compare previous generation‐ 4 SIMD
4 SIMD x 16 Shader Processor x 5
Result : 320 Stream Processor
800/320 = 2.5 times
R700 Shader Processor
Stream Processing Unit5 Scalar Units• Four small unit
• Integer Add• Floating MAD • Floating point multiply• Floating point add• Dot product
• Fifth unit• Can handle transcendental instructions
• IEEE 32‐bit floating point precisionBranch Execution Unit• Responsible for flow control instructions
Questions?