Quartus Tutorial 4 – HDL

Copyright © 2010 by Gregory L. Moss 1

Quartus Tutorial 4 – HDL A step-by-step tutorial using Quartus II v9.x

by Gregory L. Moss

This tutorial presents two different circuit design examples using AHDL and VHDL hardware description languages. It is assumed that you have already reviewed Tutorials 1 and 2 and have some experience with using Quartus. The solutions selected for this tutorial illustrate several language techniques that can be used to describe combinational circuit hardware. These HDL solutions are described in detail in the Lab Manual along with several other alternate solutions. You may choose to compile any of the Lab Manual HDL solutions for these tutorials. You should review both tutorial examples because they each describe some additional Quartus simulation procedures.

HDL tutorial:

Example 6-1* Magnitude Comparator page 2

Example 6-2* Code Converter page 13

*These examples are from Unit 6A – Combinational Circuit Design with AHDL and Unit 6V – Combinational Circuit Design with VHDL in the Digital Systems Lab Manual: A Design Approach, 11th edition by Gregory L. Moss

Quartus II HDL Tutorial


Design a comparator circuit to compare the magnitudes of two 2-bit numbers (A1 A0 and B1 B0). The circuit will have three output signals: GT, LT, and EQ. GT will be high to indicate that the 2-bit A value is greater than the 2-bit B value. LT will be high if the 2-bit A value is less than the 2-bit B value. EQ will be high if the two 2-bit values are equal. The desired 3-output function is defined in a truth table shown in Table 6-1.

Example 6-1 Tutorial

A1 A0 B1 B0 GT LT EQ 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 1

Table 6-1 Truth table for example 6-1

Several different design solutions, written in AHDL and VHDL, are given in the Lab Manual. Each design solution will produce the same desired output function.

1. “Open New Project Wizard.” A new project folder (directory) will be created for each project. Enter the working directory and name for this project. The name for the project will be the same as the design filename twobit_compare. There are no additional files to add. Specify Family & Device. There are no additional tools to use. Check the New Project Wizard Summary and click the Finish button.

Start a New Design Project



2. Open the “Create Design” task folder in the Tasks Pane and double-click “Create New Design File” to open the New file dialog box. Select either “AHDL File” or “VHDL File” (the choice depends on the language used in your course) under “Design Files” & click OK.

Create a Text Design File

3. Select the appropriate AHDL or VHDL design file solution given on the next page. Use the Quartus Text Editor to create the text file for this design. Carefully type the given text. This design entry file will have the filename twobit_compare. Save the file in the project’s folder when finished. The file extension will depend upon the HDL language that is being used in your course. An AHDL design file will have the file extension .tdf. A VHDL design file will have the file extension .vhd.



AHDL

VHDL



4. Double-click the “Analysis & Synthesis” sub-task. If successful, click OK and continue. If you have errors make the necessary corrections to the design file and run Analysis again.

Analysis & Synthesis

5. Create a Vector Waveform File to verify the correct operation of this design by double-clicking “Create New Design File” in the Task Pane. Select “Vector Waveform File” listed under “Verification/Debugging Files” in the New dialog box and click OK.

Simulate the Project

6. Specify an end time (use 160 ms) for the simulation file. Open the Edit menu and choose “End Time.” Enter time value/units and click OK. Specify a grid size (use 10 ms) for the simulation file. Open the Edit menu again and choose “Grid Size.” Enter time value/units and click OK. “Fit in Window” (View menu). Save file.

7. Select inputs and outputs for the project simulation. Open the Edit menu, choose “Insert,” and then select “Insert Node or Bus” in the submenu (or double-click in the “Name” field of the Waveform editor). The Insert Node or Bus dialog box will open. Specify the Radix as Binary in the drop-down box. Click the Node Finder button.



8. Click the List button in the Node Finder window. Select the desired input group and output node Names shown below (hold down the CTRL key while clicking the left mouse button on the node name). Select nodes for the Vector Waveform File by clicking the > button. Click OK to close the Node Finder window and return to the Insert Node or Bus dialog box. Then click OK on the Insert Node or Bus dialog box to return to the Waveform Editor window with the selected circuit nodes.



9. Create the desired input waveforms for the project simulation. Select the time from 40ms to 80ms on input group a by holding down the left mouse button and dragging the cursor through that time on the grid. Release the mouse button and the specified time should be highlighted. Click the Arbitrary Value button in the Waveform Editor’s toolbar at the left side of the window. Enter the binary value 01 in the dialog box and click OK. The group input value for a will be changed in the timing diagram.

Arbitrary Value button



10. Next select the time from 80ms to 120ms on group input a. Click the Arbitrary Value button in the Waveform Editor’s toolbar and change the binary group value to 10. Click OK.



11. Finally select the last time segment for group input a (120ms to 160ms). Change the binary group value to 11.



12. Select the entire waveform for group input b by clicking the left mouse button on the node name. Click the Count Value button in the Waveform Editor’s toolbar. The Count Value dialog box will open and should look like the one below. This will produce a repeating count sequence from 00 to 11 in binary. Click OK.

Count Value button



13. The group input value for b will change in the timing diagram to give a repeating count pattern from 00 to 11. Notice that the result is a set of input vectors for group inputs a and b that cover all 16 possible combinations for the 4 input bits.

14. Clicking a Group Expand button in the Name field will display the individual signals for the selected group. The individual signals can be turned off again by clicking the Group Collapse button . Save the file as twobit_compare.vwf.

15. Perform a functional simulation on the project to determine if our design is correct. Open “Verify Design” and then “Simulate Design” tasks, double-click “Edit Settings” in the Tasks Pane. In the “Simulator Settings” dialog, open the drop down menu for “Simulation Mode” and select “Functional.” Click OK.

16. Start the simulator by double-clicking “Quartus II Simulator (Functional)” in the Tasks Pane. Click OK when the “Simulator was successful” message appears. Verify correct operation for this project.



17. To make manual pin assignments, open the “Assign Constraints” task folder in the Tasks Pane and double-click the “Edit Pin Assignments (Open Pin Planner)” Task. The input and output nodes for this logic circuit are listed in the table at the bottom of the Pin Planner window.

Manually Assign Pin Numbers

18. In the Pin Planner window, double-click the Location field for one of the circuit nodes. Type the desired pin number in the Location field (or scroll through the drop-down list of pin assignment choices until you come to the desired pin number and click the mouse button while pointing to that number). Then press Enter. Continue assigning appropriate pins for all inputs and outputs. The pin choices are dependent upon the specific FPGA/CPLD device and IC package that was assigned as a target device so it is critical that you have specified the correct device for compilation.

19. Double-click the “Compile Design” task (or click the “Start Compilation” button on the toolbar). The current project listed in the banner at the top of the screen will be compiled. If the compilation was successful, click OK and continue. If you have errors, locate the first error in the design file (double-click message or open the menu by pointing the cursor at the message and clicking the right mouse button, choose “Locate” and then “Locate in Design File”). The error will be highlighted in the design file and the message will describe what is wrong. Make the necessary corrections to the design file and compile again.

Compile the Project

20. Attach the FPGA/CPLD development board to the PC using the appropriate interface cable (USB-Blaster or ByteBlaster). Be sure to follow any special instructions for your specific FPGA/CPLD development board.

Program a PLD

21. Open the Programmer window by double-clicking “Program Device” in the Tasks Pane (or clicking the Programmer button on the toolbar). The programmer window should identify the correct type of hardware interface (USB-Blaster or ByteBlaster).

22. Turn on the power to the board & click the Start button in the Programmer window. When the Progress bar shows 100%, the programming is complete and the FPGA/CPLD is ready for testing. Connect lights and switches, if they are not pre-wired.

23. Test your circuit by applying all input combinations using the logic switches and monitor the resulting output on the lights. Does the circuit function correctly? If it does, demo your project to your lab instructor. Create a truth table to record your test results.


Design and construct a 2421-BCD-to-5421-BCD code converter. The truth table for this design is given below. The inputs are labeled d c b a and the outputs are labeled p q r s. Note that in this situation, we care about only 10 of the 16 possible input combinations. The other 6 input combinations are listed at the bottom of the truth table and are labeled as “invalid.” Each of the invalid input conditions should be given a default output value of 1111.

Example 6-2 Tutorial

Decimal 2 4 2 1 5 4 2 1 ← weights Value d c b a p q r s ← bit names

0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 0 0 0 1 0 3 0 0 1 1 0 0 1 1 4 0 1 0 0 0 1 0 0 5 1 0 1 1 1 0 0 0 6 1 1 0 0 1 0 0 1 7 1 1 0 1 1 0 1 0 8 1 1 1 0 1 0 1 1 9 1 1 1 1 1 1 0 0

invalid 0 1 0 1 1 1 1 1 invalid 0 1 1 0 1 1 1 1 invalid 0 1 1 1 1 1 1 1 invalid 1 0 0 0 1 1 1 1 invalid 1 0 0 1 1 1 1 1 invalid 1 0 1 0 1 1 1 1

Table 6-2 Truth table for example 6-2

1. “Open New Project Wizard.” A new project folder (directory) will be created for each project. Enter the working directory and name for this project. The name for the project will be the same as the design filename code_conv. There are no additional files to add. Specify Family & Device. There are no additional tools to use. Check the New Project Wizard Summary and click Finish.

Start a New Design Project



2. “Create New Design File” (“Create Design” task folder). Select “AHDL File” or “VHDL File” as appropriate for your course.

Create a Text Design File

3. Type an HDL design file solution for Example 6-2 (AHDL version is given below and the VHDL version is on the next page) using the Quartus Text Editor. Save the code_conv.tdf or code_conv.vhd file in the project’s folder.

AHDL



VHDL

4. Run “Analysis & Synthesis” sub-task. If successful, click OK and continue.

Analysis & Synthesis



5. “Create New Design File.” Select “Vector Waveform File.”

Simulate the Project

6. Enter 16.0μs for the End Time (Edit menu). Enter 1μs for the Grid Size (Edit menu). Fit in Window (View menu).

7. Select all inputs and outputs for the project simulation. Edit menu → Insert → Insert Node or Bus → Radix: Binary → Node Finder → List nodes → Select all signals Return to the Waveform Editor window with the selected circuit nodes.



8. Re-arrange the order of the input nodes so that the MSB is on top and the LSB is on the bottom of the list. Select the input node a by clicking & releasing the left mouse button while pointing the cursor at its “handle.” Again point the cursor at the “handle” for node a, press and hold the left mouse button while moving the cursor to the new location at the bottom of the input node list, and release the mouse button. Repeat for the other input nodes to obtain the order shown below. The output nodes (p q r s) are already in the correct order of MSB on the top and the LSB on the bottom.

↑ node handles 9. Select all of the circuit inputs by pointing the cursor at the top input node “handle” and

holding the left mouse button down while dragging the cursor through the last input “handle.”



10. Point the cursor at the selected node names and click the right mouse button to open the menu. Select “Grouping” and then choose “Group.” Enter the Group name “codein” in the dialog box and click OK. Repeat to create the Group name “codeout” for the output nodes.



11. Clicking a Group Expand button in the Name field will display the individual node signals for the selected group. The individual signals can be turned off again by clicking the Group Collapse button . Expand only the codeout group. Save the file as code_conv.vwf.



12. Create test vectors to verify all 16 possible input combinations for this project. Select the entire waveform for signal group codein. Click Count Value button to count from 0000 to 1111 in Binary. OK. Save the code_conv.vwf file.

Count Value button



13. Select Functional simulation. Verify Design → Simulate Design → Edit Settings Select “Functional” Simulation Mode → OK

14. Run “Quartus II Simulator (Functional)” task. Verify correct operation.



15. Change the radix for both signal groups in the simulation waveform. → Select both waveforms (Drag cursor through both node handles while pressing left mouse button) → Open menu with right-click of mouse while pointing to the highlighted area → Choose Properties → Change Radix to Hexadecimal in the drop-down list



16. “Edit Pin Assignments (Open Pin Planner)” Task (“Assign Constraints” task folder) Double-click the Location field for one of the circuit nodes. Type in the desired pin number & press Enter. Re-compile the design.

Manually Assign Pin Numbers

17. Start Compilation. If necessary, correct any syntax errors and re-compile.

Compile the Project

18. Attach the FPGA/CPLD development board to the PC.

Program a PLD

19. Program FPGA/CPLD. “Program Device” in the Tasks Pane. Check for correct Hardware interface. Turn on the power to the board. Click Start button.

20. When programming is complete, the FPGA/CPLD is ready for testing. Connect lights and switches, if they are not pre-wired. Test your circuit by applying all input combinations using the logic switches and monitor the resulting output on the lights. Does the circuit function correctly? If it does, demo your project to your lab instructor. Create a truth table to record your test results.

Quartus Tutorial 4 – HDL

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