QTouch 7-channel Sensor IC · LP mode controls the intervals between acquisition measurements....

QTouch 7-channel Sensor IC

AT42QT1070

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Features• Configurations:

– Comms mode– Standalone mode

• Number of Keys:– Comms mode – 1 to 7 keys (or 1 to 6 keys plus a Guard Channel)– Standalone mode – 1 to 4 keys plus a fixed Guard Channel on key 0

• Number of I/O Lines: – Standalone mode – 5 outputs

• Technology:– Patented spread-spectrum charge-transfer

• Key Outline Sizes:– 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and

shapes possible• Layers Required:

– One• Electrode Materials:

– Etched copper– Silver– Carbon– Indium Tin Oxide (ITO)

• Panel Materials: – Plastic– Glass– Composites– Painted surfaces (low particle density metallic paints possible

• Panel Thickness:– Up to 10 mm glass (electrode size dependent)– Up to 5 mm plastic (electrode size dependent)

• Key Sensitivity:– Comms mode – individually settable via simple commands over I2C-compatible

interface– Standalone mode – settings are fixed

• Interface:– I2C-compatible slave mode (400 kHz). Discrete detection outputs

• Power: – 1.8V to 5.5V

• Package: – 14-pin SOIC RoHS compliant IC– 20-pin VQFN RoHS compliant IC

• Signal Processing: – Self-calibration– Auto drift compensation– Noise filtering– Adjacent Key Suppression® (AKS® – up to three groups possible)

1. Pinouts and Schematics

1.1 Pinout Configuration – Comms Mode (14-pin SOIC)

1.2 Pinout Configuration – Standalone Mode (14-pin SOIC)

Vdd

MODE (Vss)

RESET

SDA

CHANGE

KEY2

KEY1

KEY0

1

2

3

4

5

6

7 8

9

10

11

12

13

14

QT1070

SCL

KEY6

KEY3

Vss

KEY5

KEY4

Vdd

MODE (Vdd)

RESET

OUT0

OUT4

KEY2

KEY1

KEY0

1

2

3

4

5

6

7 8

9

10

11

12

13

14

QT1070

OUT3

OUT2

KEY3

Vss

OUT1

KEY4

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1.3 Pinout Configuration – Comms Mode (20-pin VQFN)

1.4 Pinout Configuration – Standalone Mode (20-pin VQFN)

N/C

N/C

Vss

Vd

d

N/C

KEY4

KEY3

KEY2

KEY1

KEY0 MODE (Vss)

SDA

1

2

3

4

5 11

12

13

14

1520 19 18 17 16

6 7 8 109

QT1070 RESET

CHANGE

SCL

KE

Y6

KE

Y5

N/C

N/C

N/C

N/C

N/C

Vss

Vdd

N/C

KEY4

KEY3

KEY2

KEY1

KEY0 MODE (Vdd)

OUT0

1

2

3

4

5 11

12

13

14

1520 19 18 17 16

6 7 8 109

QT1070 RESET

OUT4

OUT3

OU

T2

OU

T1

N/C

N/C

N/C

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1.5 Pin Descriptions

Table 1-1. Pin Listings (14-pin SOIC)

PinName

(CommsMode)

Name(Standalone

Mode) Type DescriptionIf Unused, Connect To...

1 Vdd Vdd P Power –

2 MODE (Vss) MODE (Vdd) I

Mode selection pin

Comms Mode – connect to Vss

Standalone Mode – connect to Vdd

–

3 SDA OUT0 ODComms Mode – I2C-compatible data line

Standalone Mode – open drain output for guard channel

Open

4 RESET RESET I RESET – has internal pull-up 60 k resistor Open

5 CHANGE OUT4 OD

CHANGE line for controlling the communications flow

Comms Mode – connect to CHANGE lineStandalone Mode – connect to output

Open

6 SCL OUT3 ODComms Mode – connect to I2C-compatible clockStandalone Mode – connect to output

Open

7 KEY6 OUT2 O/ODComms Mode – connect to Key 6 Standalone Mode – connect to output

Open


Open

9 KEY4 KEY4 O Key 4 Open





14 Vss Vss P Ground –

I Input only

O Output only, push-pull

OD Open drain output

P Ground or power

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Table 1-2. Pin Listings (20-pin VQFN)

PinName

(CommsMode)

Name(Standalone

Mode) Type DescriptionIf Unused, Connect To...






6 N/C N/C – Not connected –


8 Vss Vss P Ground –

9 Vdd Vdd P Power –


11 MODE (Vss) MODE (Vdd) I

Mode selection pin

Comms Mode – connect to Vss

Standalone Mode – connect to Vdd

–

12 SDA OUT0 ODComms Mode – I2C-compatible data line

Standalone Mode – open drain output for guard channel

Open

13 RESET RESET I RESET – has internal pull-up 60 k resistor Open

14 CHANGE OUT4 OD

CHANGE line for controlling the communications flow

Comms Mode – connect to CHANGE lineStandalone Mode – connects to output

Open

15 SCL OUT3 ODComms Mode – connect to I2C-compatible clockStandalone Mode – connect to output

Open


Open


Open




I Input only

O Output only, push-pull

OD Open drain output

P Ground or power

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1.6 Schematics

Figure 1-1. Typical Circuit – Comms (14-pin SOIC)

Figure 1-2. Typical Circuit – Standalone (14-pin SOIC)

Rs6

C1

K4

RSCL

Rs5

Rs4

Rs3

Rs2

Rs1

K3

K2

K1

1

QT1070

MODE (Vss)

2

SDA3

RESET4

CHANGE5

SCL6

KEY67

KEY58

KEY49

KEY310

KEY211

KEY112

KEY013

14

Vss

Rs0 K0

Vss

Vdd

CHANGE

SDA

RESET

K5

K6

Vdd

SCL

Vdd

Vss

RSDA

Vdd

RCHG RRST

ROUT2

C1

K4

ROUT3

ROUT1

Rs4

Rs3

Rs2

Rs1

K3

K2

K1

1

OUT03

RESET4

OUT45

6

OUT2 7

OUT1 8

KEY4 9

KEY3 10

KEY2 11

KEY1 12

KEY0 13

Vss

Rs0 K0

Vss

ROUT4

Vdd

RESET

COUT1

COUT2

COUT3

Vss

COUT4

COUT0

14

Vss

QT1070

Vdd

Vss

OUTPUTSOUTPUTS

ROUT0

MODE (Vdd)

2

C and are optionalOUT1, 2 3

C and are optionalOUT0 4

R1

Vdd

OUT3

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Figure 1-3. Typical Circuit – Comms (20-pin VQFN)

Figure 1-4. Typical Circuit – Standalone (20-pin VQFN)

Rs6

C1

K4

Rs5

Rs4

Rs3

Rs2

Rs1

K3

K2

K1

9

QT1070

SCL 15

SDA12

RESET13

CHANGE14KEY6 16

KEY5 17

KEY4 1

KEY3 2

KEY2 3

KEY1 4

KEY0 5

8

Vss

Rs0 K0

Vss

Vdd

K5

K6

RSCL

VddVdd

Vss

11

MODE (Vss)

N/C

N/C18

N/C19

N/C20

N/C7

N/C6

10

CHANGE

SDA

RESET

RSDA

Vdd

RCHG RRST

1) The central pad on the underside of the chip is a Vss pinand should be connected to ground. Do not put any othertracks underneath the body of the chip.

2) It is important to place all Rs components physically nearto the chip.

RsOUT2

K4

RsOUT3

RLOUT1

Rs4

Rs3

Rs2

Rs1

K3

K2

K1

OUT012

RESET13

OUT414

OUT3 15

OUT2 16

OUT1 17

KEY4 1

KEY3 2

KEY2 3

KEY1

KEY0 5

Vss

Rs0 K0

ROUT4

RESET

COUT1

COUT2

COUT3

Vss

COUT4

COUT0

8

QT1070

Vss

OUTPUTSOUTPUTS

N/C

N/C18

N/C19

N/C20

N/C7

N/C6

10

4

ROUT0

Vss

C1

9 Vss

Vdd

VddMODE (Vdd)

11

C and are optionalOUT1 2 3,

C and are optionalOUT0 4

R1

Vdd

1) The central pad on the underside of the chip is a Vss pinand should be connected to ground. Do not put any othertracks underneath the body of the chip.

2) It is important to place all Rs components physically nearto the chip.

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Re Figure 1-1, 1-2, 1-3 and 1-4, check the following sections for component values:

• Section 3.1 on page 13: Series resistors (Rs0 – Rs6 for comms mode and Rs0 – Rs4 forstandalone mode)

• Section 3.2 on page 13: LED traces

• Section 3.4 on page 14: Power Supply (voltage levels)

• Section 4.4 on page 17: SDA, SCL pull-up resistors

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AT42QT1070

AT42QT1070

2. Overview

2.1 IntroductionThe AT42QT1070 (QT1070) is a digital burst mode charge-transfer (QT™) capacitive sensordriver. The device can sense from one to seven keys, dependent on mode.

The QT1070 includes all signal processing functions necessary to provide stable sensing undera wide variety of changing conditions, and the outputs are fully debounced. Only a few externalparts are required for operation and no external Cs capacitors are required.

The QT1070 modulates its bursts in a spread-spectrum fashion in order to heavily suppress theeffects of external noise, and to suppress RF emissions. The QT1070 use a dual-pulse methodof acquisition. This provides greater noise immunity and eliminates the need for externalsampling capacitors, allowing touch sensing using a single pin.

2.2 Modes

2.2.1 Comms ModeThe QT1070 can operate in comms mode where a host can communicate with the device via anI2C-compatible bus. This allows the user to configure settings for Threshold, Adjacent KeySuppression® (AKS®), Detect Integrator, Low Power (LP) Mode, Guard Channel and Max TimeOn for keys.

2.2.2 Standalone ModeThe QT1070 can operate in a standalone mode where an I2C-compatible interface is notrequired. To enter standalone mode, connect the Mode pin to Vdd before powering up theQT1070.

In standalone mode, the start-up values are hard coded in firmware and cannot be changed.The default start-up values are used. This means that key detection is reported via theirrespective IOs. The Guard channel feature is automatically implemented on key 0 in standalonemode. This means that this channel gets priority over all other keys going into touch.

2.3 KeysDependent on mode, the QT1070 can have a minimum of one key and a maximum of sevenkeys. These can be constructed in different shapes and sizes. See “Features” on page 1 for therecommended dimensions.

• Comms mode – 1 to 7 keys (or 1 to 6 keys plus Guard Channel)

• Standalone mode – 1 to 4 keys plus a Guard Channel

Unused keys should be disabled by setting the averaging factor to zero (see Section 5.9 onpage 21).

The status register can be read to determine the touch status of the corresponding key. It isrecommended using the open-drain CHANGE line to detect when a change of status hasoccurred.

2.4 Input/Output (IO) Lines There are no IO lines in comms mode.

In Standalone mode pins OUT0 – OUT4 can be used as open drain outputs for driving LEDs.

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2.5 Acquisition/Low Power Mode (LP)There are 255 different acquisition times possible. These are controlled via the LP mode byte(see Section 5.11 on page 22) which can be written to via I2C-compatible communication.

LP mode controls the intervals between acquisition measurements. Longer intervals consumelower power but have an increased response time. During calibration, touch and during thedetect integrator (DI) period, the LP mode is temporarily set to LP mode 1 for a faster response.

The QT1070 operation is based on a fixed cycle time of approximately 8 ms. The LP modesetting indicates how many of these periods exist per measurement cycle. For example, If LPmode = 1, there is an acquisition every cycle (8 ms). If LP mode = 3, there is an acquisitionevery 3 cycles (24 ms). If a high Averaging Factor (see Section 5.9 on page 21) setting isselected then the acquisition time may exceed 8 ms.

LP settings above mode 32 (256 ms) result in slower thermal drift compensation and should beavoided in applications where fast thermal transients occur.

2.6 Adjacent Key Suppression (AKS) TechnologyThe device includes Atmel’s patented Adjacent Key Suppression (AKS) technology, to allow theuse of tightly spaced keys on a keypad with no loss of selectability by the user.

There can be up to three AKS groups, implemented so that only one key in the group may bereported as being touched at any one time. Once a key in a particular AKS group is in detect noother key in that group can go into detect. Only when the key in detect goes out of detection cananother key go into detect state.

The keys which are members of the AKS groups can be set (see Section 5.9 on page 21). Keysoutside the group may be in detect simultaneously.

2.7 CHANGE Line (Comms Mode Only)The CHANGE line is active low and signals when there is a change in state in the Detection orInput status bytes. It is cleared (allowed to float high) when the host reads the status bytes.

If the status bytes change back to their original state before the host has read the status bytes(for example, a touch followed by a release), the CHANGE line will be held low. In this case, aread to any memory location will clear the CHANGE line.

The CHANGE line is open-drain and should be connected via a 47 k resistor to Vdd. It isnecessary for minimum power operation as it ensures that the QT1070 can sleep for as long aspossible. Communications wake up the QT1070 from sleep causing a higher powerconsumption if the part is randomly polled.

Note: The CHANGE line is pulled low 100 ms after power-up or reset.

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AT42QT1070

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2.8 Proximity SensingThe QT1070 is capable of detecting near-proximity or touch. By increasing the sensitivity, theQT1070 can be used as a very effective proximity sensor, allowing the presence of a nearbyobject to be detected.

As the object being sensed is typically a hand, very large electrode sizes can be used (seeSection 2.12.3 on page 12 for Cx limitations), which is extremely effective in increasing thesensitivity of the detector. Note that, although this affects the responsiveness of the sensor, it isless of an issue in proximity sensing applications; in such applications it is only necessary todetect the presence of a large object, rather than a small, precise touch.

Proximity sensing technology enables users to interact with consumer electronics without eventouching them. With this powerful technology, sensors in a device such as a PC notebook, PCperipheral, or digital photo frame, sense the presence of a user’s hand and take action. Thesesensors can illuminate LEDs for discoverable buttons, wake devices from power-saving modeimmediately, or activate other functionality.

Refer to “Associated Documents” on page 37 for information about design guidelines.

2.9 Types of Reset

2.9.1 External ResetAn external reset logic line can be used if desired, fed into the RESET pin. However, under mostconditions it is acceptable to tie RESET to Vdd.

2.9.2 Soft ResetThe host can cause a device reset by writing a nonzero value to the RESET byte. This soft resettriggers the internal watchdog timer on a 125 ms interval. After 125 ms the device resets andwakes again.

The device NACKs any attempts to communicate with it during the first 30 ms of its initializationperiod.

2.10 CalibrationWriting a nonzero value to the calibration byte can force a recalibration at any time. This can beuseful to clear out a stuck key condition after a prolonged period of uninterrupted detection.

Note: A calibrate command clears all key status bits and the overflow bit (until it is checked on the next cycle).

2.11 Guard Channel A guard channel to help prevent false detection is available in both modes. This is fixed on key 0for standalone mode and programmable for comms mode.

Guard channel keys should be more sensitive than the other keys (physically bigger). Becausethe guard channel key is physically bigger it becomes more susceptible to noise so it has ahigher Averaging Factor (see Section 5.9 on page 21) and a lower Threshold (see Section 5.8on page 21) than the other keys. In standalone mode it should have an Averaging Factor of 16and a Threshold of 10 counts.

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A channel set as the guard channel (there can only be one) is prioritised when the filtering ofkeys going into detect is taking place. So if a normal key is filtering into touch (touch present butDI has not been reached) and the key set as the guard key begins filtering in, then the normalkey’s filter is reset and the guard key filters in first.

The guard channel is connected to a sensor pad which detects the presence of touch andoverrides any output from the other keys.

Figure 2-1. Guard Channel Example

2.12 Signal Processing

2.12.1 Detect ThresholdThe device detects a touch when the signal has crossed a threshold level and remained therefor a specified number of counts (see Section 5.10 on page 21). This can be altered on akey-by-key basis using the key threshold I2C-compatible commands.

In standalone mode the detect threshold is set to a fixed value of 10 counts of change withrespect to the internal reference level for the guard channel and 20 counts for the other fourkeys. The reference level has the ability to adjust itself slowly in accordance with the driftcompensation mechanism.

The drift mechanism will drift toward touch at a rate of 160 ms x 18 = 2.88 seconds and awayfrom touch at a rate of 160 ms x 6 = 0.96 seconds. The 160 ms is based on 20 x 8 ms cycles. Ifthe cycle time exceeds 8 ms then the overall times will be extended to match.

2.12.2 Detect IntegratorThe device features a fast detection integrator counter (DI filter), which acts to filter out noise atthe small expense of a slower response time. The DI filter requires a programmable number ofconsecutive samples confirmed in detection before the key is declared to be touched. Theminimum number for the DI filter is 2. Settings of 0 and 1 for the DI also default to 2. The DI isalso implemented when a touch is removed.

2.12.3 Cx LimitationsThe recommended range for key capacitance Cx is 1 pF – 30 pF. Larger values of Cx will givereduced sensitivity.

Guard channel

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2.12.4 Max On DurationIf an object or material obstructs the sense pad the signal may rise enough to create a detection,preventing further operation. To prevent this, the sensor includes a timer which monitorsdetections. If a detection exceeds the timer setting the sensor performs a key recalibration. Thisis known as the Max On duration feature and is set to approximately 30s in standalone mode.

In comms mode this feature can be changed by setting a value in the range 1 – 255(160 ms – 40800 ms) in steps of 160 ms. A setting of 0 disables the Max On Durationrecalibration feature.

Note: If bit 4 of address 53 is clear then a recalibration of all keys occurs on Max On Duration instead of the individual key recalibration.

2.12.5 Positive RecalibrationIf a keys signal jumps in the negative direction (with respect to its reference) by more than thePositive Recalibration setting (4 counts), then a recalibration of that key takes place.

2.12.6 Drift Hold TimeDrift Hold Time (DHT) is used to restrict drift on all keys while one or more keys are activated.DHT restricts the drifting on all keys until approximately four seconds after all touches have beenremoved.

This feature is particularly useful in cases of high-density keypads where touching a key orhovering a finger over the keypad would cause untouched keys to drift, and therefore create asensitivity shift, and ultimately inhibit touch detection.

2.12.7 HysteresisHysteresis is fixed at 12.5 percent of the Detect Threshold. When a key enters a detect stateonce the DI count has been reached, the NTHR value is changed by a small amount(12.5 percent of NTHR) in the direction away from touch. This is done to affect hysteresis and somakes it less likely a key will dither in and out of detect. NTHR is restored once the key drops outof detect.

3. Wiring and Parts

3.1 Rs ResistorsSeries resistors Rs (Rs0 – Rs6 for comms mode and Rs0 – Rs4 for standalone mode) are in linewith the electrode connections and should be used to limit electrostatic discharge (ESD)currents and to suppress radio frequency interference (RFI). Series resistors are recommendedfor noise reduction. They should be approximately 4.7 kto 20 k each.

3.2 LED Traces and Other Switching SignalsDigital switching signals near the sense lines induce transients into the acquired signals,deteriorating the signal-to-noise (SNR) performance of the device. Such signals should berouted away from the sensing traces and electrodes, or the design should be such that theselines are not switched during the course of signal acquisition (bursts).

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LED terminals which are multiplexed or switched into a floating state, and which are within, orphysically very near, a key (even if on another nearby PCB) should be bypassed to either Vss orVdd with at least a 10 nF capacitor. This is to suppress capacitive coupling effects which caninduce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact itcan be quite distant. The bypass capacitor is noncritical and can be of any type.

LED terminals which are constantly connected to Vss or Vdd do not need further bypassing.

3.3 PCB CleanlinessModern no-clean flux is generally compatible with capacitive sensing circuits.

If a PCB is reworked in any way, clean it thoroughly to remove all traces of the flux residuearound the capacitive sensor components. Dry it thoroughly before any further testing isconducted.

3.4 Power SupplySee Section 6.2 on page 24 for the power supply range. If the power supply fluctuates slowlywith temperature, the device tracks and compensates for these changes automatically with onlyminor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensationmechanism is not able to keep up, causing sensitivity anomalies or false detections.

The usual power supply considerations with QT parts apply to the device. The power should beclean and come from a separate regulator if possible. However, this device is designed tominimize the effects of unstable power, and except in extreme conditions should not require aseparate Low Dropout (LDO) regulator.

It is assumed that a larger bypass capacitor (like 1 µF) is somewhere else in the power circuit;for example, near the regulator.

To assist with transient regulator stability problems, the QT1070 waits 500 µs any time it wakesup from a sleep state (in LP modes) before acquiring, to allow Vdd to fully stabilize.

CAUTION: If a PCB is reworked in any way, it is almost guaranteed that the behavior of the no-clean flux will change. This can mean that the flux changes from an inert material to one that can absorb moisture and dramatically affect capacitive measurements due to additional leakage currents. If so, the circuit can become erratic and exhibit poor environmental stability.

CAUTION: A regulator IC shared with other logic can result in erratic operation and isnot advised.

A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed veryclose to the power pins of the IC. Failure to do so can result in device oscillation,high current consumption and erratic operation.

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4. I2C-compatible Communications (Comms Mode Only)

4.1 I2C-compatible Protocol

4.1.1 ProtocolThe I2C-compatible protocol is based around access to an address table (see Table 5-1 onpage 18) and supports multibyte reads and writes. The maximum clock rate is 400 kHz.

See Section A on page 31 for an overview of I2C-compatible bus operation.

4.1.2 SignalsThe I2C-compatible interface requires two signals to operate:

• SDA - Serial Data

• SCL - Serial Clock

A third line, CHANGE, is used to signal when the device has seen a change in the status byte:

• CHANGE: Open-drain, active low when any capacitive key has changed state since the last I2C-compatible read. After reading the two status bytes, this pin floats (high) again if it is pulled up with an external resistor. If the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the CHANGE line is held low. In this case, a read to any memory location clears the CHANGE line.

4.2 I2C-compatible AddressThere is one preset I2C-compatible address of 0x1B. This is not changeable.

4.3 Data Read/Write

4.3.1 Writing Data to the DeviceThe sequence of events required to write data to the device is shown next.

1. The host initiates the transfer by sending the START condition

2. The host follows this by sending the slave address of the device together with the WRITE bit.

Table 4-1. Description of Write Data Bits

Key Description

S START condition

SLA+W Slave address plus write bit

A Acknowledge bit

MemAddress Target memory address within device

Data Data to be written

P Stop condition

SLA+W MemAddressA AS Data A P

Host to Device Device to Host

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3. The device sends an ACK.

4. The host then sends the memory address within the device it wishes to write to.

5. The device sends an ACK if the write address is in the range 0x00 – 0x7F, otherwise it sends a NACK.

6. The host transmits one or more data bytes; each is acknowledged by the device (unless trying to write to an invalid address).

7. If the host sends more than one data byte, they are written to consecutive memory addresses.

8. The device automatically increments the target memory address after writing each data byte.

9. After writing the last data byte, the host should send the STOP condition.

Note: the host should not try to write to addresses outside the range 0x20 to 0x39 because thisis the limit of the device’s internal memory address.

4.3.2 Reading Data From the DeviceThe sequence of events required to read data from the device is shown next.

1. The host initiates the transfer by sending the START condition

2. The host follows this by sending the slave address of the device together with the WRITE bit.

3. The device sends an ACK.

4. The host then sends the memory address within the device it wishes to read from.

5. The device sends an ACK if the address to be read from is less than 0x80 otherwise it sends a NACK).

6. The host must then send a STOP and a START condition followed by the slave address again but this time accompanied by the READ bit.

Note: Alternatively, instead of step 6 a repeated START can be sent so the host does not need to relinquish control of the bus.

7. The device returns an ACK, followed by a data byte.

8. The host must return either an ACK or NACK.

a. If the host returns an ACK, the device subsequently transmits the data byte from the next address. Each time a data byte is transmitted, the device automatically increments the internal address. The device continues to return data bytes until the host responds with a NACK.

b. If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition.

9. The device resets the internal address to the location indicated by the memory address sent to it previously. Therefore, there is no need to send the memory address again when reading from the same location.

Note: Reading the 16-bit reference and signal values is not an automatic operation; reading the first byte of a 16-bit value does not lock the other byte. As a result glitches in the reported value may be seen as values increase from 255 to 256, or decrease from 256 to 255.

SLA+W MemAddressA AS S SLA+R A

A P

Host to Device Device to Host

P

A /AData 1 Data 2 Data n

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4.4 SDA, SCLThe I2C-compatible bus transmits data and clock with SDA and SCL respectively. They areopen-drain; that is I2C-compatible master and slave devices can only drive these lines low orleave them open. The termination resistors pull the line up to Vdd if no I2C-compatible device ispulling it down.

The termination resistors commonly range from 1 k to 10 kand should be chosen so that therise times on SDA and SCL meet the I2C-compatible specifications (1 µs maximum).

Standalone mode: if I2C-compatible communications are not required, then standalone modecan be enabled by connecting the MODE pin to Vdd. See Section 2.4 on page 9 for moreinformation.

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5. Setups

5.1 IntroductionThe device calibrates and processes signals using a number of algorithms specifically designedto provide for high survivability in the face of adverse environmental challenges. User-definedSetups are employed to alter these algorithms to suit each application. These Setups are loadedinto the device over the I2C-compatible serial interfaces. In standalone these settings are fixed topredetermined values.

Table 5-1. Internal Register Address Allocation

Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

0 Chip ID Major ID (= 2) Minor ID (= E) R

1 Firmware Version Firmware version number R

2 Detection status CALIBRATE OVERFLOW – – – – – TOUCH R

3 Key status Reserved Key 6 Key 5 Key 4 Key 3 Key 2 Key 1 Key 0 R

4 – 5 Key signal 0 Key signal 0 (MSByte) – Key signal 0 (LSByte) R







18 – 19 Reference data 0 Reference data 0 (MSByte) – Reference data 0 (LSByte) R







32 NTHR key 0 Negative Threshold level for key 0 R/W







39 AVE/AKS key 0 Adjacent key suppression level for key 0 R/W




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5.2 Address 0: Chip ID

MAJOR ID: Reads back as 2

MINOR ID: Reads back as E

5.3 Address 1: Firmware Version

FIRMWARE VERSION: this shows the 8-bit firmware version 1.5 (0x15).




46 DI key 0 Detection integrator counter for key 0 R/W







53 FO/MO/Guard No FastOutDI/ Max Cal/Guard Channel R/W

54 LP Low Power (LP) Mode R/W

55 Max On Duration Maximum On Duration R/W

56 Calibrate Calibrate R/W

57 RESET RESET R/W

Table 5-2. Chip ID

Address b7 b6 b5 b4 b3 b2 b1 b0

0 MAJOR ID MINOR ID

Table 5-1. Internal Register Address Allocation (Continued)

Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

Table 5-3. Firmware Version


1 FIRMWARE VERSION

199596A–AT42–10/10

5.4 Address 2: Detection Status

CALIBRATE: This bit is set during a calibration sequence.

OVERFLOW: This bit is set if the time to acquire all key signals exceeds 8 ms.

TOUCH: This bit is set if any keys are in detect.

5.5 Address 3: Key Status

KEY0 – 6: bits 0 to 6 indicate which keys are in detection, if any. Touched keys report as 1,untouched or disabled keys report as 0.

5.6 Address 4 – 17: Key Signal

KEY SIGNAL: addresses 4 – 17 allow key signals to be read for each key, starting with key 0.There are two bytes of data for each key. These are the key’s 16-bit key signals which areaccessed as two 8-bit bytes, stored MSByte first. These addresses are read-only.

5.7 Address 18 – 31: Reference Data

REFERENCE DATA: addresses 18 – 31 allow reference data to be read for each key, startingwith key 0. There are two bytes of data for each key. These are the key’s 16-bit reference datawhich is accessed as two 8-bit bytes, stored MSByte first. These addresses are read-only.

Table 5-4. Detection Status


2 CALIBRATE OVERFLOW – – – – – TOUCH

Table 5-5. Key Status


3 Reserved KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0

Table 5-6. Key Signal


4 MSByte OF KEY SIGNAL FOR KEY 0

5 LSByte OF KEY SIGNAL FOR KEY 0

6 – 17 MSByte/LSByte OF KEY SIGNAL FOR KEYS 1 – 6

Table 5-7. Reference Data


18 MSByte OF REFERENCE DATA FOR KEY 0

19 LSByte OF REFERENCE DATA FOR KEY 0

20 – 31 MSByte/LSByte OF REFERENCE DATA FOR KEYS 1 – 6

209596A–AT42–10/10

AT42QT1070

AT42QT1070

5.8 Address 32 – 38: Negative Threshold (NTHR)

NTHR Keys 0 – 6: these 8-bit values set the threshold value for each key to register a detection.

Default: 20 counts

Note: Do not use a setting of 0 as this causes a key to go into detection when its signal is equal to its reference.

5.9 Address 39 – 45: Averaging Factor/Adjacent Key Suppression (AVE/AKS)

AVE 0 – 5: The Averaging Factor (AVE) is the number of pulses which are added together andaveraged to get the final signal value for that channel.

For example, if AVE = 8 then 8 ADC samples are taken and added together. The result isdivided by the original number of pulses (8). If sixteen pulses are used then the result is dividedby sixteen.

This provides a better signal-to-noise ratio but requires longer acquire times. Values for AVE arerestricted internally to 1, 2, 4, 8, 16 or 32.

Default: 8 (In standalone mode key 0 is 16)

AKS 0 – 1: these bits control which keys are included in an AKS group. There can be up to threegroups, each containing any number of keys (up to the maximum allowed for the mode).

Each key can have a value between 0 and 3, which assigns it to an AKS group of that number. Akey may only go into detect when it has the largest signal change of any key in its group. A valueof 0 means the key is not in any AKS group.

Default: 0x01

5.10 Address 46 – 52: Detection Integrator (DI)

DETECTION INTEGRATOR: addresses 46 – 52 allow the DI level to be set for each key. This8-bit value controls the number of consecutive measurements that must be confirmed as havingpassed the key threshold before that key is registered as being in detect. The minimum value forthe DI filter is 2. Settings of 0 and 1 for the DI also default to 2 because a minimum of twoconsecutive measurements must be confirmed.

Default: 4

Table 5-8. NTHR


32 – 38 NEGATIVE THRESHOLD FOR KEYS 0 – 6

Table 5-9. AVE/AKS


39 – 45 AVE5 AVE4 AVE3 AVE2 AVE1 AVE0 AKS1 AKS0

Table 5-10. Detection Integrator


46 – 52 DETECTION INTEGRATOR

219596A–AT42–10/10

5.11 Address 53: FastOutDI/Max Cal/Guard Channel

FO: Fast Out DI – when bit 5 is set then a key filters out with an integrator of 4. Could have a DIin of 100 but filter out with DI of 4 (global setting for all keys).

MAX CAL: if this bit is clear then all keys recalibrate after a Max On Duration timeout, otherwiseonly the key with the incorrect timing gets recalibrated.

GUARD CHANNEL: bits 0 – 3 are used to set a key as the guard channel (which gets priorityfiltering). Valid values are 0 – 6, with any larger value disabling the guard key feature.

5.12 Address 54: Low Power (LP) Mode

LP MODE: this 8-bit value determines the number of 8 ms intervals between keymeasurements. Longer intervals between measurements yield a lower power consumption butat the expense of a slower response to touch.

Default: 2 (16 ms between key acquisitions)

Table 5-11. Max On/Guard Channel


53 – FO MAX CAL GUARD CHANNEL

Table 5-12. LP Mode


54 LOW POWER MODE

Setting Time

0 8 ms

1 8 ms

2 16 ms

3 24 ms

4 32 ms

...254 2.032s

255 2.040s

229596A–AT42–10/10

AT42QT1070

AT42QT1070

5.13 Address 55: Max On Duration

MAX ON DURATION: this is a 8-bit value which determines how long any key can be in touchbefore it recalibrates itself.

A value of 0 turns Max On Duration off.

Default: 180 (160 ms x 180 = 28.8s)

5.14 Address 56: Calibrate

Writing any nonzero value into this address triggers the device to start a calibration cycle. TheCALIBRATE flag in the detection status register is set when the calibration begins and clearswhen the calibration has finished.

5.15 Address 57: RESET

Writing any nonzero value to this address triggers the device to reset.

Table 5-13. Max Time On


55 MAX ON DURATION

Setting Time

0 Off

1 160 ms

2 320 ms

3 480 ms

4 640 ms

255 40.8s

Table 5-14. Calibrate


56 Writing a nonzero value forces a calibration

Table 5-15. RESET


57 Writing a nonzero value forces a reset

239596A–AT42–10/10

6. Specifications

6.1 Absolute Maximum Specifications

6.2 Recommended Operating Conditions

6.3 DC Specifications

Vdd -0.5 to +6V

Max continuous pin current, any control or drive pin ±10 mA

Short circuit duration to ground, any pin infinite

Short circuit duration to Vdd, any pin infinite

Voltage forced onto any pin -0.5V to (Vdd + 0.5) Volts

CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification conditions for extended periods may affect device reliability.

Operating temperature -40oC to +85oC

Storage temperature -55oC to +125oC

Vdd +1.8V to 5.5V

Supply ripple+noise ±25 mV

Cx load capacitance per key 1 to 30 pF

Vdd = 3.3V, Cs = 10nF, load = 5 pF, 32 ms default sleep, Ta = recommended range, unless otherwise noted

Parameter Description Minimum Typical Maximum Units Notes

Vil Low input logic level – – 0.2Vdd V

Vih High input logic level 0.7Vdd – Vdd + 0.5 V

Vol Low output voltage – – 0.6 V

Voh High output voltage Vdd - 0.7V – – V

Iil Input leakage current – – ±1 µA

249596A–AT42–10/10

AT42QT1070

AT42QT1070

6.4 Power Consumption Measurements

6.5 Timing Specifications

Cx = 5 pF, Rs = 4.7 k

LP ModeIdd (µA) at Vdd =

5V 3.3V 1.8V

0 (8 ms) 1744 906 442

1 (16 ms) 1375 615 305

2 (24 ms) 1263 525 261

4 (32 ms) 1168 486 234

5 (40 ms) 1119 445 221

6 (48 ms) 1089 434 211

Parameter Description Minimum Typical Maximum Units Notes

TR Response timeDI setting

x 8 ms–

LP mode + (DI setting x 8 ms)

ms Under host control

FQT Sample frequency 162 180 198 kHzModulated spread-spectrum (chirp)

TDPower-up delay to operate/calibration time

–

6.6 Mechanical Dimensions

6.7 AT42QT1070X-SSU – 14-pin SOIC

2325 Orchard ParkwaySan Jose, CA 95131

TITLE DRAWING NO.

R

REV. 14S1, 14-lead, 0.150" Wide Body, Plastic GullWing Small Outline Package (SOIC)

2/5/02

14S1 A

A1

E

L

Side View

Top View End View

HE

b

N

1

e

A

D

COMMON DIMENSIONS(Unit of Measure = mm/inches)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information.2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not

exceed 0.15 mm (0.006") per side.3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm

(0.010") per side.4. L is the length of the terminal for soldering to a substrate.5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value

of 0.61 mm (0.024") per side.

A 1.35/0.0532 – 1.75/0.0688

A1 0.1/.0040 – 0.25/0.0098

b 0.33/0.0130 – 0.5/0.02005

D 8.55/0.3367 – 8.74/0.3444 2

E 3.8/0.1497 – 3.99/0.1574 3

H 5.8/0.2284 – 6.19/0.2440

L 0.41/0.0160 – 1.27/0.0500 4

e 1.27/0.050 BSC

269596A–AT42–10/10

AT42QT1070

AT42QT1070

6.8 AT42QT1070X-MMH – 20-pin 3 x 3 mm VQFN

TITLE DRAWING NO. GPC REV. Package Drawing Contact: [email protected] 20M2 ZFC B

20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm, 1.55 x 1.55 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN)

10/24/08

15

14

13

12

11

1

2

3

4

5

16 17 18 19 20

10 9 8 7 6

D2

E2 e

b

K L

Pin #1 Chamfer (C 0.3)

D

E SIDE VIEW

A1

y

Pin 1 ID

BOTTOM VIEW

TOP VIEW A1

A

C

C0.18 (8X)

0.3 Ref (4x)

COMMON DIMENSIONS (Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.75 0.80 0.85

A1 0.00 0.02 0.05

b 0.17 0.22 0.27

C 0.152

D 2.90 3.00 3.10

D2 1.40 1.55 1.70

E 2.90 3.00 3.10

E2 1.40 1.55 1.70

e – 0.45 –

L 0.35 0.40 0.45

K 0.20 – –

y 0.00 – 0.08

279596A–AT42–10/10

6.9 Marking

6.9.1 AT42QT1070-SSU – 14-pin SOICEither part marking can be used.

1

Pin 1 ID

10701R5

Date Code DescriptionW=Week code

W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...Z=52

Date Code

Abbreviated part number

Code revision 1.5, released

1

Pin 1 ID

Abbreviated part number

Code revision 1.5, released

ATMEL QT1070

1R5 YYWWYYWW = Date code, variable

text

289596A–AT42–10/10

AT42QT1070

AT42QT1070

6.9.2 AT42QT1070-MMH – 20-pin 3 x 3 mm VQFNEither part marking can be used.

Date Code,released

42E15Code Revision 1.5, released

Shortened part number in hexadecimal42E = 1070

Pin 1 ID

Date Code DescriptionW=Week code

W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...Z=52

Date Code,released

15 = Code Revision 1.5, released

Abbreviation of part number: (AT42QT1070-MMH)

Pin 1 ID

YZZ = traceability code (variable text)Y = the last digit of the year

(for example 0 for year 2010, 1 for year 2011), ZZ is the trace code for each assembly lot.

17015XYZZ

X = Assembly location code (variable text)

299596A–AT42–10/10

6.10 Part Number

6.11 Moisture Sensitivity Level (MSL)

Part Number Description

AT42QT1070-SSU 14-pin SOIC RoHS compliant IC

AT42QT1070-MMH 20-pin 3 x 3 mm VQFN RoHS compliant IC

MSL Rating Peak Body Temperature Specifications

MSL3 260oC IPC/JEDEC J-STD-020

309596A–AT42–10/10

AT42QT1070

AT42QT1070

Appendix A. I2C-compatible Operation

A.1 Interface BusThe device communicates with the host over an I2C-compatible bus. The following sections givean overview of the bus; more detailed information is available from www.i2C-bus.org. Devicesare connected to the I2C-compatible bus as shown in Figure A-1. Both bus lines are connectedto Vdd via pull-up resistors. The bus drivers of all I2C-compatible devices must be open-draintype. This implements a wired “AND” function that allows any and all devices to drive the bus,one at a time. A low level on the bus is generated when a device outputs a zero.

Figure A-1. I2C-compatible Interface Bus

A.2 Transferring Data BitsEach data bit transferred on the bus is accompanied by a pulse on the clock line. The level of thedata line must be stable when the clock line is high; the only exception to this rule is forgenerating START and STOP conditions.

Figure A-2. Data Transfer

A.3 START and STOP ConditionsThe host initiates and terminates a data transmission. The transmission is initiated when thehost issues a START condition on the bus, and is terminated when the host issues a STOPcondition. Between the START and STOP conditions, the bus is considered busy. As shown inFigure A-3, START and STOP conditions are signaled by changing the level of the SDA linewhen the SCL line is high.

Vdd

Device 1 Device 2 Device 3 Device n R1 R2

SDA

SCL

SDA

SCL

Data Stable Data Stable

Data Change

319596A–AT42–10/10

Figure A-3. START and STOP Conditions

A.4 Address Byte FormatAll address bytes are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit andan acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise awrite operation is performed. When the device recognizes that it is being addressed, it willacknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address byte consisting of aslave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.

The most significant bit of the address byte is transmitted first. The address sent by the hostmust be consistent with that selected with the option jumpers.

Figure A-4. Address Byte Format

A.5 Data Byte FormatAll data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a datatransfer, the host generates the clock and the START and STOP conditions, while the Receiveris responsible for acknowledging the reception. An acknowledge (ACK) is signaled by theReceiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA linehigh, a NACK is signaled.

SDA

SCL

START STOP

SDA

SCL

Addr MSB Addr LSB R/W ACK

START

1 2 7 8 9

329596A–AT42–10/10

AT42QT1070

AT42QT1070

Figure A-5. Data Byte Format

A.6 Combining Address and Data Bytes into a TransmissionA transmission consists of a START condition, an SLA+R/W, one or more data bytes and aSTOP condition. The wired “ANDing” of the SCL line is used to implement handshaking betweenthe host and the device. The device extends the SCL low period by pulling the SCL line lowwhenever it needs extra time for processing between the data transmissions.

Note: Each write or read cycle must end with a stop condition. When reading, a repeatedSTART is allowed. So S, SLA+W, A, S, SLA+R, A, DATA1, A,......,DATAx, /A, P can be sent.

Figure 6-1 shows a typical data transmission. Note that several data bytes can be transmittedbetween the SLA+R/W and the STOP.

Figure 6-1. Byte Transmission

SCL fromMaster

SLA+R/W

1 2 7 8 9

SDA fromTransmitter

AggregateSDA

Data MSB Data LSB ACK

Data Byte

SDA fromReceiver

STOP orNext Data Byte

1 2 7 8 9 1 2 7 8 9

Data MSB Data LSB ACK

Data Byte STOP

SDA

SCL

Addr MSB Addr LSB R/W ACK

START SLA+R/W

339596A–AT42–10/10

Contents

Features ..................................................................................................... 1

1 Pinouts and Schematics ......................................................................... 2

1.1 Pinout Configuration – Comms Mode (14-pin SOIC) .........................................2

1.2 Pinout Configuration – Standalone Mode (14-pin SOIC)....................................2

1.3 Pinout Configuration – Comms Mode (20-pin VQFN) ........................................3

1.4 Pinout Configuration – Standalone Mode (20-pin VQFN) ..................................3

1.5 Pin Descriptions..................................................................................................4

1.6 Schematics .........................................................................................................6

2 Overview ................................................................................................... 9

2.1 Introduction.........................................................................................................9

2.2 Modes.................................................................................................................9

2.2.1 Comms Mode ............................................................................... 9

2.2.2 Standalone Mode.......................................................................... 9

2.3 Keys....................................................................................................................9

2.4 Input/Output (IO) Lines .......................................................................................9

2.5 Acquisition/Low Power Mode (LP)....................................................................10

2.6 Adjacent Key Suppression (AKS) Technology .................................................10

2.7 CHANGE Line (Comms Mode Only) ................................................................10

2.8 Proximity Sensing.............................................................................................11

2.9 Types of Reset .................................................................................................11

2.9.1 External Reset ............................................................................ 11

2.9.2 Soft Reset ................................................................................... 11

2.10 Calibration ........................................................................................................11

2.11 Guard Channel .................................................................................................11

2.12 Signal Processing.............................................................................................12

2.12.1 Detect Threshold ........................................................................ 12

2.12.2 Detect Integrator ......................................................................... 12

2.12.3 Cx Limitations ............................................................................. 12

2.12.4 Max On Duration......................................................................... 13

2.12.5 Positive Recalibration ................................................................. 13

2.12.6 Drift Hold Time............................................................................ 13

2.12.7 Hysteresis ................................................................................... 13

349596A–AT42–10/10

AT42QT1070

AT42QT1070

3 Wiring and Parts ..................................................................................... 13

3.1 Rs Resistors .....................................................................................................13

3.2 LED Traces and Other Switching Signals ........................................................13

3.3 PCB Cleanliness...............................................................................................14

3.4 Power Supply ...................................................................................................14

4 I2C-compatible Communications (Comms Mode Only) ...................... 15

4.1 I2C-compatible Protocol ...................................................................................15

4.1.1 Protocol........................................................................................15

4.1.2 Signals .........................................................................................15

4.2 I2C-compatible Address ...................................................................................15

4.3 Data Read/Write ...............................................................................................15

4.3.1 Writing Data to the Device ...........................................................15

4.3.2 Reading Data From the Device ...................................................16

4.4 SDA, SCL .........................................................................................................17

5 Setups ...................................................................................................... 18

5.1 Introduction.......................................................................................................18

5.2 Address 0: Chip ID ...........................................................................................19

5.3 Address 1: Firmware Version ...........................................................................19

5.4 Address 2: Detection Status .............................................................................20

5.5 Address 3: Key Status ......................................................................................20

5.6 Address 4 – 17: Key Signal ..............................................................................20

5.7 Address 18 – 31: Reference Data ....................................................................20

5.8 Address 32 – 38: Negative Threshold (NTHR).................................................21

5.9 Address 39 – 45: Averaging Factor/Adjacent Key Suppression (AVE/AKS) ....21

5.10 Address 46 – 52: Detection Integrator (DI).......................................................21

5.11 Address 53: FastOutDI/Max Cal/Guard Channel .............................................22

5.12 Address 54: Low Power (LP) Mode..................................................................22

5.13 Address 55: Max On Duration ..........................................................................23

5.14 Address 56: Calibrate .......................................................................................23

5.15 Address 57: RESET .........................................................................................23

6 Specifications.......................................................................................... 24

6.1 Absolute Maximum Specifications....................................................................24

6.2 Recommended Operating Conditions ..............................................................24

6.3 DC Specifications .............................................................................................24

6.4 Power Consumption Measurements ................................................................25

359596A–AT42–10/10

6.5 Timing Specifications........................................................................................25

6.6 Mechanical Dimensions....................................................................................26

6.7 AT42QT1070X-SSU – 14-pin SOIC .................................................................26

6.8 AT42QT1070X-MMH – 20-pin 3 x 3 mm VQFN...............................................27

6.9 Marking.............................................................................................................28

6.9.1 AT42QT1070-SSU – 14-pin SOIC.............................................. 28

6.9.2 AT42QT1070-MMH – 20-pin 3 x 3 mm VQFN............................ 29

6.10 Part Number .....................................................................................................30

6.11 Moisture Sensitivity Level (MSL) ......................................................................30

Appendix A I2C-compatible Operation................................................. 31

A.1 Interface Bus ....................................................................................................31

A.2 Transferring Data Bits.......................................................................................31

A.3 START and STOP Conditions ..........................................................................31

A.4 Address Byte Format........................................................................................32

A.5 Data Byte Format .............................................................................................32

A.6 Combining Address and Data Bytes into a Transmission 33

Associated Documents .......................................................................... 37

Revision History...................................................................................... 37

369596A–AT42–10/10

AT42QT1070

AT42QT1070

Associated Documents• QTAN0062 – QTouch and QMatrix Sensitivity Tuning for Keys, Slider and Wheels

• Touch Sensors Design Guide

Revision History

Revision Number History

Revision A – October 2010 Initial release of document for code revision 1.5

379596A–AT42–10/10

9596A–AT42–10/10

Headquarters International

Atmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: (+1) (408) 441-0311Fax: (+1) (408) 487-2600

Atmel AsiaUnit 01-05 & 16, 19FBEA Tower, Millennium City 5418 Kwun Tong RoadKwun TongKowloonHONG KONGTel: (+852) 2245-6100Fax: (+852) 2722-1369

Atmel Munich GmbHBusiness CampusParkring 4D- 85748 Garching b. MUNICHTel: (+49) 89-31970-111Fax: (+49) 89-3194621

Atmel Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JAPANTel: (+81) 3-3523-3551Fax: (+81) 3-3523-7581

Touch Technology Division1560 ParkwaySolent Business ParkWhiteleyFarehamHampshirePO15 7AGUNITED KINGDOMTel: (+44) 844 894 1920Fax: (+44) 1489 557 066

Product Contact

Web Sitewww.atmel.com

Technical [email protected]

Sales Contactwww.atmel.com/contacts

Literature Requestswww.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to anyintellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS ANDCONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED ORSTATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESSFOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL,PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, ORLOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITYOF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves theright to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the informationcontained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products arenot intended, authorized, or warranted for use as components in applications intended to support or sustain life.

© 2010 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, Adjacent Key Suppression®, AKS®, QTouch®,QMatrix® and others are registered trademarks, QT™ and others are trademarks of Atmel Corporation or its subsidiaries. Other terms andproduct names may be registered trademarks or trademarks of others.

Features1. Pinouts and Schematics1.1 Pinout Configuration – Comms Mode (14-pin SOIC)1.2 Pinout Configuration – Standalone Mode (14-pin SOIC)1.3 Pinout Configuration – Comms Mode (20-pin VQFN)1.4 Pinout Configuration – Standalone Mode (20-pin VQFN)1.5 Pin Descriptions1.6 Schematics

2. Overview2.1 Introduction2.2 Modes2.2.1 Comms Mode2.2.2 Standalone Mode

2.3 Keys2.4 Input/Output (IO) Lines2.5 Acquisition/Low Power Mode (LP)2.6 Adjacent Key Suppression (AKS) Technology2.7 CHANGE Line (Comms Mode Only)2.8 Proximity Sensing2.9 Types of Reset2.9.1 External Reset2.9.2 Soft Reset

2.10 Calibration2.11 Guard Channel2.12 Signal Processing2.12.1 Detect Threshold2.12.2 Detect Integrator2.12.3 Cx Limitations2.12.4 Max On Duration2.12.5 Positive Recalibration2.12.6 Drift Hold Time2.12.7 Hysteresis

3. Wiring and Parts3.1 Rs Resistors3.2 LED Traces and Other Switching Signals3.3 PCB Cleanliness3.4 Power Supply

4. I2C-compatible Communications (Comms Mode Only)4.1 I2C-compatible Protocol4.1.1 Protocol4.1.2 Signals

4.2 I2C-compatible Address4.3 Data Read/Write4.3.1 Writing Data to the Device4.3.2 Reading Data From the Device

4.4 SDA, SCL

5. Setups5.1 Introduction5.2 Address 0: Chip ID5.3 Address 1: Firmware Version5.4 Address 2: Detection Status5.5 Address 3: Key Status5.6 Address 4 – 17: Key Signal5.7 Address 18 – 31: Reference Data5.8 Address 32 – 38: Negative Threshold (NTHR)5.9 Address 39 – 45: Averaging Factor/Adjacent Key Suppression (AVE/AKS)5.10 Address 46 – 52: Detection Integrator (DI)5.11 Address 53: FastOutDI/Max Cal/Guard Channel5.12 Address 54: Low Power (LP) Mode5.13 Address 55: Max On Duration5.14 Address 56: Calibrate5.15 Address 57: RESET

6. Specifications6.1 Absolute Maximum Specifications6.2 Recommended Operating Conditions6.3 DC Specifications6.4 Power Consumption Measurements6.5 Timing Specifications6.6 Mechanical Dimensions6.7 AT42QT1070X-SSU – 14-pin SOIC6.8 AT42QT1070X-MMH – 20-pin 3 x 3 mm VQFN6.9 Marking6.9.1 AT42QT1070-SSU – 14-pin SOIC6.9.2 AT42QT1070-MMH – 20-pin 3 x 3 mm VQFN

6.10 Part Number6.11 Moisture Sensitivity Level (MSL)

Appendix A. I2C-compatible OperationA.1 Interface BusA.2 Transferring Data BitsA.3 START and STOP ConditionsA.4 Address Byte FormatA.5 Data Byte FormatA.6 Combining Address and Data Bytes into a Transmission

Associated DocumentsRevision History

QTouch 7-channel Sensor IC · LP mode controls the intervals between acquisition measurements....

Documents

Transcript of QTouch 7-channel Sensor IC · LP mode controls the intervals between acquisition measurements....