Pyxis

Pyxis

Aaron Martin

April Lewis

Steve Sherk

September 5, 2005 Pyxis1600 2

Pyxis1600

General-purpose 16-bit RISC microprocessor

16 16-bit registers 24-bit address bus Up to 16MB of addressable memory


Registers 16 registers 3 special purpose

– $r0 – zero– $r14 – stack pointer– $r15 – return address

13 general purpose – $r1 - $r13

Status register (sr)– 8 bits – carry (c), overflow (o), negative (n), zero (z), interrupt

enable (i), less than (l), 2 bits unused Program counter (pc) Accumulator high (ah) and accumulator low (al)

– Used for multiply and divide Page register (pr)

– Sets the high order 8 bits in the 24-bit address space


Instruction Formats

16-bit instructions 7-bit opcode 1 bit to indicate information in next word rd is source and target rs is source Branch instructions use special format

opcode rd rs

Displacement / Immediate

ext

0

015

315 4789

opcode branch type address

089121315

R-type

B-type


Instruction SetCategory Instruction Example Meaning

add add <rd>,<rs> r3 = r3 + r4add immediate add <rd>, #100 r3 = r3 + 100subtract sub <rd>, <rs> r3 = r3 - r4subtract immediate subi <rd>, #200 r3 = r3 - 200divide div <rd>, <rs> <ah, al> = r3 / r4divide immediate divi <rd>, #4 <ah, al> = r3 / 4multiply mult <rd>, <rs> <ah, al> = r3 * r4multiply immediate multi <rd>, #6 <ah, al> = r3 * 6move from al mal <rd> r4 = (al)move from ah mah <rd> r4 = (ah)load word lw <rd>, 100(<rs>) r3 = Memory[r4 + 100]store word sw 200(<rd>), <rs> Memory[r3 + 200] = r4load byte lb <rd>, 100(<rs>) r3[7:0] = Memory[r4 + 100]store byte sb 200(<rd>), <rs> Memory[r3 + 200] = r4[7:0]load page register lpr #100 pr = 100

Arithmetic

Data Transfers


Instruction SetCategory Instruction Example Meaning

and and <rd>, <rs> r3 = r3 & r4andi andi <rd>, #4 r3 = r3 & 4or or <rd>, <rs> r3 = r3 | r4ori ori <rd>, #4 r3 = r3 | 4nor nor <rd>, <rs> r3 = ~(r3 | r4)nori nori <rd>, #4 r3 = ~(r3 | 4)comp comp <rd>, <rs> set sr bits after compareshl shl <rd>, #10 r3 = r3 << 10shr shr <rd>, #10 r3 = r3 >> 10beq beq #100 if sr[z] = 1, go to PC + 100bne bne #100 if sr[z] = 0, go to PC + 100blt blt #100 if sr[l] = 1, go to PC + 100bgt bgt #100 if sr[l] = 0, go to PC + 100jmp jmp #2500 go to 2500jmpl jmpl #2500 r15 = PC + 2, go to 2500jmpr jmpr <rd> go to r4

Other no operation nop stall for one clock cycle

Logical

Conditional Branch

Unconditional Branch


Addressing Modes

Register direct Register indirect plus displacement

– Use r0 for absolute addressing PC-relative Immediate


Interrupts

Options for handling interrupts– Handled by hardware

• Each interface wired to its own pin

– Handled by software• Use interrupt vector that points to different

routines• Have separate priority level for each interface• All interrupts go to same routine that polls each

device to see which one caused the interrupt


Block Diagram Major Components

PC

InstructionRegister

Registers

Control

ALU

Memory

Instruction[15:8]

Instruction[7:4]

Instruction[3:0]

Read / WriteRegister

ReadRegister

OpCode Dest. Reg Source Reg15 8 7 4 3 0


Sub-systems Internal to the microprocessor

– Fetch and Memory access logic• addressing modes

– ALU• add, sub, mult, div, memory access calculations

(PC+offset)– Control logic

• micro instructions, control signal labels– Register implementation

External– Serial bus implementation

• hardware associated with serial port


Assembler Converts assembly code into machine language Uses a look-up table to find machine code for each

instruction– Some instruction are “psudo-instructions” implemented with

other, lower level instructions

Written in Perl and implemented on a PC– Perl is good for parsing and string manipulation

Machine code saved on EPROM and loaded onto microprocessor – .asm .HEX EPROM burning software


Hardware XCV300 FPGA - 322,970 logic gates - 8 KB on-chip RAM 128KB off-chip SRAM 128KB off- chip EPROM


Input / Output Devices

Serial RS232 port Monitor / LCD Keyboard / Keypad USB port


Feature Priority General-purpose processor

– Multi-cycle design– Complete reduced instruction set– Some test code, Game, or Benchmark Program

Assembler On-chip hardware divider C compiler Floating-point unit L1 data and instruction cache 5 stage pipeline design


Roles and Responsibilities Aaron

– Logic design– Verilog programming

April– Assembler– Software interfaces

Steve– Hardware components– Hardware interfaces

All– Integration and Test– Documentation


ScheduleID Task Name Duration Start Finish

1 Projec t Definitiion 1 wk Mon 8/29/05 Fri 9/2/05

2 Preliminary Des ign Rev iew 1 day Thu 9/8/05 Thu 9/8/05

3 Func tion Definition 1 wk Wed 8/31/05 Tue 9/6/05

4 Hardware Definition 3 days Thu 9/8/05 Mon 9/12/05

5 Part Selec tion 3 days Thu 9/8/05 Mon 9/12/05

6 Software Definition 5 days Thu 9/8/05 Wed 9/14/05

7 Language Choice 1 wk Thu 9/8/05 Wed 9/14/05

8 Hardware Design 10 days Thu 9/15/05 Wed 9/28/05

9 Layout 1 wk Thu 9/15/05 Wed 9/21/05

10 Hardware Tes t 1 wk Thu 9/22/05 Wed 9/28/05

11 Software Design 15 days Thu 9/15/05 Wed 10/5/05

12 Logic Design 15 days Thu 9/15/05 Wed 10/5/05

13 State diagrams 1 wk Thu 9/15/05 Wed 9/21/05

14 ALU 1 wk Thu 9/22/05 Wed 9/28/05

15 Decoder 1 wk Thu 9/22/05 Wed 9/28/05

16 Controller 2 wks Thu 9/22/05 Wed 10/5/05

17 Logic Tes t 1 wk Thu 9/29/05 Wed 10/5/05

18 Assembler 2 wks Thu 9/22/05 Wed 10/5/05

19 Critical Des ign Rev iew 1 day Thu 10/6/05 Thu 10/6/05

20 Integration 26 days Wed 9/21/05 Wed 10/26/05

21 Software Interfaces 1 wk Wed 10/5/05 Tue 10/11/05

22 Hardware Interfaces 1 wk Wed 10/5/05 Tue 10/11/05

23 SW / HW Interfaces 26 days Wed 9/21/05 Wed 10/26/05

24 Miles tone 1 1 day Thu 10/27/05 Thu 10/27/05

25 Test Programs 10 days Thu 10/27/05 Wed 11/9/05

26 Benchmark 2 wks Thu 10/27/05 Wed 11/9/05

27 Game1 2 wks Thu 10/27/05 Wed 11/9/05

28 Game2 2 wks Thu 10/27/05 Wed 11/9/05

29 Miles tone 2 1 day Thu 11/17/05 Thu 11/17/05

30 System Test 3 wks Thu 11/17/05 Wed 12/7/05

31 Documentation 70 days Thu 9/1/05 Wed 12/7/05

All

9/8

All

All

All

Steve

Steve

All

April

Steve

Aaron

Aaron

April

10/6

April

Steve

Aaron

10/27

Aaron

April

Steve

11/17

All

All

S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T FAug 28, '05 Sep 4, '05 Sep 11, '05 Sep 18, '05 Sep 25, '05 Oct 2, '05 Oct 9, '05 Oct 16, '05 Oct 23, '05 Oct 30, '05 Nov 6, '05 Nov 13, '05 Nov 20, '05 Nov 27, '05 Dec 4, '05


Risks and Contingency Plan

Risk Resolution

Problems in logic design Optional features will not be implemented

Bad Parts Several XCV300 chips are available, other components are inexpensive

Problems with hardware interfaces

Several options exist (I.e. LCD vs. monitor, RS232 vs. USB)

Problems with software interfaces

Validate all software interfaces early in schedule to allow time to correct if necessary

Questions

Pyxis

Documents

Transcript of Pyxis