I NTRODUCTION

The digital clock can be easily constructed using readily-available ICs and components. The block diagram of the digital clock is shown in figure.1. The basic 1Hz clock pulse signal is obtained from the clock pulse generator using a 4.194304Mz crystal. It is divided by 60 by the second’s section to produce one clock pulse every minute, which is further divided by 60 to produce one clock pulse every hour. Both the seconds and minutes sections use divide-by-10 and divide-by-6 counters. The clock pulse from the minute’s section is applied to the hour’s section, which is divide-by-12 counter to control the hour and AM/PM indication with the help of code converter circuit and J-K flip-flop. The output of all counters is displayed on 7-segment displays after suitable decoding.

BLOCK DIAGRAM

Fig. shows the circuit diagram of digital clock with AM and PM indication. The heart of the circuit is precision 1- second oscillator section that is built around 14-stage counters CD4060 (IC1 and IC2). The clock accuracy depends upon the 1-second oscillator, which divides crystal frequency (4.194304 MHz) by 16,348 to output 256 Hz at pin of IC1, which is further divided by 256 to output one pulse per second at pin 14 of IC2. Resistors R1 and R2 are biasing and power limiting resistors, respectively.

The one-second pulse is applied to the clock input of decade counter 74LS90(IC3), which is a 4-stage ripple counter containing a master/slave flip-flop acting as a divide-by-2 counter and three flip-flops connected as a divide-by-5 counter. Clock input CP1of the divide –by-5 sections must be externally connected to Q0 output of the divide-by-2 section.CPO clock input of the divides-by-2section receives the clock signal from the oscillator output and a BCD count sequence is produced.

Q0 through Q3 outputs of the decade counter (IC3) are connected to A0 through A3 input pins of the BCD to 7 segment decoder/driver 74LS47 (IC9), respectively. IC9 accepts the 4-line input data generates their complements internally and decodes the data with seven AND/OR gates having open collector outputs to drive LED segments directly. The ‘a’ through ‘f’ outputs pf IC 74LS47 (IC9) are connected to the corresponding inputs of 7-segment display DIS1. All the 7-segment displays work in the same fashion. Resistors R3 through R8 are used as current-limiting resistors for display DIS6 down to DIS1, respectively. Each display comprises seven light-emitting diodes with their common anodes connected together. This configuration is known as the common-anode,7-segment display.

ICs 74LS90 (IC4) are cascaded to produce units’ tens’ digit of the seconds’ display. Decade counter IC3 is reset to start counting from 0 after ninth count. Pin 11 (Q3) of IC3 is connected to clock input pin 14 (CP 0) of IC4. After ninth count, Q3 output of IC3 goes from high to low and provides a clock signal to CP0 (pin 14) of IC4.

IC4 contains a flip-flop acting as a divide-by-2 counter and three flip-flops connected as a divide-by-6 counter. After fifth count, Q2 output of IC4 goes from high to low and IC4 starts counting from 0.

The next clock pulse resets the second’s section after it counts up to 59 seconds and provides a clock pulse to the minute’s section. IC5 and IC6 are used for

generation of units’ and tens’ digits of the minutes’ display with the help of IC11 and IC12, respectively. Q2 output of IC4 is connected to the clock input (CP0) of IC5 through transistor T1. Resistor R9 is pulled low and the high output of inverters N5 provides forward bias to transistor T1. Q2 output of IC4 is available at pin 14 of IC5 through the low-resistance path of transistor T1 and T2 are connected to pin 14 of IC5.

Switch S1 is used for setting the minute’s time. When switch S1 is pressed, transistor T1 is reverse biased and transistor T2 is forward is biased. Forward-biased transistor T2 provides a low resistance path for 1Hz clock signal and, at the same time, transistor T1 blocks the signal from Q2 output from IC4.

The minute section works the same way as the second’s section. After 59 count, the next clock pulse reset the minute section and provides a clock pulse(through transistor T3) to clock input pin 14 of IC 74LS93 (IC7) of the hours section.

IC 74LS93 is four-bit binary counter that consists of four master/slave flip-flop which are internally connected as a divide-by-2 counter section and a divide-by-8 counter section.

POWER SUPPLY CIRCUIT

Each section has a separate clock input, which initiates counting on receiving a high to low clock pulse. QA output of the divide-by-2 section must be externally connected to CP1(pin 1) clock input of the divide-by-8 counter section. The input count pulse is applied on CP 0(pin 14) clock input of divide-by-2 counter section. This configuration acts as a divide-by-16 counter in normal condition.

Binary counter 74LS93 (IC7) is used as a divide-by-12 counter in the circuit (Fig 2). This is achieved by connecting by its QC and QD outputs to MR1 and MR2 asynchronous master reset inputs, respectively. When both QC and QD

outputs become 1, the counter is reset to 0000 and as a divide-by-12 counter. It counts the clock pulse and gives the binary output from 0000 to 1011.

The outputs of IC7 are given to cose converter section. The code converter section converts the 4-bit binary input ( QA through QD) into 5-bit code (HA

through HE) as shown in the table. For inputs from 0001 through 1001, it produces the same outputs. But when inputs are 1010, 1011 and 0000, the code converter section converts these into 10000, 10001, and 10010, respectively. The code converter circuit comprises NOT gates N1 through N4, AND gates N8 through N13 and OR gates N14 and N15. HA through HE outputs of the code converter are simplified by using Karnaugh map as follows:

HA = QA

HA¿QD .(QB+QA .QC )

HC= QC

HD = QD.QB

HE = QD.QB+QA .QB .QC .QD

HA through HD outputs of the code converter are connected to 7-segment decoder 74LS47 (IC13) to display the units digit of hour and He is connected to IC14 to display the tens’ digit of hour. After ninth count, tens’ digit of the hour display becomes ‘1’ (HE goes high) and units’ digit resets to ‘0’. To display 01.00.00 after 12.59.59, the code converter circuit resets the tens’ digit to ‘0’ and the units’ digit to ’1’.

BINARY INPUT CONVERSION INTO 5-BIT CODE

Edge-trigger flip-flop 74LS76 (IC15) is used for AM and PM indications in conjunction with CD4017 (IC8). He output of the code converter controls the AM/PM display. It is connected to clock input pin 14 of IC8 via NOT gate N7.

Every 12 hours, He outputs goes from high to low. The high clock input of IC8 takes its output pin 2(Q1) high, which, in turn, triggers the flip-flop and resets IC8 via diode D1.

Initially, Q 2output of IC15 is high as Q2 putput is low. Thus AM LED1 (green) is on. After 12 hours, the first clock pulse turns Q2 high and its compliment Q 2

goes low. As a result, PM LED2 (red) glows.

Again after twelve hours,HE output of the code converter goes from high to low and gives another clock pulse to the flip-flop with help of CD4017.NowQ2 output goes low and its complementQ 2 becomes high. Thus AM LED glows.

Push-to-on switches S1 and S2 are used to manually set minute and hour, respectively. The 1Hz clock from the output of IC2 is used to advance the minute’s counters (IC5 and IC6) or the hours counter (IC7) at a fast rate by pressing switch S1 (of the minutes’ set) or switch S2 (of the hours’ set). Switch S3 is used for initial resetting of IC8.

The power supply circuit is shown in Fig 5. The AC main supply is stepped down by transformer X1 to deliver secondary Output of 9V AC, 300mA. The output of the transformer is rectified by full wave rectifier comprising diodes D2 through D5. Capacitor C3 acts as a filter to eliminate ripple. Regulator 7805 (IC21) provide regulated 5V power supply to the digital clock circuit.

An actual-size, single-side PCB for the digital clock is shown in Fig.3 and its component layout in Fig.4.HA through HE inputs of ICs 13 and 14 have been terminated on Con-1 and suitably marked on the PCB .These pins are to be connected to code converter outputs with identical marking and terminated on pads using jumpers.

CIRCUIT DIAGRAM OF DIGITAL CLOCK USING DISCRETE IC’S

LAYOUT DESIGN

CIRCUIT LAYOUT

COMPONENT LAYOUT