PROGRESS ON ENERGY SUM ELECTRONIC BOARD

VXS Backplane

Energy Sum

18 fADC

VME64

High SpeedSerial

VME64

16 CH

16 CH16 CH16 CH16 CH

16 CH 16 CH 16 CH

Detector Signals

Crate Sum to Trigger

Energy Sum In DAQ System

Parallel Or Serial Transmission

Parallel Transmission• 16 ADC per fADC x 18 fADC = 288 wires• fADC data rate = 250 MHz => LVDS => 576 wires• Difficult if not impossible to design backplane that balances 576 wires with each other and with clock

Serial Transmission• 36 LVDS wires• 16 bits * 250 MHz => 4 GBits/Second• VXS Bus Support up to 10 GBits/Second• Commercially available VXS backplane

Xilinx FPGA V4 with 6.5 GBits/Second Transceiver is now available

But VXS ?????

Exploring VXS

Scale DownEnergy Sum

PENTEK

fADC

Exploring VXS

Step # 1. Exploring PentekStep # 2. Design Scale DownEnergy SumStep # 3. Test Scale Down Energy SumStep # 4. Energy Sum Bit Error TestStep # 5 Energy Sum and PentekStep # 6. fADC Loop Back Step # 7. 2 fADC and Energy Sum

Step # 8. Design Full Energy Sum Step # 10. 18 fADC and Full Energy Sum

Step # 1. Exploring Pentek

CONNECTORWITH 8 WIRES CONNECTINGTX PINS TO RX PINS(4 LANES)

JTAG

ADC FIFO

XILINX Aurora MGTTransmitUserCLKReceiveStatus

FIFO

FPGA VHDL CODE

XILINX CHIP SCOPE

PENTEK

CLOCK

ChipScopeTx Rx

Tdelay Test Result :• Tdelay =• Extra Data 2.5 Gbits/Sec

3.125 GBits/Sec

DOUG CURRY

Step # 2. Design Scale DownEnergy Sum

LINE SIMXLINXMANUAL

DOUG CURRY

Energy Sum

Step # 3. Test Energy Sum

Tx

Rx

DAC2Data Generator

XILINX Aurora MGTTransmitUserCLK

ReceiveStatus

Data Assembler

FPGA VHDL CODE

DAC3

XILINX CHIP SCOPE

ENERGYSUM

156.25MHzCLOCK

CONNECTORWITH 8 WIRES CONNECTINGTX PINS TO RX PINS(4 LANES)

PC

SCOPE

JTAG

Energy Sum

DAC 2

DAC 3HARDWARE SETUP

FIRMWARE SETUP

MGT IS SET UP TO RUN AT

2.5 GBPS FOR TEST 13.125 GBPS FOR TEST 2

DAC 1 and DAC2 Measurement with Tektronics SCOPE1. Test 1 (2.5 GBPS)

• DAC1 to DAC2 delay is 732 ns• DAC Clock (UserCLK) is 125 MHz

2. Test 2 (3.125 GBPS)• DAC1 to DAC2 delay is 580 ns• DAC Clock (UserCLK) is 156.25 MHz

Test 1

#of UserCLK

Test 1

Absolute Time = #of UserCLK* 8 ns

Test 1

#of UserCLK

Test 1

Absolute Time = #of UserCLK * 6.4 ns

DAC1 to DAC2 DELAY

87 696 87 556.8

MGT ReSYNC Interval

4992 39936 4992 31948.8

Measurement with CHIPSCOPE

No Missing DataNo Extra Data

Step # 3. Result Of Loop Back Test

Step # 3. Loop Back Test. DAC1 and DAC2 With TEK Scope

Step # 3. Loop Back Test. DAC1 and DAC2 With ChipScope

Step # 3. Loop Back Test. Resync Shown With ChipScope

Step # 4.Energy Sum Bit Error TestCONNECTORWITH 8 WIRES CONNECTINGTX PINS TO RX PINS(4 LANES)

PC

SCOPE

JTAG

Energy Sum

DAC 2

DAC 3HARDWARE SETUP

DAC1 XILINXIBERT

• Integrate Bit Error Ratio Tester• Tweaking MGT operating and electrical paramaters.

FPGA

DAC2

COLLECTORCARD

156.25MHzCLOCK

MGT IS SET UP TO RUN AT

2.5 GBPS FOR TEST 33.125 GBPS FOR TEST 4

Step # 4 IBERT 2.5GBPS After 4 Hours

Step # 4 IBERT 3.125 GBPS After 4 Hours

Step # 5 Energy Sum and Pentek

Energy SumPentek PC 2

GENERATOR125MHz

SCOPE

PC 1

HARDWARE SETUP

FIRMWARE SETUP

DAC2

Data Generator

XILINX Aurora MGT Transmit

UserCLK

Receive

Status

Data Assembler

FPGA VHDL CODE

DAC3

XILINX CHIP SCOPE

COLLECTORCARD

156.25MHzCLOCK

XILINX CHIP SCOPE

PENTEK CARD

XILINX Aurora MGT

Receive Rx Data

UserCLK

Transmit Tx Data

Status

FPGA VHDL CODE

4 Lanes16bits / lane

• 2.5 GBITS• Lane 0 => Constant 0xAAAA; Lane 1 => Ramp Up• Lane 2 => Constant 0xCCCC; Lane 4 => Ramp Down• DAC 2 and DAC 3 show RampUp sent and received

GENERATOR125MHz

Step # 5 Energy Sum and Pentek

• USER_CLOCK is 125 MHz• DELAY FROM DAC 2 to DAC 3 is 134 USER_CLOCK (1.072 uS)• NO Missing Data• MGT never lost lock in 8 hours• MGT ReSYNC Interval is 4992 USER_CLOCK. Resync duration is 6 USER_CLOCK

Step # 5 Energy Sum and Pentek. Result

CONCLUSION: • XILINX AURORA MGT CAN BE USED TO TRANSFER DATA FROM fADC TO ENERGY SUM.

Step # 6. fADC Loop Back

To Be Continued

Step # 7. 2 fADC and Energy Sum

Step # 8. Design Full Energy Sum

Step # 9. 18 fADC and Full Energy Sum