Electronic developments Electronic developments for the HADES RPC wall: for the HADES RPC wall: overview and progressoverview and progress

A. Gil A. Gil aa, D. Belver , D. Belver bb, P. Cabanelas , P. Cabanelas bb, E. Castro , E. Castro bb, J. Díaz , J. Díaz aa, J.A. , J.A. Garzón Garzón bb, D.González-Díaz , D.González-Díaz cc, W. Koenig , W. Koenig cc, J.S. Lange , J.S. Lange cc, G. May, P. , G. May, P.

Skott Skott cc, M. Traxler , M. Traxler cc

aa IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain. IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain.bb LabCAF, Dpto. de Física de Partículas, Universidade de LabCAF, Dpto. de Física de Partículas, Universidade de

Santiago de Compostela, Santiago de Compostela, 15782, Spain.Santiago de Compostela, Santiago de Compostela, 15782, Spain.cc GSI, Darmstadt,64291, Germany. GSI, Darmstadt,64291, Germany.

TWEPP-07

3-7 September 2007

Prague

OUTLINEOUTLINE INTRODUCTION TO HADES INTRODUCTION TO HADES

EXPERIMENTEXPERIMENT OVERVIEW OF TESTED ELECTRONICSOVERVIEW OF TESTED ELECTRONICS

FRONT-END ELECTRONICSFRONT-END ELECTRONICS DAUGHTERBOARDDAUGHTERBOARD MOTHERBOARDMOTHERBOARD

READ OUT SYSTEMREAD OUT SYSTEM RESULTSRESULTS

CURRENT PROGRESS: NEW CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS DEVELOPED ELECTRONICS

PLAN FOR THE NEXT TESTSPLAN FOR THE NEXT TESTS

OUTLINEOUTLINE INTRODUCTION TO HADES INTRODUCTION TO HADES

EXPERIMENTEXPERIMENT OVERVIEW OF TESTED ELECTRONICSOVERVIEW OF TESTED ELECTRONICS

FRONT-END ELECTRONICSFRONT-END ELECTRONICS DAUGHTERBOARDDAUGHTERBOARD MOTHERBOARDMOTHERBOARD

READ OUT SYSTEMREAD OUT SYSTEM RESULTSRESULTS

CURRENT PROGRESS: NEW CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS DEVELOPED ELECTRONICS

PLAN FOR THE NEXT TESTSPLAN FOR THE NEXT TESTS

HADES EXPERIMENTHADES EXPERIMENT

Detection of electron-Detection of electron-positron pairs produced positron pairs produced in relativistic hadron-in relativistic hadron-nucleus and nucleus-nucleus and nucleus-nucleus collisionsnucleus collisions with with the goal of the goal of studying studying vector meson propertiesvector meson properties in nuclear matterin nuclear matter, both , both normal and hot and normal and hot and compressed.compressed.

Consists of several Consists of several subdetectors for:subdetectors for: TrackingTracking TriggeringTriggering Particle identificationParticle identification Momentum Momentum

reconstructionreconstruction

High Acceptance DiElectonHigh Acceptance DiElecton SpectrometerSpectrometer

Located at the SIS accelerator of GSI, Darmstadt (Germany)Located at the SIS accelerator of GSI, Darmstadt (Germany)

Goal of the Hades RPC project: upgrade the Goal of the Hades RPC project: upgrade the low angles Time of Flight (TOF) detectorlow angles Time of Flight (TOF) detector

HADES EXPERIMENTHADES EXPERIMENT Area of polar angles <45ºArea of polar angles <45º

low particle ratelow particle rate ((up to 700 Hz/cm2up to 700 Hz/cm2))

Existing temporary low angles TOF Existing temporary low angles TOF detector (called TOFino):detector (called TOFino):- Low time resolution (350ps)- Low time resolution (350ps)- Low granularity - Low granularity

Cross section of HADESCross section of HADES

BeamBeam RICH

Target

MDCs

Coil

MDCs TOF Shower

RPC

TOFino

Front view from insideFront view from inside

Upgrade using RPC technology:Upgrade using RPC technology:-Time resolutions lower than 100psTime resolutions lower than 100ps-Cost-effective solutionCost-effective solution

RPC wallRPC wallThe RPC wall contains 1024 double-sided The RPC wall contains 1024 double-sided

readout cells (2048 channels)readout cells (2048 channels)

80 times larger granularity80 times larger granularity

Will allow collisions from C-C to Will allow collisions from C-C to Au-Au at 1.5GeVAu-Au at 1.5GeV

Sectors are filled with RPC cellsSectors are filled with RPC cells

Acceptance close to 100%Acceptance close to 100%

Double layerDouble layer

RPC cellsRPC cells

CHEAP MATERIALS:CHEAP MATERIALS:AluminiumAluminiumGlassGlass

SHIELDED CELLS:SHIELDED CELLS:Crosstalk < 1% Crosstalk < 1%

STANDARD GASSTANDARD GAS MIXTURE:MIXTURE:

Freon (85%)Freon (85%)SF6 (15%)SF6 (15%)Isobutane (5%)Isobutane (5%)

RPC Gas Box & RPC Gas Box & cells(P. Fonte et al. cells(P. Fonte et al. LIP-Coimbra)LIP-Coimbra)

Structure of the HADES RPC cellsStructure of the HADES RPC cells

OUTLINEOUTLINE INTRODUCTION TO HADES INTRODUCTION TO HADES

EXPERIMENTEXPERIMENT OVERVIEW OF TESTED ELECTRONICSOVERVIEW OF TESTED ELECTRONICS

FRONT-END ELECTRONICSFRONT-END ELECTRONICS DAUGHTERBOARDDAUGHTERBOARD MOTHERBOARDMOTHERBOARD

READ OUT SYSTEMREAD OUT SYSTEM RESULTSRESULTS

CURRENT PROGRESS: NEW CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS DEVELOPED ELECTRONICS

PLAN FOR THE NEXT TESTSPLAN FOR THE NEXT TESTS

TRB

MB DB

To ethernet

RPC cells

ELECTRONICS ELECTRONICS

Read out systemRead out system

Front EndFront End

TRB

MB DB

To ethernet

RPC cells

ELECTRONICS ELECTRONICS Front EndFront End

Not enough number of channels to design an ASIC Not enough number of channels to design an ASIC

Built with commercially available componentsBuilt with commercially available components

Space restrictions due to geometrySpace restrictions due to geometry

Requires low power consumption to avoid heating problemsRequires low power consumption to avoid heating problems

FRONT END ELECTRONICSFRONT END ELECTRONICS

Front End set up on the RPC sectorFront End set up on the RPC sector

Detector active area

100ns

50mV

INPUT: Short analog pulses (about 500ps INPUT: Short analog pulses (about 500ps rise time and 5ns width) from the RPC cells.rise time and 5ns width) from the RPC cells.

Electronic requirements:Electronic requirements:A large bandwidth to deal with the short rise A large bandwidth to deal with the short rise timestimesLow electronic jitter and noise for good time Low electronic jitter and noise for good time resolutionsresolutions

DAUGHTERBOARDDAUGHTERBOARD

5cm

4.5cm

1 2 3 4

4 electronic channels/board 4 electronic channels/board (two in each side)(two in each side)

All SMT components All SMT components (0603 size of R & C)(0603 size of R & C)

6 Layer board6 Layer board

2 4

Takes analog signals from 2 RPC cells and provides a Takes analog signals from 2 RPC cells and provides a digital output pulsesdigital output pulses

Front sideFront side

Back sideBack side

Generates a timing-signal (output pulse) . It contains information about:Generates a timing-signal (output pulse) . It contains information about: Arrival time (for TOF measurement)Arrival time (for TOF measurement)Leading edgeLeading edge ChargeChargeWidth(Trailing edge)Width(Trailing edge)

DAUGHTERBOARDDAUGHTERBOARD

4 ch. out

C

Amplifier

PECL-LVDS

ToF-Threshold

In

GALI-S66 Monolithic(20dB, 2GHz)

MAX9601-2ch (500ps Propagation Delay)

SN65LVDT100

R

2k2 Trigger Out. Σ4ch.

SAMTEC16 diff. pins

BFT92 Wideband PNP Transistor

PECL comparator

width~charge

Arrival time

OPA690 Wideband Op. Amplifier

MAX9601-2ch

ToT-Threshold Integrator

C

Latch enable

QQ/C

QQ/

Walk Walk errorerror

Small walk error due to:Small walk error due to:

-Small rise time-Small rise time

Further reduction by:Further reduction by:

-Decreasing TOF thr.-Decreasing TOF thr.

-Charge correction-Charge correction

IdealIdeal correctioncorrection

Latch enable

TOT thrTOT thr

width~charge

Integrated signal

Amplified RPC signal

Output pulseTime (100ns/div)

Voltage (50mV/div)

xGToF

ToT

RPC signal

RPC arrival time

ƒ

DAUGHTERBOARDDAUGHTERBOARD

TOF thrTOF thr

Part of the Front End Electronics that did not fit on the Part of the Front End Electronics that did not fit on the Daughterboard Daughterboard interfaces DB with Readout system interfaces DB with Readout system

Provides support to 32 channels (8 DB)Provides support to 32 channels (8 DB) 12 layer board12 layer board

MOTHERBOARDMOTHERBOARD

DAC

inverters

Connector to DB

DAC

inverters

Connector to DB

Low level trigger (N to 1)

Connector to TRB +5V -5V +3.3V DC input

Test signal distribution

LVDS conv

DAC

inverters

Connector to DB

DAC

inverters

Connector to DB

DAC

inverters

Connector to DB

DAC

inverters

Connector to DB

DAC

inverters

Connector to DB

DAC

inverters

Connector to DB

DC filterDC filter DC filter DC filter

MOTHERBOARDMOTHERBOARD

Main tasks:Main tasks:

Delivers the timing-signals from 8 Daughterboard to the Read out Delivers the timing-signals from 8 Daughterboard to the Read out board.board.

Supply stable voltage to the DaughterboardsSupply stable voltage to the Daughterboards (+5V,-5V,+3.3V)(+5V,-5V,+3.3V)

Combines the 32 multiplicity signals coming out from the Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal.Daughterboard to provide a low level trigger signal.

Allocates DACs for the threshold voltages of the comparators on the Allocates DACs for the threshold voltages of the comparators on the DaugherboardDaugherboard

Minor tasks:Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC Test signals distribution, LVDS repeaters,interface for DAC

programming, etcprogramming, etc

40cm

6cm

32 channels32 channels12 Layer board12 Layer board

MOTHERBOARDMOTHERBOARDInterface: Low Voltage Differential Signaling (LVDS)Interface: Low Voltage Differential Signaling (LVDS)

Advantages: Advantages: Low power consumptionLow power consumption High noise inmunityHigh noise inmunity

Diferential impedance matching lines and termination resistors (100Diferential impedance matching lines and termination resistors (100ΩΩ) to ) to reduce signal reflections/distorsionsreduce signal reflections/distorsions

MOTHERBOARDMOTHERBOARD

Main tasks:Main tasks:

Delivers the timing-signals from 8 Daughterboard to the Read out Delivers the timing-signals from 8 Daughterboard to the Read out board.board.

Supply stable voltages to the DaughterboardsSupply stable voltages to the Daughterboards (+5V,-5V,+3.3V)(+5V,-5V,+3.3V)

Combines the 32 multiplicity signals coming out from the Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal.Daughterboard to provide a low level trigger signal.

Allocates DACs for the threshold voltages of the comparators on the Allocates DACs for the threshold voltages of the comparators on the DaugherboardDaugherboard

Minor tasks:Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC Test signals distribution, LVDS repeaters,interface for DAC

programming, etcprogramming, etc

40cm

6cm

MOTHERBOARDMOTHERBOARDRipple filtering: Low Dropout RegulatorsRipple filtering: Low Dropout Regulators

Motherboard

+5V-5V

+3.3V

+5V,+3.3V: +5V,+3.3V: ADP3338ADP3338 (1A) (1A)

-5V: -5V: LT1175 (0.5A)LT1175 (0.5A)

MIN VOLTAGE DROP:~200mV

( from DC up to 10-200Kilohertz)

MIN VOLTAGE DROP:~350mV

1 regulator block 1 regulator block every two channelsevery two channels

ch1ch1

ch2ch2

DC-DC converter

Noise filtering: Ferrite beads + Noise filtering: Ferrite beads + low ESL capacitorslow ESL capacitors

MOTHERBOARDMOTHERBOARD

Main tasks:Main tasks:

Delivers the timing-signals from 8 Daughterboard to the Read out Delivers the timing-signals from 8 Daughterboard to the Read out board.board.

Supply stable voltages to the DaughterboardsSupply stable voltages to the Daughterboards (+5V,-5V,+3.3V)(+5V,-5V,+3.3V)

Combines the 32 multiplicity signals coming out from the Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal.Daughterboard to provide a low level trigger signal.

Allocates DACs for the threshold voltages of the comparators on the Allocates DACs for the threshold voltages of the comparators on the DaugherboardDaugherboard

Minor tasks:Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC Test signals distribution, LVDS repeaters,interface for DAC

programming, etcprogramming, etc

40cm

6cm

MOTHERBOARDMOTHERBOARD

Low level trigger output:Low level trigger output: Two-stage circuitTwo-stage circuit Summing OPAMsSumming OPAMs OPA690OPA690

High slew rateHigh slew rate High output swingHigh output swing

-100mV contribution -100mV contribution

per channelper channel

Rate < 1kHz/cm2 RPC areax100cm2 =100kHz

X31 channels = 3.1 MHz firing

MOTHERBOARDMOTHERBOARD

Main tasks:Main tasks:

Delivers the timing-signals from 8 Daughterboard to the Read out Delivers the timing-signals from 8 Daughterboard to the Read out board.board.

Supply stable voltages to the DaughterboardsSupply stable voltages to the Daughterboards (+5V,-5V,+3.3V)(+5V,-5V,+3.3V)

Combines the 32 multiplicity signals coming out from the Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal.Daughterboard to provide a low level trigger signal.

Allocates DACs for the threshold voltages of the comparators on the Allocates DACs for the threshold voltages of the comparators on the DaugherboardDaugherboard

Minor tasks:Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC Test signals distribution, LVDS repeaters,interface for DAC

programming, etcprogramming, etc

40cm

6cm

MOTHERBOARDMOTHERBOARDDAC thresholdsDAC thresholds Programable by SPIProgramable by SPI 8 DAC 8 DAC

chips/Motherboardchips/Motherboard 8 Channels/DAC chip8 Channels/DAC chip Daisy-chainedDaisy-chained LTC2620 (12 bits LTC2620 (12 bits

resolution)resolution) Feedback for data Feedback for data

transmission error transmission error detectiondetection

Read out board

DO CS CLK

DAC1 DAC2 DAC8

Motherboard

DINDIN

TTL to LVDS TTL to LVDS converterconverter

LVDS to TTL LVDS to TTL convertersconverters

MOTHERBOARDMOTHERBOARD

Main tasks:Main tasks:

Delivers the timing-signals from 8 Daughterboard to the Read out Delivers the timing-signals from 8 Daughterboard to the Read out board.board.

Supply stable voltages to the DaughterboardsSupply stable voltages to the Daughterboards (+5V,-5V,+3.3V)(+5V,-5V,+3.3V)

Combines the 32 multiplicity signals coming out from the Combines the 32 multiplicity signals coming out from the Daughterboard to provide a low level trigger signal.Daughterboard to provide a low level trigger signal.

Allocates DACs for the threshold voltages of the comparators on the Allocates DACs for the threshold voltages of the comparators on the DaugherboardDaugherboard

Minor tasks:Minor tasks: Test signals distribution, LVDS repeaters,interface for DAC Test signals distribution, LVDS repeaters,interface for DAC

programming, etcprogramming, etc

40cm

6cm

TRB

MB DB

To ethernet

RPC cells

ELECTRONICS ELECTRONICS

Read out systemRead out system

Front EndFront End

Board ControllerBoard Controller

FPGAFPGA

LVL2 queueLVL2 queueLVL1 queueLVL1 queue

Custom boardCustom board

Based on the HPTDC Based on the HPTDC ASIC developed at ASIC developed at CERNCERN

128-channel128-channel

READ OUT SYSTEMREAD OUT SYSTEM

GSI (M. Traxler et al.)

TRB (TDC Readout Board):TRB (TDC Readout Board): 4x32 channels 4x32 channels

HPTDCHPTDC 80 pin twisted parir 80 pin twisted parir

cable, KEL connectorcable, KEL connector Single chip computer Single chip computer

with ethernet with ethernet (ETRAX)(ETRAX)

FPGAFPGA DC/DC 48V, isolatedDC/DC 48V, isolated MemoryMemory

HPTDCHPTDC

CPU CPU

Trigger busTrigger bus

HPTDCHPTDC HPTDCHPTDC HPTDCHPTDC

Optional DSP Optional DSP processingprocessing

EthernetEthernet

ToFToFThrThr=15mV=15mV

ToTToTThrThr=-20mV=-20mV

RESULTSRESULTS

Output width vs charge Output width vs charge correlation for gamma correlation for gamma

illumination using illumination using 6060Co sourceCo source

Time of Flight measurements

-<0.5W/channel<0.5W/channel

-Crosstalk<1%Crosstalk<1%

Full chain:Detector+FEE+TRB

Tests with gamma illumination using Tests with gamma illumination using 6060Co source:Co source:

Test with RPC signals under C-C (1.5 GeV) Test with RPC signals under C-C (1.5 GeV) collisionscollisions

80 ps80 ps

77 ps77 ps Crosstalk 2%-6%Crosstalk 2%-6%

Sector prototype with 48 channelsSector prototype with 48 channels

RESULTSRESULTS

OUTLINEOUTLINE INTRODUCTION TO HADES INTRODUCTION TO HADES

EXPERIMENTEXPERIMENT OVERVIEW OF TESTED ELECTRONICSOVERVIEW OF TESTED ELECTRONICS

FRONT-END ELECTRONICSFRONT-END ELECTRONICS DAUGHTERBOARDDAUGHTERBOARD MOTHERBOARDMOTHERBOARD

READ OUT SYSTEMREAD OUT SYSTEM RESULTSRESULTS

CURRENT PROGRESS: NEW CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS DEVELOPED ELECTRONICS

PLAN FOR THE NEXT TESTSPLAN FOR THE NEXT TESTS

IImproved charge measurementmproved charge measurement Used a more gain preamplifierUsed a more gain preamplifier 2nd integration for linearity2nd integration for linearity

Only one comparator Only one comparator 30% power consumption reduction30% power consumption reduction

DAUGHTERBOARDDAUGHTERBOARD

4 ch. out

C

ToT Integrator

Amplifier Step

PECL-LVDS

ToF-Threshold

In

OPA690 Wideband Op. Amplifier

BGM1013 Monolithic(31dB, 2.2GHz)

MAX9601-2ch 500ps Propagation Delay

SN65LVDT100C

Latch enable/

R

2k2 Trigger Out.

Σ4ch.

SAMTEC16 diff. pins

BFT92 Wideband PNP Transistor

Discriminator Step

Q Q/

R

C

2nd integration RC=20ns

Charge comparator removed

Benefits:Benefits: linearity of the charge measurementlinearity of the charge measurement

(by adjusting integration values)(by adjusting integration values) More dynamic rangeMore dynamic range

Linear

Saturation

DAUGHTERBOARDDAUGHTERBOARD

MOTHERBOARDMOTHERBOARD

2 only modifications:2 only modifications: Addition of common mode filters at the power inputAddition of common mode filters at the power input Cooper area at the bottom ground improvementCooper area at the bottom ground improvement

40cm

6cm

32input LVDS 32input LVDS lineslines

READ OUT SYSTEMREAD OUT SYSTEMNew general purpose New general purpose

Readout:Readout: Layout bugs correctedLayout bugs corrected New FPGA (VIRTEX4)New FPGA (VIRTEX4) New DSP (TigerSharc)New DSP (TigerSharc) Detector independent:Detector independent:Also for PANDA & CBMAlso for PANDA & CBM

Add-on board concept:Add-on board concept:32 LVDS input lines 32 LVDS input lines

Front EndFront End

Board ControllerBoard Controller

FPGAFPGA

LVL2 queueLVL2 queueLVL1 queueLVL1 queue

CPU CPU

Optical link Optical link (2Gbit/s)(2Gbit/s)

HPTDCHPTDC HPTDCHPTDC HPTDCHPTDC

Optional DSP Optional DSP processingprocessing

EthernetEthernet

HPTDCHPTDC

OUTLINEOUTLINE INTRODUCTION TO HADES INTRODUCTION TO HADES

EXPERIMENTEXPERIMENT OVERVIEW OF TESTED ELECTRONICSOVERVIEW OF TESTED ELECTRONICS

FRONT-END ELECTRONICSFRONT-END ELECTRONICS DAUGHTERBOARDDAUGHTERBOARD MOTHERBOARDMOTHERBOARD

READ OUT SYSTEMREAD OUT SYSTEM RESULTSRESULTS

CURRENT PROGRESS: NEW CURRENT PROGRESS: NEW DEVELOPED ELECTRONICS DEVELOPED ELECTRONICS

PLAN FOR THE NEXT TESTSPLAN FOR THE NEXT TESTS

PLAN FOR NEXT TESTS PLAN FOR NEXT TESTS FULL SECTOR TESTFULL SECTOR TEST

350 channels350 channels Sector gas box ready.Sector gas box ready. New electronics already New electronics already

developed. Produced:developed. Produced: 12 MB & 4 miniMB12 MB & 4 miniMB 108 DB108 DB 4 TRB (Read out)4 TRB (Read out)

Currently being Currently being assembledassembledGas box wiew without front cover Gas box wiew without front cover

Thanks for your Thanks for your attentionattention