Programmable Data Plane at Terabit Speeds

Copyright © 2016 - Barefoot Networks

Programmable Data Plane at Terabit Speeds

Vladimir Gurevich


The Three Planes

• Independent software components◦ Implement different classes of

algorithms◦ Have different design requirements◦ Are designed using different

methodologies◦ Are Implemented using different

languages■ Or different hardware

◦ Run Independently◦ Communicate through well-defined

interfaces

2

Management PlaneConfiguration CLI/GUI/SNMP...

Control PlaneProtocol Stacks Port

Mgmt

Platform Mgmt

OSPF

STPIS-IS

PIM-SM

BGP

Data PlanePacket Forwarding


Switch OS

Run-time APIDriver

“This is how I know toprocess packets”

(i.e. the ASIC datasheetmakes the rules)

Fixed-function ASIC

Bottoms-up network element design

Network Demands

3


Switch OS

Run-time APIDriver

“This is how I want the network to behave and how to

switch packets…”(the user / controller

makes the rules)Barefoot Tofino + P4

Top-down network element design

Network Demands

P4

Feedback

4


Fixed Function Switches

SwitchOS

StaticRun-timeAPIDriver

Fixed Meta-Data

Traffic Manager

Fixed Parser

Fixe

d Lo

okup

s

Fixed Memories

Fixe

d Ac

tions

Fixe

d Lo

okup

s

Fixed Memories

Fixe

d Ac

tions

Fixe

d Lo

okup

s

Fixed Memories

Fixe

d Ac

tions

Fixe

d Lo

okup

s

Fixed Memories

Fixe

d Ac

tions

Fixed Packet Mods

Fixed Function ASIC

5


Programmable Switch Approach

Fixed Meta-Data

Traffic Manag

er

Fixed Parser

Fixe

d Lo

oku

ps

Fixed Memories

Fixe

d Lo

oku

ps

Fixe

d Lo

oku

ps

Fixed Memories

Fixe

d Lo

oku

ps

Fixe

d Lo

oku

ps

Fixed Memories

Fixe

d Lo

oku

ps

Fixe

d Lo

oku

ps

Fixed Memories

Fixe

d Lo

oku

ps Fixed Packe

t Mods

Programmable Meta-Data

Traffic Manager

Prog

ram

mab

lePa

rser Fl

exib

le

Look

ups

SharedMemories

Cus

tom

Actio

ns

Flex

ible

Look

ups

SharedMemories

Cus

tom

Actio

ns

Flex

ible

Lo

okup

s

SharedMemories

Cus

tom

Actio

ns

Flex

ible

Look

ups

SharedMemories

Cus

tom

Actio

ns

DeP

arse

r

Programmable ASIC

switch.p4

ProtocolAuthoring

1

Compile2

Configure3

AutoGeneratedRun-timeAPI

6


Result: Customer Defined Switch

SwitchOS

Driver

User Defined Meta-Data

Traffic ManagerU

ser

Def

ined

Pars

er Use

r D

efin

edLo

okup

s

User DefinedTables

Use

r D

efin

edAc

tions

Use

r D

efin

ed

Look

ups

User Defined Tables

Use

r D

efin

edAc

tions

Use

r D

efin

edLo

okup

s

User DefinedTables

Use

r D

efin

edAc

tions

Use

r D

efin

ed

Look

ups

User Defined Tables

Use

r D

efin

ed

Actio

ns

Use

r D

efin

ed

DeP

arse

r

Programmable ASIC : User Defined Forwarding Plane

Run!4

Add/deletetablerulesAutoGeneratedRun-timeAPI

7


Match-Action Packet Processing Concept

8

Prog

ram

mab

lePa

rser

MatchMemory

ActionALU

Copyright © 2016 - Barefoot Networks 9

Prog

ram

mab

lePa

rser

PISA: Protocol Independent Switch Architecture

Ingress EgressBuffer

Copyright © 2016 - Barefoot Networks 10

Prog

ram

mab

lePa

rser

PISA: Protocol Independent Switch ArchitectureMix of SRAM and TCAM for: lookup tables, counters, meters, Bloom filters ALUs for: Standard Boolean and Arithmetic

Operations & add/delete fields, hashes

Recirculation

ProgrammablePacketGenerator


What Happens Inside?

Queues

Prog

ram

mab

lePa

rser

CLK

… … … …

Match Table (SRAM or TCAM)

Cross Bar

PHV(Packet Header Vector) PHV’

action

11


P4 Visualizations (PHV Allocation)

12


P4 Visualizations (Resource Allocation)

13


P4 Visualizations (Resource Usage Summary)

14


Tofino Block Diagram

Rx MACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

Control & Configuration

Reset / Clocks PCIe CPU

MACDMA

engines

Rx MACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

Rx MACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

Rx MACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

Traffic Manager

EgressPipeline

EgressPipeline

EgressPipeline

EgressPipeline


Barefoot SDE

16

Tofino:Best-in-class P4 Targets

Chip Driver

Protocol-independent API

Your Auto-generated API

Your P4 Program

Your Control-plane Program (Apps)

ASICModel

BarefootCompiler

& Dev. Tools

Add/delete table rulesat run time

Behavioral Model


Reference P4 Program + Your

Custom Features

BarefootCompiler

& Dev. Tools

Barefoot SDE

17

Tofino:Best-in-class P4 Targets

Chip Driver

Protocol-independent API

Your Auto-generated API

Your Control-plane Program (Apps)

ASIC Model

Behavioral Model

SwitchAPI

OCP SAI (Switch Abstraction Interface) Open

source

Packet Test Framew

ork


switch.p4 & switchAPI Features

18

TCP New

IPv4 IPv6

VLANEth

Parser IngressMatch+Action EgressMatch+ActionQueues

switch.p4SwitchOS

Run-timeAPIAuto-generate

Add/deletetablerules

Driver

ProtocolAuthoring

1

Compile2

Configure3

Run!4

IPv4 and IPv6 routing- Unicast- Unicast RPF

- Strict and Loose- Multicast

- PIM-SM/DM & PIM-BiDir

L2 switching- Learning- STP state- VLAN Translation

Load balancing- WECMP, ECMP and LAG- Resilient Hashing

Tunneling- IPv4 & IPv6 Routing & Switching- IP-in-IP (6in4, 4in4)- VXLAN, NVGRE, GENEVE & GRE

MPLS- LER - LSR- IPv4/v6 routing (L3VPN)- L2 switching (EoMPLS, VPLS)

ACL- MAC ACL,- IPv4/v6 ACL/RACL,- QoS ACL- System ACL- PBR (Policy based routing)

NAT

QOS- QoS Classification & marking- Drop profiles/WRED- RoCE v2 & FCoE- CoPP (Control plane policing)

Security Features- Storm Control, IP Source Guard

Mirroring- Ingress Mirroring and Egress Mirroring- Negative Mirroring

Counters- Route Table Entry Counters- VLAN/Bridge Domain Counters- Port/Interface Counters

Protocol Offload- BFD, OAM

Multi-chip Fabric Support- Forwarding, QOS


Thank you

Programmable Data Plane at Terabit Speeds

Technology

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