PRODUCT / PROCESS CHANGE NOTIFICATION 1. PCN basic data · 2020. 2. 10. · PRODUCT / PROCESS...

PRODUCT / PROCESS CHANGE NOTIFICATION

1. PCN basic data

1.1 Company STMicroelectronics International N.V

1.2 PCN No. MDG/20/11944

1.3 Title of PCN STM32MP15x product improvement - listed products

1.4 Product Category STM32MP151x, STM32MP153x STM32MP157x

1.5 Issue date 2020-02-07

2. PCN Team

2.1 Contact supplier

2.1.1 Name ROBERTSON HEATHER

2.1.2 Phone +1 8475853058

2.1.3 Email [email protected]

2.2 Change responsibility

2.2.1 Product Manager Ricardo Antonio DE SA EARP

2.1.2 Marketing Manager Veronique BARLATIER

2.1.3 Quality Manager Pascal NARCHE

3. Change

3.1 Category 3.2 Type of change 3.3 Manufacturing Location

General Product & Design Die redesign : Mask or mask set change withnew die design like metallization (specificallychip frontside) or bug fix

Crolles

4. Description of change

Old New

4.1 Description Revision B (cut 2.0)Limitations as described in Errata SheetES0438 Revision 3 - November 2019“STM32MP151x STM32MP153x STM32MP157x” Summary of Device errata

New Revision Z (cut 2.1):New Errata sheet ES0438 Revision 4 - January2020“STM32MP151x STM32MP153x STM32MP157x” Summary of Device errata

4.2 Anticipated Impact on form,fit,function, quality, reliability orprocessability?

Function will change only

5. Reason / motivation for change

5.1 Motivation Correct some product functionality limitations

5.2 Customer Benefit QUALITY IMPROVEMENT

6. Marking of parts / traceability of change

6.1 Description Traceability of the change is ensured by ST internal tools.

7. Timing / schedule

7.1 Date of qualification results 2020-01-30

7.2 Intended start of delivery 2020-03-09

7.3 Qualification sample available? Upon Request

8. Qualification / Validation

8.1 Description 11944 MDG-MCD-RER1902 V2.0 - STM32MP15x - Die 500XXXZ - Reliability evaluation report.pdf

8.2 Qualification report andqualification results

Available (see attachment) IssueDate

2020-02-07

9. Attachments (additional documentations)

11944 Public product.pdf11944 MDG-MCD-RER1902 V2.0 - STM32MP15x - Die 500XXXZ - Reliability evaluation report.pdf

10. Affected parts

10. 1 Current 10.2 New (if applicable)

10.1.1 Customer Part No 10.1.2 Supplier Part No 10.1.2 Supplier Part No

STM32MP151AAB3

STM32MP151AAC3

STM32MP151AAD3

STM32MP151CAB3

STM32MP151CAC3

STM32MP151CAD3

STM32MP153AAB3

STM32MP153AAC3

STM32MP153AAD3

STM32MP153CAB3

STM32MP153CAC3

STM32MP153CAD3

STM32MP157AAB3

STM32MP157AAC3

STM32MP157AAD3

STM32MP157CAB3

STM32MP157CAC3

STM32MP157CAD3

IMPORTANT NOTICE – PLEASE READ CAREFULLY

Subject to any contractual arrangement in force with you or to any industry standard implemented by us, STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2018 STMicroelectronics – All rights reserved

Public Products List

Publict Products are off the shelf products. They are not dedicated to specific customers, they are available through ST Sales team,

or Distributors, and visible on ST.com

PCN Title : STM32MP15x product improvement - listed products

PCN Reference : MDG/20/11944

Subject : Public Products List

Dear Customer,

Please find below the Standard Public Products List impacted by the change.

STM32MP153CAC3T STM32MP157AAB3 STM32MP151CAD3

STM32MP153CAD3 STM32MP153AAC3 STM32MP153CAB3T

STM32MP157CAC3T STM32MP157CAB3 STM32MP153CAB3

STM32MP157CAD3T STM32MP151AAB3T STM32MP157AAD3

STM32MP157AAD3T STM32MP151CAB3 STM32MP151AAD3T

STM32MP151CAB3T STM32MP157CAC3 STM32MP157AAC3

STM32MP157CAB3T STM32MP153AAD3T STM32MP157CAD3

STM32MP151CAC3 STM32MP153AAB3 STM32MP153AAB3T

STM32MP151AAB3 STM32MP153CAD3T STM32MP151CAD3T

STM32MP153CAC3 STM32MP151AAC3T STM32MP153AAC3T

STM32MP153AAD3 STM32MP157AAC3T STM32MP151CAC3T

STM32MP151AAD3 STM32MP151AAC3 STM32MP157AAB3T

Public Products List

IMPORTANT NOTICE – PLEASE READ CAREFULLY

Subject to any contractual arrangement in force with you or to any industry standard implemented by us, STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2018 STMicroelectronics – All rights reserved

Quality & Reliability –MDG-MCD.

STM32MP15x – Reliability Evaluation Report.

RER Identification Number: MDG-MCD-RER1902 Page 1/17

Reliability Evaluation Report

MDG-MCD-RER1902

STM32MP15x (500x66)

Reliability Evaluation Purpose (New Product Qualification)

General Information Traceability

Commercial Product

STM32MP151x / 153x / 157x

Diffusion Plant ST CROLLES 300,

FRANCE.

Product Line 500X66

Assembly Plant AMKOR ATK4, KOREA.

Die revision 500XXXZ (Cut2.1)

Product Description STM32MP15x family

Package

LFBGA 18x18 448L ATK4

LFBGA 16x16 354L ATK4

TFBGA 12x12 361L ATK4

TFBGA 10x10 257L ATK4

Reliability Assessment

Silicon Technology

ST C12” CMOS040

Pass ☒

Division MDG-MCD

Fail ☐

Reliability Maturity

Level 30

Investigation

required ☐

Note: this report is a summary of the reliability trials performed in good faith by STMicroelectronics in

order to evaluate the electronic device conformance to its specific mission profile. This report and its

contents shall not be disclosed to a third party without previous written agreement from STMicroelectronics

or under the approval of the author (see below).

Version Date Author Function

2.0 9th Jan. 2020 Celine NAVARRO

Moses TAN MDG-MCD-Q&R Engineer

APPROVED BY:

Function Location Name Date

Division Q&R Manager Grenoble Dominique GALIANO 9th Jan. 2020




TABLE OF CONTENTS

1 RELIABILITY EVALUATION OVERVIEW ............................................................................................................ 3

OBJECTIVE .................................................................................................................................................. 3

RELIABILITY STRATEGY ................................................................................................................................. 3

CONCLUSION .............................................................................................................................................. 4

2 PRODUCT OR TEST VEHICLE CHARACTERISTICS .......................................................................................... 5

GENERALITIES.............................................................................................................................................. 5

TRACEABILITY ............................................................................................................................................. 5

2.2.1 Wafer fab information ................................................................................................................ 5

2.2.2 Assembly information ................................................................................................................ 6

2.2.3 Reliability testing information .................................................................................................. 8

3 TESTS RESULTS SUMMARY .............................................................................................................................. 8

LOT INFORMATION ...................................................................................................................................... 8

TEST PLAN AND RESULTS SUMMARY ............................................................................................................. 10

4 APPLICABLE AND REFERENCE DOCUMENTS ................................................................................................ 15

5 GLOSSARY ....................................................................................................................................................... 16

6 REVISION HISTORY ......................................................................................................................................... 16




1 RELIABILITY EVALUATION OVERVIEW

Objective

The aim of this report is to present results of the reliability evaluation performed on

STM32MP151x/153x/157x - Die 500XXXZ.

Test vehicle is described here below:

Qualification is based on standard STMicroelectronics Corporate Procedures for Quality and

Reliability, in full compliancy with the JESD-47 international standard

Reliability Strategy

The STM32MP151x / 153x / 157x – Die 500XXZ, is processed in the CMOS040 process from ST

C12” CROLLES 300 plant and considered as a new process for our division.

All the packages, used for this product family, has not been qualified previously for other products

from our division

According to “RELIABILITY TESTS AND CRITERIA FOR QUALIFICATION” specification (DMS 0061692),

the following qualification strategy has been defined:

• Die Qualification:

Full reliability exercise on 2 diffusion lots for Cut1.0

Full reliability exercise on 1 diffusion lot for Cut2.0

Full reliability exercise on 1 diffusion lot for Cut2.1

• Package Qualification:

The reliability test plan and result summary are presented in the following tables:

Package Body Pitch Package

Code Wire Assy

Bounding

Option Trial

LFBGA 448L 18x18 0.8 B032 Gold ATK4 Legacy 3 assembly lots.

TFBGA 361L 12x12 0.5/0.65 B031 Gold ATK4 Legacy 3 assembly lots.

LFBGA 354L 16x16 0.8 B02Z Gold ATK4 Legacy 1 assembly lot.

TFBGA 257L 10x10 0.5/0.65 B02Y Gold ATK4 Legacy 1 assembly lot.

Product Process / Package Diffusion / Assembly plant

STM32MP157CAA3 CMOS040, LFBGA 18x18 448L ST C12” , SC AMKOR ATK4

STM32MP157AAC3 CMOS040, TFBGA 12x12 361L ST C12” , SC AMKOR ATK4

STM32MP157AAB3 CMOS040, LFBGA 16x16 354L ST C12” , SC AMKOR ATK4

STM32MP157AAD3 CMOS040, TFBGA 10x10 257L ST C12” , SC AMKOR ATK4




Conclusion

All reliability tests have been completed with positive results. Neither functional nor parametric

rejects were detected at final electrical testing.

According to good reliability tests results in line with validated product mission profile and reliability

strategy, the qualification is granted for the STM32MP151x / 153x /157x - Die 500XXXZ in all

packages listed in the Chapter 1.2.

Refer to Section 3.0 for reliability test results.




2 PRODUCT OR TEST VEHICLE CHARACTERISTICS

Generalities

STM32MP15x product is based on ARM Cortex®-A7 core and ARM Cortex®-M4 core in C40nm

technology. It provides a standard peripheral set compatible with STM32H7x (M40nm) with the

addition of a 3D GPU, DRAM memory controller and supports high level operating system like Linux,

Android or Windows. It is using external flash, larger and faster external memory, with embedded

two port USB High-Speed PHY, GPU for 3D capabilities, security with Trust Zone which is system

security by ARM.

For additional information concerning the product behavior, refer to STM32MP15x datasheets.

Traceability

2.2.1 Wafer fab information

Table 1

Wafer fab information

FAB1

Wafer fab name / location ST C12” CROLLES 300 / FRANCE

Wafer diameter (inches) 12

Wafer thickness (µm) 775 +/- 25

Silicon process technology CMOS040

Number of masks 39

Die finishing front side (passivation)

materials/thicknesses (µm) PSG + NITRIDE, 1.1

Die area (Stepping die size) (µm) 5200, 5043

Die pad size (X,Y) (µm) 41.4, 90

Sawing street width (X,Y) (µm) 72, 72

Metal levels/Materials/Thicknesses (µm) Metal 1 Cu 0.130 / Metal 2 Cu 0.140 / Metal 3 Cu 0.140 Metal 4 Cu 0.140 / Metal 5 Cu 0.140 / Metal 6 Cu 0.900 Metal 7 Cu 0.900 / Metal 8 Ta/TaN/AlCu 2.880

Die over coating (material/thickness) No

FIT level (Ea=0.7eV, C.L: 60%, 55°C) 2 FITs

Soft Error Rate - Alpha SER [FIT/Mb]

- Neutron SER [FIT/Mb]

- Conditions

Alpha SER: 357 FIT/Mb Neutron SER: 288 FIT/Mb Neutron SER is an estimation at sea level of NYC (13n/h/cm²). Alpha result is estimated using a nominal flux of 0.001α/h/cm²

Wafer Level Reliability

- Electro-Migration (EM)

- Time Dependent Dielectric Breakdown (TDDB)

or Gate Oxide Integrity (GOI)

- Hot Carrier Injection (HCI)

- Negative Bias Thermal Instability (NBTI)

- Stress Migration (SM)

Yes

Other Device(s) using same process No




2.2.2 Assembly information

Table 2

Assembly Information

Package 1 – LFBGA18x18x1.27 448L B032

Assembly plant name / location AMKOR ATK4, KOREA

Pitch (mm) 0.8

Die thickness after back-grinding (µm) 102 +/- 10

Die sawing method Laser Grooving

Bill of Material elements

Substrate material/supplier/reference LFBGA18x18x1.2 448L SID #101400639 / KCC /

101400639

Die attach material/type(glue/film)/supplier Glue Ablestick 2025D

Wire bonding material/diameter/supplier 0.7 mil 2N gold wire / HEE SENG

Balls metallurgy/diameter/supplier (BGA/CSP) SACN305 0.4 mm DIA /Duksan

Molding compound material/supplier/reference GE110LL 6.7 / Hitachi / 101377954

Package Moisture Sensitivity Level

(JEDEC J-STD020D) MSL 3

Package 2 – TFBGA 12x12x1.2 361 B031

Assembly plant name / location AMKOR ATK4, KOREA.

Pitch (mm) 0.5/0.65




Substrate material/supplier/reference TFBGA12x12x1.1 361L SID #101400638 / UMTC /

101400638



Balls metallurgy/diameter/supplier (BGA/CSP) SACN12505 0.3 mm DIA. / Duksan.







Package 3 – LFBGA 16x16x1.5 354 B02Z


Pitch (mm) 0.8

Die thickness after back-grinding (µm) 102 +/-10



Substrate material/supplier/reference LFBGA16x16x1.27 354L SID #101404168 / KCC /

101404168



Balls metallurgy/diameter/supplier (BGA/CSP) SACN305 0.4 mm DIA / Duksan.




Package 4 – TFBGA 10x10x1.2 257 B02Y


Pitch (mm) 0.5/0.65




Substrate material/supplier/reference TFBGA10x10x1.1 257L SID #101404219 / UMTC /

101404219



Balls metallurgy/diameter/supplier (BGA/CSP) SACN12505 0.3 mm DIA. / MKE.







2.2.3 Reliability testing information

Table 3

Reliability Testing Information

Reliability laboratory name / location ST GRAL in Grenoble

Note: ST is ISO 9001 certified. This induces certification of all internal and subcontractor labs.

ST certification document can be downloaded under the following link:

http://www.st.com/content/st_com/en/support/quality-and-reliability/certifications.html

3 TESTS RESULTS SUMMARY

Lot Information

Table 4

Lot # Diffusion Lot

/ Wafer ID

Die

Revision

(Cut)

Assy Lot /

Trace Code Raw Line Package Note

1 Q738074

Wafer#19 1.0 HP813ABD X2GU*500XXXA

LFBGA

18x18

448L

Die Reliability

assessment.

2 Q726451

Wafer#07 1.0 HP812ABP X2GU*500XXXA

LFBGA

18x18

448L

Die Reliability

assessment.

3 Q830384

Wafer#11 2.0 HP843ADC O2GU*500ESXB

LFBGA

18x18

448L

Die Reliability

assessment.

4 Q835409

Wafer#23 2.0 HP850ACB O2GU*500ESXB

LFBGA

18x18

448L

Die Reliability

assessment.

5 Q848286

Wafer#16 2.1 HP938ALU O1GU*500ESXZ

LFBGA

18x18

448L

Die Reliability

assessment.

6 Q745403

Wafer#02 1.0 HP835ADH O2GU*500ESXA

LFBGA

18x18

448L

Package

Reliability

assessment.

7 Q835403


LFBGA

18x18

448L

Package

Reliability

assessment.

8 Q835403


LFBGA

18x18

448L

Package

Reliability

assessment.




9 Q745403

Wafer#09 1.0 HP836ABL O1GR*500ESXA

TFBGA

12x12

361

Package

Reliability

assessment.

10 Q745403


TFBGA

12x12

361

Package

Reliability

assessment.

11 Q745403


TFBGA

12x12

361

Package

Reliability

assessment.

12 Q745403

Wafer#07 1.0 HP836ABL O2GO*500ESXA

LFBGA

16x16

354

Package

Reliability

assessment.

13 Q745403

Wafer#07 1.0 HP837ABM O2GJ*500ESXA

TFBGA

10x10

257

Package

Reliability

assessment.

14 Q830384

Wafer#12 2.0 HP846ADY O1GR*500ESXB

TFBGA

12x12

361

Package

Reliability

assessment.

15 Q830384

Wafer#07 2.0 HP850ACA O2GO*500ESXB

LFBGA

16x16

354

Package

Reliability

assessment.

16 Q830384

Wafer#11 2.0 HP846ADW O2GJ*500ESXB

TFBGA

10x10

257

Package

Reliability

assessment.

Note:

• Lot 4 defined for Early Failure Rate (ELFR) exercise.




Test plan and results summary

Table 5 – ACCELERATED LIFETIME SIMULATION TESTS

HTOL JESD22 A108 Ta=125°C

Duration= 1200H

Vcore :1V28

Vdd : 3V6

3 77 231 Lot1: 0/77

Lot2: 0/77

Lot3: 0/77

Ta=125°C

Duration= 1200H

Vcore :1V38

Vdd : 3V6

3 77 231 Lot1: 0/77

Lot4: 0/77

Lot5: 0/77

ESD HBM ANSI/ESDA/

JEDEC JS-001

1500 Ω, 100 pF

2kV class2

3 3 9 Lot1: 0/3

Lot2: 0/3

Lot3: 0/3

Lot5: 0/3

ESD CDM ANSI/ESDA/

JEDEC JS-002

250V 7 3 21 Lot1: 0/3

Lot2: 0/3

Lot3: 0/3

Lot5: 0/3

Lot14: 0/3

Lot15: 0/3

Lot16: 0/3

Latch Up JESD78 130°C 4 3 12 Lot1: 0/3

Lot2: 0/3

Lot3: 0/3

Lot5: 0/3

ELFR JESD22-A108

JESD74

Ta=125°C

Duration= 48hrs

Vcore :1V28

Vdd : 3V6

3 800 2400 Lot1: 0/800

Lot2: 0/800

Lot4: 0/800

Test code Stress

method Stress Conditions Lots S.S. Total Results/Lot

Fail/S.S.

Comments:

(N/A =Not Applicable)




Table 6 – ACCELERATED ENVIRONMENT STRESS TESTS

For LFBGA 18x18

PC J-STD-020 24h bake@125°C,

MSL3 (192h@30C/60%RH)

3x Reflow simulation

Peak Reflow Temp= 260°C

3

231 693 Lot6: 0/231

Lot7: 0/231

Lot8: 0/231

TC JESD22-A104 Ta=-65/150°C

Duration= 500cyc

☒ After PC

3 77 231 Lot 6: 0/77

Lot 7: 0/77

Lot 8: 0/77

HTSL JESD 22-A103 Ta=150°C ,

Duration= 1000hrs

☒ After PC

3 77 231 Lot 6: 0/77

Lot 7: 0/77

Lot 8: 0/77

THB JESD 22-A101 Ta=85°C/85%RH

VDD=3v6

Duration= 1000hrs

☒ After PC

3 77 231 Lot 6: 0/77

Lot 7: 0/77

Lot 8: 0/77

ESD

CDM

ANSI/ESDA/

JEDEC JS-002

250V 4 3 12 Lot1: 0/3

Lot2: 0/3

Lot3: 0/3

Lot5: 0/3

Note: Test method revision reference is the one active at the date of reliability trial execution

Test

code Stress method Stress Conditions Lots S.S. Total Results/Lot

Fail/S.S.

Comments:





For TFBGA 12x12


MSL3 (192h@30C/60%RH)



3

231 693 Lot 9: 0/231

Lot 10: 0/231

Lot 11: 0/231

TC JESD22-A104 Ta=-65/150°C

Duration= 500cyc

☒ After PC

3 77 231 Lot 9: 0/77

Lot 10: 0/77

Lot 11: 0/77


Duration= 1000hrs

☒ After PC

3 77 231 Lot 9: 0/77

Lot 10: 0/77

Lot 11: 0/77


VDD=3v6

Duration= 1000hrs

☒ After PC

3 77 231 Lot 9: 0/77

Lot 10: 0/77

Lot 11: 0/77

ESD

CDM

ANSI/ESDA/

JEDEC JS-002

250V 2 3 6 Lot9: 0/3

Lot14: 0/3

Note: Test method revision reference is the one active at the date of reliability trial execution

Test


Fail/S.S.

Comments:





For TFBGA 10x10


MSL3 (192h@30C/60%RH)



1

231 231 Lot 13: 0/231

TC JESD22-A104 Ta=-65/150°C

Duration= 500cyc

☒ After PC

1

231 231 Lot 13: 0/231


Duration= 1000hrs

☒ After PC

1

231 231 Lot 13: 0/231


VDD=3v6

Duration= 1000hrs

☒ After PC

1

231 231 Lot 13: 0/231

ESD

CDM

ANSI/ESDA/

JEDEC JS-002

250V 2 3 6 Lot13: 0/3

Lot16: 0/3

Test


Fail/S.S.

Comments:





For LFBGA 16x16


MSL3 (192h@30C/60%RH)



1

231 231 Lot 12: 0/231

TC JESD22-A104 Ta=-65/150°C

Duration= 500cyc

☒ After PC

1

231 231 Lot 12: 0/231


Duration= 1000hrs

☒ After PC

1

231 231 Lot 12: 0/231


VDD=3v6

Duration= 1000hrs

☒ After PC

1

231 231 Lot 12: 0/231

ESD

CDM

ANSI/ESDA/

JEDEC JS-002

250V 2 3 6 Lot12: 0/3

Lot15: 0/3

Table 8 – PACKAGE ASSEMBLY INTEGRITY TESTS

CA

Construction

Analysis including

-Wire bond shear

-Wire bond pull

-Solderability

JESD 22B102

JESDB100/

B108

8 50 400

Lot6: 0/50

Lot7: 0/50

Lot8: 0/50

Lot9: 0/50

Lot10: 0/50

Lot11: 0/50

Lot12: 0/50

Lot13: 0/50

Test


Fail/S.S.

Comments:


Test

code Method Tests Conditions Lots S.S. Total Results/Lot

Fail/S.S.

Comments:





4 APPLICABLE AND REFERENCE DOCUMENTS

Reference Short description

JESD47 Stress-Test-Driven Qualification of Integrated Circuits

SOP2.4.4 Record Management Procedure

SOP2.6.2 Internal Change Management

SOP2.6.7 Finished Good Maturity Management

SOP2.6.9 Package & Process Maturity Management in BE

SOP2.6.11 Program Management for Product Development

SOP2.6.17 Management of Manufacturing Transfers

SOP2.6.19 Front-End Technology Platform Development and Qualification

DMS 0061692 Reliability Tests and Criteria for Product Qualification

ANSI/ESDA

JEDEC JS-001 Electrostatic discharge (ESD) sensitivity testing human body model (HBM)

ANSI/ESDA

JEDEC JS-002 Electrostatic discharge (ESD) sensitivity testing charge device model (CDM)

JESD78 IC Latch-up test

JESD 22-A108 Temperature, Bias and Operating Life

JESD 22-A103 High Temperature Storage Life

J-STD-020: Moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices

JESD22-A113: Preconditioning of non-hermetic surface mount devices prior to reliability testing

JESD22-A118: Unbiased Highly Accelerated temperature & humidity Stress Test

JESD22-A104: Temperature cycling

JESD22-A110: Temperature Humidity Bake

JESD 22B102: Solderability test

JESD22B100/B108: Physical dimension




5 GLOSSARY

Reference Short description

HTOL High Temperature Operating Life

EDR Endurance and Data Retention

ELFR Early Failure Rate

PC Preconditioning (solder simulation)

THB Temperature Humidity Bias

TC Temperature cycling

uHAST Unbiased Highly Accelerated Stress Test

HAST Highly Accelerated Stress Test

HTSL High temperature storage life

DMS ST Advanced Documentation Controlled system/ Documentation Management system

ESD HBM Electrostatic discharge (human body model)

ESD CDM Electrostatic discharge (charge device model)

LU Latch-up

CA Construction Analysis

6 REVISION HISTORY

Revision Author Content

description

Approval List

Function Location Name Date

1.0 Celine NAVARRO

Moses TAN

Initial

Release

Div. Quality Manager Rousset Pascal NARCHE 27th Feb. 2019

Division Back-End

Quality Manager Rousset Gisele SEUBE 27th Feb. 2109

Q&R Quality Manager Grenoble Dominique GALIANO 11th Feb. 2019

Rousset Frederic BRAVARD 11th Feb. 2019

2.0 Moses TAN

Updated with

results on

CUT 2.1

Q&R Quality Manager Grenoble Dominique GALIANO 9th Jan. 2020




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Disclosure of this document to any non-authorized party must be previously authorized by ST only under the

provision of a signed NDA between ST and Customer and must be treat as strictly confidential.

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its

subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this

document, and the products and services described herein at any time, without notice.

Information in this document is intended as support for authorized communication between ST and Customer

only, for internal discussions purposes.

In no event the information disclosed by ST to Customer hereunder can be used against ST, or in a claim

brought in front of any Court or Jurisdiction.

At all times you will comply with the following securities rules:

• Do not copy or reproduce all or part of this document

• Keep this document locked away

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no

responsibility for the consequences of use of such information nor for any infringement of patents or other

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PRODUCT / PROCESS CHANGE NOTIFICATION 1. PCN basic data · 2020. 2. 10. · PRODUCT / PROCESS...

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