Process Control during Wafer Design and Production.
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Process Control during Wafer Design and Production CONCEPT LO GIC D ESIG N A N A LYSIS AS IC LAYOUT TEST VECTOR GENERATION D O C U M EN TA TIO N , M A N U FAC TU R IN G IN TER FA C E S ASIC PROTOTYPE FABR IC ATIO N ASIC PROTOTYPE VER IFIC ATIO N ASIC PR O D U CTIO N -H igh level descriptive language (H DL)/VH DL -FunctionalM odel -Libraries,Softw are (S/W ), H ardware (H /W ) -Topological Analysis -Electrical R ule C heck (ERC ) -D esign R ule C heck (D RC) -Testability A nalysis -D esign-for-Test -Built-in S elfTest(BIST) -Logic S im -FaultGrading -FaultGrading -Tim ing Ver. -C ircuitAnalysis -H ardware Accelerators -H ardw are P arts Sim -Autoplace & Route ATE TEST TAPE GENERATION -FaultSim -FaultGrading -TVG (M anual/ Automatic) -Softw are V erification -TestP rogram installation on ATE Resimulate R AD IATIO N TE STIN G FO R EACH LO T S H IP TO PLASTIC E ncapsulated M icrocircuit MANUFACTURER
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Transcript of Process Control during Wafer Design and Production.
Process Control during Wafer Design and Production
CONCEPTLOGIC
DESIGNANALYSIS
ASICLAYOUT
TESTVECTOR
GENERATION
DOCUMENTATION,MANUFACTURING
INTERFACES
ASICPROTOTYPE
FABRICATION
ASICPROTOTYPE
VERIFICATION
ASICPRODUCTION
- High leveldescriptive language(HDL)/VHDL- Functional Model
- Libraries, Software (S/W),Hardware (H/W)- Topological Analysis- Electrical Rule Check (ERC)- Design Rule Check (DRC)- Testability Analysis- Design-for-Test- Built-in Self Test (BIST)
- Logic Sim- Fault Grading- Fault Grading- Timing Ver.- Circuit Analysis- HardwareAccelerators- Hardware PartsSim
- Autoplace &Route
ATE TESTTAPE
GENERATION
- Fault Sim- Fault Grading- TVG (Manual /Automatic)
- Software Verification- Test Programinstallation on ATE
Resimulate
RADIATIONTESTING FOR
EACH LOT
SHIP TO PLASTICEncapsulatedMicrocircuit
MANUFACTURER
The development and implementation of the Reliability Rule Checker tools stating from the basic process technology assessment through automated tool.
TECHNOLOGYCHARACTER
LIBRARY
CELLCHECK
CHIPCHECK
SIMULATIONS(SPACE)
REGRESIONFITs
DC DESIGNRULES
SOASPEC
'FRIENDLY'DESIGN RULES
DESIGNEXPERIENCE
AC DEISNGRULES
DESIGNRELIABILITYEXTRACTOR
ELECTROMIG.CHECKER
POWERDENSITY
CHECKER
HOT-CARRIERCHECKER
LATCH-UPCHECKER
ASIC Part Evaluation (1 of 2)
ASICDesign
Vendor Selection Dominated
by Analog Design
Transfer of ASICDesign Files (GDS)
to Vendor
ASIC Fabrication (Wafers)
Package PEMparts
Characterize Packaged parts as
per PEM flow
Evaluate and Survey Packaging Part
Supplier
Test vectors over specified Temp. and
Voltage extremes
ElectricalCharacterization
Performance Tests
Specification and Data Verification
DPA(Sample Only)
ASIC Part Evaluation (2 of 2)
Package Flight Parts
as per SCD
Qualify Flight Packaged Parts as per modified PEM
test flow (samples only)
Evaluation and Selection of a
Screening Supplier
100% Screen all parts, using test
vectors. Perform functional test, etc
Failure may require
failure analysis
Parts to the Controlled
Storage
Modify design if required and repeat
previous steps
QUALIFICATION OF PLASTIC ENCAPSULATED MICROCIRCUITS (1 of 2)
Receiving Inspection
Review Suppliers’ Qualification
and Reliability Data
SupplierSelection
Review Performance
History
Review Reliability
Monitoring Details
Statistical Process Control (SPC)
Procure Parts
Visual Inspection
ScanningAcoustic
Microscopy
Destructive Physical Analysis
(DPA)
Review Data
Pre-Conditioning (5 pieces max.)
SMD to be machine soldered
Temp.Cycling 20 cycles
ScanningAcoustic
MicroscopyBake-out
16 hrs
ScanningAcoustic
Microscopy
Moisture Soak85C /
85% RH
Reflow Phase
220C, 1 Pass
Pre-Conditioning Sequence
FinalVisual
Examination
PLASTIC ENCAPSULATED MICROCIRCUITS (2 of 2)
ScanningAcoustic
Microscopy
Destructive Physical Analysis, Sample
Temperature Cycling, (100%),
883, Method 1010, 10 Cycles
Initial Electrical
883, Method 5005, Subgroup 2
Burn-In72 / 160 hrs.
max.
InterimElectrical
883, Method 5005,Subgroup 1
Calculate Percentage Defects Allowable (PDA)
10%
FinalElectrical
883, Method 5005,Subgroups 2 - 7
Scanning Acoustic
MicroscopyExternalVisual
