PowerPC (RISC) Architecture Michael McCarthy Scott Watson Jason Wollenberg.
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Transcript of PowerPC (RISC) Architecture Michael McCarthy Scott Watson Jason Wollenberg.
PowerPC (RISC) Architecture
Michael McCarthy
Scott Watson
Jason Wollenberg
PowerPC Evolution
601
(32-bit)
603
(32-bit)
604
(32-bit)
740/750
(64-bit)
G4
(64-bit)
G4 rev.3
(64-bit)
Ship Date 1993 1994 1994 1997 1999 2001
Top Speed
(MHz)
120 300 350 366 500 867
L1 Cache
Instr / Data
(Kbyte/Kbyte)
- 16/16 32/32 32/32 32/32 32/32
L2 Cache - - - 256K-1M 256K-1M 256K
L3 Cache - - - - - 1M-2M
Topical Outline
System Overview (G4)
Memory Management / Cache Hierarchy
System Model
Addressing and Instruction SetsRegister Sets
Branch Processing
Exception Handling
AltiVec (vector processes)
System Overview
Memory Management
2 Memory Management Units
3 Address Translation ModesPage Address Translation
Block Address Translation
Real Addressing Mode
Memory SupportPhysical Memory: 64 Gigabytes (236)
Virtual Memory: 4 Pentabytes (252)
Cache Hierarchy
L1 Cache32Kbyte Instruction and 32Kbyte Data Cache
L2 Cache256Kbyte unified Cache
L3 CacheOn chip L3 Cache Controller
1 – 2Mbyte off chip
System Model – PowerPC Register Set
Branch Processing
Unconditional and conditional instructions supported
Conditional Branch InstructionsTest single bit of CR and count register
9 separate conditions
Iteration loops use count register
Use of link register allows for call/return processing
Exception Handling
exception condition process interruptExamples
System reset
Machine check interrupt
MSR (Machine State Register)Allows for recovery of processor state
Interrupt HandlingUtilizes specific interrupt handlers.
AltiVec Technology
Why is this important???
AltiVec Technology:ImplementationImplementation
Questions?
References
M. Morris Mano and Charles R. Kime. Logic and Computer Design Fundamentals, 2nd Ed. Prentice-Hall: Upper Saddle River, NJ, 2000.
William Stallings, Computer Organization and Architecture, 5th Edition, Prentice-Hall, 2000.
Sam Fuller. Motorola’s AltiVec Technology. Motorola Inc. Semiconductor Product Sector. 1998. http://e-www.motorola.com/brdata/PDFDB/docs/ALTIVECWP.pdf
MPC7450 RISC Microprocessor Technical Summary. Motorola Inc. 5/2001. http://e-www.motorola.com/brdata/PDFDB/docs/MPC7450TS.pdf
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