PowerMixer IP : IP-Level Power Modeling for Processors
-
Upload
kermit-miranda -
Category
Documents
-
view
45 -
download
0
description
Transcript of PowerMixer IP : IP-Level Power Modeling for Processors
PowerMixerIP: IP-Level Power Modeling for Processors
Shan-Chien Fang1 Jia-Lu Liao2 Chen-Wei Hsu2 Chia-Chien Weng2
Shi-Yu Huang2 Wen-Tsan Hsieh3 Jen-Chieh Yeh3
1TinnoTek Inc, Taiwan ([email protected])
2Dept. of Electrical Engineering, National Tsing Hua University, Taiwan
3Industrial Technology Research Institute, Taiwan
Introduction Power dissipation has become a major design metric
IR drop, signal integritypower budgeting, power tradeoff, battery lifetimepower grid design, thermal analysis, packaging
High-level power estimation enable power optimization in early stageachieve higher power savingfast but often suffer from inadequate accuracy
PowerMixerIP
IP-based power modeling/analysis toolbottom-up power modeling/analysis methodologyfast and accurate power analysis for large SoC designs
Power Modeling Strategies
Processor Model
General IP Model
PowerMixerIPPowerMixerIP
1. For general IP2. Adopt operation-mode-based model3. By observing user-defined operation mode and key
signals
1. For general IP2. Adopt operation-mode-based model3. By observing user-defined operation mode and key
signals
1. Specific for processor2. Adopt instruction-level or stage-accurate model3. By observing the program counter register and the
instruction registers
1. Specific for processor2. Adopt instruction-level or stage-accurate model3. By observing the program counter register and the
instruction registers
IP-Based Power Simulation
μProcessor
(3) Essential VCD
(1) SoC Netlist (2) IP Power Models (.PMF)
Cache Bus DMA ASICs
……
(4) Std. CellPower Library
(4) Std. CellPower Library
PowerMixerIP
(IP-Based Power Simulation)
Power ProfilePower Profile PowerMixerIPcan significantly speed up the simulation process!
Processor Modeling Example:PAC-DSP Core Architecture
PACDSP core is a VLIW processor with 8 pipeline stages and 5 issues
ISA supports 206 instructions
Energy Model Complexity Enumerate all possible instruction combinations
206 is total number of instruction 5 is number of instructions per issue O(2065)
Divide all instructions into instruction classes instructions with similar behaviors in one class divide instructions into 13 types O(2065)O(135)
Sum up the individual power of each instruction in a issue O(135)O(13) Consider power consumption of an instruction in eight
different stages O(13)O(13*8) = O(104)
Divide the execution time of training programs into a number of basic periods
Basic period the time period during which the program counter’s value is not
changed calculate energy Ei of each basic period i
Basic Period of Processor Energy Model
CLK
PC 10000039 10000040 10000047 1000004e 10000056
E1 E2 E3 E4 E5
Generate Energy Matrix Energy Equation for Each Basic Period
Energy Matrix
Ei : energy consumption of the basic period iNi,s: number of times the s-th stage is executed in basic period iJs : one-time execution energy of the stage ss : pipeline stage id in each instruction class
n
1-n
2
1
104
103
2
1
104,103,2,1,
104,11,1
104,21,2
104,1103,12,11,1
E
E
E
E
J
J
J
J
NNNN
NN
NN
NNNN
nnnn
nn
Solve the energy matrix to obtain J vector
Ni,1 x J1 + Ni,2 x J2 + …… + Ni,104 x J104 = Ei
Experimental ResultsAccuracy and Runtime Comparisons of IP-level Power Analysis
General IP modelGeneral IP modelGate-levelGate-level
CLKSTATUS
ENDE
AESPower
Waveform
IP Design Gate CountAccuracy Comparison Run Time Comparison
Gate-level IP-level Error Gate-level IP-level Speedup
AES 88K 63.20 mW 63.29 mW 0.14% 120.1 sec 0.37 sec 324 X
PACDSP 248K 18.9 mW 18.3 mW -3.1% 937 .0sec 2 sec 468 X
AndesCore 490K 215.9 mW 220.2 mW 1.9% 10133.3 sec 32.21sec 314 X
8051 25K 1.53 mW 1.54 mW 0.7% 316 .7sec 6.02sec 52 X
Power Exploration & Design Trade-OffApplication: H.264 (100K instructions)Specification: PAC-DSP with various caches @ 240MHz
Norm
alized time
Norm
alized energy
Cache size
00.20.40.60.811.21.4
00.20.40.60.8
11.21.41.6
8k 16k 32k 64k
Normalized timeNormalized energy
Normalized time = TTarget
TReference Normalized energy=
ETarget
EReference
TTarget: Execution time of different cache sizes Treference: Execution time of 32K cache sizeETarget: Energy of different cache sizes Ereference: Energy of 32K cache size
SummaryPowerMixerIP: IP-based power analysis tool
Construct the power models of processors and other various IPs automatically
Explore potential power-performance trade-offs at an early SoC design stage
~100X power simulation speedup with high estimation accuracy