Power Integrity Challenges forNext Generation High-Speed Signalings

Dan Oh

Based on High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting,

by Oh and Yuan

AgendaAgenda

� Introduction− SI/PI trends and challenges

− Latest additions to jitter modeling topics: amplification and tracking

� Basics of power supply induced jitter (PSIJ) modeling− Basics of power supply noise induced jitter modeling

− Noise-to-jitter and noise-to-period-jitter sensitivity models

� Supply noise in various applications− Serial link

− parallel bus

− core digital operation

� Conclusions

2

Signaling (I/O) TrendsSignaling (I/O) Trends

� Continuous increase in data rate and bandwidth− Driven by multicore CPU and GPU

− Not as aggressive as before

� Cost sensitive design− Server (Sun,DEC,IBM) � PC (Intel) � consumer devices (Qualcomm,

Samsung, Apple) + clouds servers (Intel, ARM)

� Power optimized design− Server and mobile applications dominate market

� New signaling for on-chip communication− SOC, multicore

− 2.5D, 3D integrations

3

SOC TrendsSOC Trends

� Core frequency scaling slowed down− Timing closure is still challenging due to voltage scaling

� Power consumption continues to increase− Core power decoupling is still active development area

� Multicore and IP integration usage increased− Complex noise coupling and timing jitter impact

− Static supply noise budget leads to significant over or under estimation of timing error

� Clock and power gating is a must− Time to consider dynamic power decoupling schemes in addition to

conventional passive PDN design

− Potential hot research area

4

Signal and Power Integrity ChallengesSignal and Power Integrity Challenges

� High-speed links beyond 20Gb/s− Accurate passive channel modeling

− Exploration of advance signaling options (EQ, coding, etc.)

− Jitter spectrum and impact on BER

� Parallel and memory interfaces− Jitter tracking and amplification modeling

− Supply noise induced jitter modeling and simulation

� Bus coding, on-chip jitter path, supply-domain optimization, etc.

� 2.5D and 3D integration− Passive channel modeling (almost completed)

− Next steps, signaling optimization (jitter source and propagation)

� SOC design− Power distribution network design and dynamic noise modeling

− On-chip high-speed data communication

� Energy efficient computing− I/O performance optimization over multiple data rate

5

New Topics in Jitter ModelingNew Topics in Jitter Modeling

� Traditional analysis focuses on component level− Jitter contribution is statistically added to predict the system-level impact

− True margin requires system-level modeling (transmit and receive)

� What’s missing?− Transmitter jitter amplification

− Jitter cancellation by clock signal

� What has been changed?− Circuit design is more subject to power noise

� Stringent power target is used in modern IC designs

− System-level circuit and PDN co-design is necessary to remove pessimism

6

Component-Level Design Issues (PCIe2)Component-Level Design Issues (PCIe2)

Connector

PCB Trace

PackageChip

PCB Trace Via

Via

Via

Element (units in UI) RJ DJ TJ @ BER=10-12

Transmitter 0.007 0.15 0.25

Receiver 0.007 0.24 0.34

Channel 0 0.29 0.29

Ref Clock 0.02 0 0.28

Linear Sum 1.16

Root Sum of Squares 0.0223 0.68 1.0

LinkLab vs. Dual Dirac Model

-12

-10

-8

-6

-4

-2

0

0.0 0.2 0.4 0.6 0.8 1.0

Time (UI, 1UI = 200ps)

Lo

g B

ER

LinkLab

Dual Dirac

LinkLab vs. Dual Dirac Model

-12

-10

-8

-6

-4

-2

0

0.0 0.2 0.4 0.6 0.8 1.0

Time (UI, 1UI = 200ps)

Lo

g B

ER

LinkLab

Dual Dirac

Zero Margin

0.11 UI Margin

7

Limitations of Component-Level Timing BudgetLimitations of Component-Level Timing Budget

� Based on double-delta (dual-dirac) model

− DJ distribution is ignored

− Worst case DJs from different components are notaligned in general (linear sum is pessimistic)

− Potential double counting of some of jitter terms (i.e., separation of pkg effect)

− No RJ spectrums (assumes independent white Gaussian RJs)

à Produce pessimistic results

− No jitter amplification due to interaction is ignored.

à Produce optimistic results

∑∑ +=+=2

2 RJQDJTJTJTJ BERRJDJ

In overall, the budget is pessimistic

8

Jitter Impulse Response (JIR)Jitter Impulse Response (JIR)

� Move a single edge of a clock pattern

� Measure the edge variation at the output of channel compared to the ideal input location

No Amplification

Jit

ter

Am

ou

nt

Time

Lossy Channel

Amplification

Jit

ter

Am

ou

nt

Time

9

Jitter Amplification by Passive ChannelJitter Amplification by Passive Channel

� Channel attenuation results in jitter amplification

� Severe jitter amplification for high data rate and lossy channels

10 15 20 25 30

2

4

6

8

10

12

14

Signal Loss (dB)

Am

p F

acto

r

DCD

Measured data

Transient Sims

Statistical model

White Spectrum RJ

Data Rate

24’’ inch backplane used here

10

Jitter Tracking in Parallel BusJitter Tracking in Parallel Bus

� Tracking/cancellation of jitter for the blue path− Short channel systems results better tracking

− Very high-frequency jitter such as DCD is not tracked at all

� No tracking for the red path

Data

PLL +Buffers

Controller

FWD CLK

DRAM

• Controller noise

• DRAM noise

• RefClk jitter

• VRM/BRD

• AC self-induced

• Core noise coupling

f

f

f

• VRM/BRD

• AC self-induced

• Core noise coupling

f

11

Jitter Tracking ExampleJitter Tracking Example

No Tracking With Tracking

PLL +CLK

BUFFER

Controller

FWD CLK

DRAM

• Controller noise

• Dram noise

DATA

15mVp-pWhite Uniform

12

AgendaAgenda

� Introduction− SI/PI trends and challenges

− Latest additions to jitter modeling topics: amplification and tracking

� Basics of power supply induced jitter (PSIJ) modeling− Basics of power supply noise induced jitter modeling

− Noise-to-jitter and noise-to-period-jitter sensitivity models

� Supply noise in various applications− Serial link

− parallel bus

− core digital operation

� Conclusions

13

Power Supply Noise and JitterPower Supply Noise and Jitter

� Package technology developing at slower pace than process technology

− Power consumption does not decrease

− Supply noise stays relative constant but supply voltage level gradually lowers

� Low power design is a key in modern SOC devices− Clock gating, power gating, etc.

− Static load condition is no longer applicable

− Circuits are more sensitive to noise (results in more jitter)

� Jitter due to supply noise becomes a dominant timing error component

− I/O clock path delay is still large to accommodate more pins (more subject to voltage noise)

− Jitter in terms of unit interval (available time) increases as data rate increase

14

Overall Supply Induced Jitter Modeling FlowOverall Supply Induced Jitter Modeling Flow

V(f): Supply noise spectrum, circuit and data activity dependent

S(f): Jitter sensitivity profile, circuit dependent only

J(f): Jitter spectrum, magnitude and phase

×f

Supply Noise Spectrum

V(f)

=Noise Sensitivity Profile

f

H(f)

PSIJ Spectrum

f

J(f)

Current Profile

Power DistributionNetwork

CircuitImplementation

CircuitActivity

15

Noise-2-TIE Jitter Transfer Function (Open Loop)Noise-2-TIE Jitter Transfer Function (Open Loop)

* Additional sharp nulls at multiple of Nyquist frequency not shown here

×f

Supply Noise Spectrum

V(f)

=Noise Sensitivity Profile

f

H(f)

Jitter Spectrum

f

J(f)

)e-(1)(

)()()(

d20

τπfjHfH

fVfHfJ

−=

⋅=

12

120

VVH

−

−=

ττ

Longer Delay

-20dB/dec

n/Td

16

Jitter Sensitivity of PLL / DLL (Closed Loop)Jitter Sensitivity of PLL / DLL (Closed Loop)

� PLL and DLL are most sensitive to noise at loop BW frequency

− PLL (2nd order), DLL (1st order)

− PLL and DLL are high path filter to power supply noise

Frequency

Se

nsitiv

ity

0

0.5

1.0

1.5

Noise Frequency (Hz)

Clo

ck J

itte

r T

ransfe

r (p

s/m

V)

Loop BWLoop BW

[ PLL sensitivity ] [ DLL sensitivity ]

17

Noise-2-Period Jitter Transfer Function (Open Loop)Noise-2-Period Jitter Transfer Function (Open Loop)

×f

Supply Noise Spectrum

V(f)

=Noise Sensitivity Profile

f

H(f)

Jitter Spectrum

f

J(f)

anti-correlation (2 at 0.5*fck)

N*fck

n/Td

-3dB point(0.7 at ~0.1*fck)

)1()()(

)()()(

2 ckfTjperiod

periodperiod

efHfH

fVfHfJ

π−−⋅=

⋅=

18

AgendaAgenda

� Introduction− SI/PI trends and challenges

− Latest additions to jitter modeling topics: amplification and tracking

� Basics of power supply induced jitter (PSIJ) modeling− Basics of power supply noise induced jitter modeling

− Noise-to-jitter and noise-to-period-jitter sensitivity models

� Supply noise in various applications− Serial link

− parallel bus

− core digital operation

� Conclusions

19

CDR Based High Speed Serial LinkCDR Based High Speed Serial Link

� CDR recovers clock from incoming data

� High frequency jitter (> CDR BW) is not tracked out− CDR tracks only lower frequency jitter

− Golden PLL setting : data rate / 1667

PLL +CLK

BUFFER

TX RX

channel

SE

R

CDR

Recovered clock

20

CD

R B

an

dw

idth

(1M

~10M

Hz)

Serial Link Jitter Reduction ChallengesSerial Link Jitter Reduction Challenges

� PDN noise is typically above CDR bandwidth− PDN related jitter cannot be filtered out by PLL/CDR

� Accurate jitter modeling methodology is crucial to explore architecture-level solutions

Frequency (log)

PD

N I

mp

ed

an

ce P

rofi

le (

log

)

PD

N R

eso

nan

ce

(50~

300M

Hz)

CD

R C

hara

cte

risti

c (

log

)

Critical Region

21

Challenge for High Speed Transceiver DesignChallenge for High Speed Transceiver Design

� Typical TX jitter budget is about 0.28UI

� Additional on-chip decap is not cost effective− Reducing package inductance isn’t either

� Circuit level jitter reduction is required− Change current profile to minimize PDN noise generation

− Improve jitter sensitivity

Decap PSIJ vstarget

PSIJ reduction

Decap area/IP area

Extra die area / IP area

Base 660% - - -

x6 200% 73% 46% -

x14 95% 88% 121% 45%

22

SSN Reduction by Jitter Compensation CircuitSSN Reduction by Jitter Compensation Circuit

� Compensate non switching current to eliminate low and mid frequency noise

− Equivalent to clock pattern if all missing transitions are compensated

− Adjustable in terms of strength or occurrence

100

101

102

103

104

10-8

10-7

10-6

10-5

10-4

10-3

10-2

Freq [MHz]

Curr

ent S

pectr

um

[A

]

PDN resonance area

CLKPRBS15

Time

Time

[ Current of main path ]

[ Current of compensation path ]

[ Data transition of main path ]

[ Data transition of compensation ]

Patent pending

23

Jitter Reduction by Compensation CircuitJitter Reduction by Compensation Circuit

� 80% of PSIJ reduction has been achieved without additional decap

− x13 is required without jitter reduction technique

[ Simulated PSIJ ]

On-chip decap w/o compensation With compensation

Base 660% 135%

x2 300% 60%

x4 266% 47%

24

Parallel Bus Jitter Modeling ChallengesParallel Bus Jitter Modeling Challenges

� PDN related jitter is mostly cancelled due to forwarded clock

� Accurate jitter modeling methodology is crucial− To accurately account for the jitter impact and to optimize the circuit and PDN

designs

Frequency (log)

PD

N I

mp

ed

an

ce P

rofi

le (

log

)

PD

N R

eso

nan

ce

(50~

300M

Hz)

Jit

ter

Tra

ckin

g(>

800M

Hz)

2

1

Jit

ter

Tra

ckin

g F

acto

r (l

inear)

Critical Region

25

Jitter Tracking between DQ and DQsJitter Tracking between DQ and DQs

� If the noise frequency << data rate, jitter is cancelled out.− Small phase difference

− Depending on noise freq, tacking and anti tracking ( TF > 1 )

90̊ of DQ

DQS edge

Net margin loss

DQ

DQS

DQ DQS

90̊ of DQ

DQS edge

Net margin loss

DQ

DQS

[ Low frequency noise ] [ High frequency noise ]

Tskew

Tskew

26

DQ-DQS Tracking ImpactDQ-DQS Tracking Impact

� Low frequency jitter is canceled out

� Net timing margin loss is important

� System level co-design analysis is a must− To avoid overdesign and to balance the cost versus performance

0 400 800 1200 1600 2000-30

-20

-10

0

10

20

30

Time [ns]

Jitte

r [p

s]

[ TIE jitter ]

PLL TIE jitterNet jitter after tracking

Including big LF

Only HF

[ Jitter spectrum ]

100

101

102

10310

-4

10-3

10-2

10-1

100

101

Freq [MHz]

Jitte

r [p

s]

10-4

10-3

10-2

10-1

100

101

PLL jitterDQ-DQS net jitterTracking factor

27

System Level OptimizationSystem Level Optimization

� Separate and isolate power rails to reduce power noise coupling

� Add ODC to reduce PDN impedance of external power

� Shift PSRR peak to lower frequency by increasing loading cap− Avoid peak in anti tracking region

Frequency (log)

PD

N I

mp

ed

an

ce P

rofi

le (

log

)

Jit

ter

Tra

ckin

g F

acto

r (l

inear)

Reg

ula

tor

Perf

orm

an

ce (

log

)

10M 100M 1G

Anti tracking region

ODC

Cload

Power separation

28

Jitter Improvement by Design OptimizationJitter Improvement by Design Optimization

� Changing power configuration reduces clock jitter by 87% without additional ODC and OPD− Before optimization, clock jitter severely violates the target clock jitter

� Clock jitter spec is ±5% of Tck

� ±2% out of ±5 % Tck is for PSIJ

Net PSIJ Write Read Period CLK jitter

Improvement 83 % 65 % 85 %

Ratio (PSIJ/spec) 33 % 55 % 50 %

PSIJ of total write and read paths

Total path = non-regulated IPs + regulated IPs

29

Core Power Noise Pattern Modeling ChallengesCore Power Noise Pattern Modeling Challenges

� Broadband current spectrum with a few multitones

� Accurate core activity pattern modeling is important− Decoupling is more focus on surge current (low frequency component)

Frequency (log)

PD

N I

mp

ed

an

ce P

rofi

le (

log

)

PD

N R

eso

nan

ce

(20~

70M

Hz)

Co

re F

req

uen

cy

(>200M

Hz)

Co

re C

urr

en

t S

pectr

um

(li

near)

Critical Region

30

Dynamic Noise ChallengesDynamic Noise Challenges

� Large dynamic noise is reported by many SOC companies− Nvidia and Samsung (DesignCon 2014)

− Large power consumption and limited PDN resource

� Core power can no longer be decoupled effectively using a conventional target impedance method

− Intel, Nvidia, LSI and other SOC companies

− IVR (Integrated voltage regulator)?

� Traditional +/- 10% supply noise budget is no longer viable option

� EDA model of dynamic noise is very pessimistic− Modeling dynamic noise as dc variation is too pessimistic

31

Modeling Dynamic Noise as Timing ErrorModeling Dynamic Noise as Timing Error

� Conventional approach which models dynamic noise as a part of VMIN and VMAX budgets for .LIB STA models

− Pessimistic but a conventional approach taken by others

− Yield and performance impact due to large voltage variation

− Hard to accommodate clock gating and power gating induced large noise

� Timing error makes more sense as it reduces pessimism

− Accurate jitter tracking model between clock and data paths reduces most of low frequency noise

− Complex design flow

32

Jitter due to full activity and surge current is calculated

Circuit Activity Creating NoiseCircuit Activity Creating Noise

� Static current− Leakage current

− Dynamic voltage noise average

�Budgeted in supply rail voltage spec

High ActivityI(t)

NupNdown

Low ActivityLeakage Current

Dynamic Current AverageDynamic Current Variation

� Full activity mode (dynamic)− Idyn_p2p noise without average value

− Multiple clock frequencies

� Budgeted in timing jitter

� Surge current− Function of ramp time and dynamic current

− Impacts both low and high frequency noise

�Budgeted in timing jitter (currently in CU)

Surge Current Noise

33

Clocking in Digital Core Logic Clocking in Digital Core Logic

� PSIJ reduces setup/hold timing margin− Data must arrive before the capture clock and setup time

− Data must be unchanged during the hold time

� Common path jitter mostly cancels out− Significant non-common path jitter could be also canceled out

34

INBUF

PLL

Source DestinationArrival Path

Capture Path

Margin Loss due to Surge CurrentMargin Loss due to Surge Current

� Positive noise induced hold time jitter, while negative noise does setup time jitter

� Average IR drop must be subtracted from the jitter value in order to avoid double counting

250 300 350 400 450 500 550 600 650

0.7

0.8

0.9

1.0

20 Tck

Noise profile depending with 20 clock cycles ramping up

Time [ns]

Voltage [V

] -3% VDD

+6% VDD

Hold time loss

Setup time loss

35

ConclusionConclusion

� Signal and power integrity is a key to model IC designs− Optimum IC design requires a system-level jitter modeling

� Power supply induced jitter is a bottleneck for high speed serial/parallel IOs and higher fmax for digital logic

� Design focus and modeling techniques varies depending on interface type

− Clock embedded

− Clock forwarding

− Register to register application

36

Thank YouThank YouThank You