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Power Chip Interconnection: From Wirebonding to Area Bonding

The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number 4, Fourth Quarter, 2000 (ISSN 1063-1674)

© International Microelectronics And Packaging Society 407

Power Chip Interconnection: From Wirebondingto Area BondingXingsheng Liu and Guo-Quan LuPower Electronics Packaging LaboratoryCenter for Power Electronics SystemsVirginia TechBlacksburg, Virginia 24061-0111Phone: 540-231-3233Fax: 540-231-6390e-mails: [email protected], [email protected]

Abstract

Inside the state-of-the-art power devices and power modules, interconnection of power devices is accomplished with wirebonds.Wirebonds in power devices and modules are prone to high resistance, noise, parasitic oscillations, uneven current distribution,fatigue and eventual failure. Furthermore, for some applications, such as portable electronic products, higher power density andbetter efficiency are desired. Power semiconductor suppliers have been concentrating on improving device structure, density, andprocess technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconduc-tor technology are pushing packaging technology to the limits for performance of these power systems since the resistance andparasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. These limitations havemotivated researchers to seek new ways of packaging power semiconductor devices. To improve performance and reliability ofpackaged power electronics, wirebonds need to be replaced. The researchers have reported area-bonding technologies for intercon-necting power chips using solder bumps and/or metal posts1-4 . In this paper, the authors comparatively study the fabrication issues,the electrical performances, the thermal management, and the reliability of wirebonding and area bonding technologies for powerchip interconnection. The advantages and disadvantages of wirebonding and area bonding for power chip interconnection arepointed out.

Key words:

Power Electronics Packaging, Wirebonding, Area Bonding, Sol-der Bump, Metal Post, and IGBT.

1. Introduction and Background

Circuit assembly and packaging technologies for power elec-tronics5 -6 have not kept pace with those for integrated circuits(IC) chips7 . For the state-of-the-art power devices and modules,interconnection of power devices is accomplished with wirebonds,

which are prone to noise, parasitic oscillations, and fatigue fail-ure. In the rapidly expanding market of portable electronics wherepackaging density and power conversion efficiency are highlydesired, wirebonded power devices/modules are being pushed totheir functional limits. Recent advances in power semiconduc-tor technology further highlight the limitations of current pack-aging technology since resistance and parasitics contribution bythe package and the wirebonds are exceeding those in the sili-con. To improve performance, efficiency, and reliability of pack-aged power electronics, alternative interconnect techniques, suchas bond-wireless, are in need of development. There are severalpower packaging technologies under development to eliminatewirebonds8-14 . The authors introduced Die Dimensional Ball GridArray (D2BGA) Chip Scale power package, solder bump FlipChip technology, and metal post area array technology for powerelectronics packaging 1-4,8,15 . Recently, Fairchild announced thatthey developed BGA MOSFETs16 ; Paulasto et al.17 reported Flip

© International Microelectronics And Packaging Society


Intl. Journal of Microcircuits and Electronic Packaging

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Chip die attachment for multichip mechatronics power package;and Gillot et al.18 also proposed Flip Chip solder bump technol-ogy for interconnecting IGBT chip.

It is pointed out that packaging is a central driver in the futureof power electronics technology19 . Power electronics equipment,to date, is mostly custom-designed and requires a labor-intensivemanufacturing process. The resulting products are usually char-acterized by problems in quality, reliability, long design cycles,and high cost. Wirebonding, mother/daughter boards, and otherserial processes must be reduced to the minimum. Recent re-search results concerning components and processing within thefield of power electronics have not yielded the overall improve-ment needed for the next generation of power equipment elec-tronics. It is believed that the next level of improvement can beachieved only through a systems-level approach by developingintelligent, Integrated Power Electronics Modules (IPEM) thatwill enable greater integration within power electronics systems,and their end-use applications. IPEMs are envisioned to havehigh levels of integration of power semiconductor devices, gatedrive, and control circuitry for a wide range of power electronicsapplications. The IPEMs will be standardized, off-the-shelf unitsfor any range of power application, including computer, tele-communications, and aerospace applications, as well as high-volume commercial, and industrial power conversion equipmentand motor drives. The researchers have reported the IPEM struc-tures that use area bonds to interconnect active power chips in-stead of wirebonds1-4, 8. In this paper, the researchers compara-tively study the fabrication issues, the electrical performance, thethermal management, and the reliability of wirebonding and areabonding technologies for power chip interconnection. The ad-vantages and disadvantages of wirebonding and area bondingfor power chip interconnection are pointed out.

2. High-Density IPEM Challenges

Figure 1 shows a typical commercial power module. One cansee that wirebond module is a planar structure. The 2-D struc-ture makes it difficult to realize full integration of gate drive,controller, passive components, and other sensor and communi-cation circuitry. The bottom substrate accommodates power chips(the backside of the chips is drain), wirebond pads that is used toconnect source and gate (top surface of the chips) to the sub-strate, drain, source and gate tracks, and terminal leads that isconnected to outside power buses. All these end up occupying alarge area of the module substrate (non-silicon area). Conse-quently, wirebond module cannot fulfill the high density and sizereduction requirement. Also, the long substrate tracks, and bond-ing wires contribute to parasitic inductance and resistance andincrease the wire delay. Furthermore, this planar structure limitsheat transfer to one direction. There is an increasing demand forhigh frequency, high-density, high performance, and more inte-grated power modules. Three-dimensional multichip modules(MCMs) can meet the requirement for the future power electron-

ics systems. However, a major technical challenge to be over-come is the lack of three-dimensional packaging technologiesthat can offer high-level of integration of power devices, passivecomponents, driver circuitry, controls, sensors, and communica-tion connections. Figure 2 is an advanced three-dimensionalpackaging concept that has been envisioned for IPEM packag-ing. The wirebond interconnected power devices are excludedfrom three-dimensional MCMs due to their large size, poor ther-mal management, and incompatible processing techniques. Tomove toward with this concept, bond-wireless techniques for in-terconnecting power devices have to be developed.

4x IGBT 4x Diode

Mounting holes

Positive

Negative

Output

Plastic case

Wirebonds

IGBT

Diode

Silicone Gel

AlN-DBC

Base plate

Figure 1. Outside and inside of a wirebond module.

Integrated Passives

Integrated Communications, Sensors, Gate Drives, and Protection

Optical Fiber andAuxiliary Power

Connector

Advanced Devices

Thermally Conductive Encapsulant

Figure 2. Schematic of 3-D packaging concept for IPEMs.

In the dynamic signal-processing sector of the microelectron-ics industry where the critical performance measure is MillionInstructions Per Second (MIPS), one of the most promising tech-nology for interconnecting integrated circuit chips, the first levelpackaging, is Chip Scale Packaging (CSP) using Flip Chip in-terconnection20,21,22 . Flip Chip and CSP concepts to power elec-tronics packaging, as illustrated in Figure 3, have been extended.The result is a significantly higher packaging density and highersignal processing speeds when compared with wirebond inter-connected packages. One can see that the area array intercon-nects provide a larger effective contact area between power semi-conductor devices and outside circuitry. The low-profiled thickand short solder joints can carry larger currents than thinwirebonds, introduce much lower parasitic inductance, and im-prove heat dissipation due to added thermal path through thejoints. The larger contact area greatly reduces current crowdingand eliminates mechanical forces generated between wirebonds.This design also allows mechanical and thermo-mechanical forces




to be distributed over a larger area, thus reducing equivalentmechanical stresses at the device connections.

Wire Bonds

Small Contact Area of Wire Bond

Large Contact

Area of Post Array

Large Contact

Area of Solder Bump

Figure 3. Comparison of contact geometries of wirebondand area array interconnections.

The ability to have Known Good Die (KGD) before packag-ing them into a multichip module is highly desired for MCMpackaging. Supply of KGD helps lower the cost for manufactur-ing MCMs by cutting down the intermediate testing and reworktime during module fabrication. However, cost-effective burn-inand test technologies leading to KGD are still under develop-ment. This is especially true in power electronics, where testingbare dice (such as MOSFETs, IGBTs) at levels of several hun-dred to thousand volts and hundreds of amps is currently impos-sible. The Chip Scale Packaging of the power devices as shownin Figure 3 offers a potential solution for known-good powerdevices since the packaged devices can be readily handled andtested at full power ratings.

Figure 4 shows the area bonding that was processed on anIGBT rated at 1200 V and 70 A (Tc = 25oC) using solder bumpand metal posts. The device has source pads and one gate pad onthe topside and drain on the bottom. For this application, all ofthe contacts were made solderable by a device/module manufac-turer. Figure 4 (a) shows seven individual metal posts (1 mm x1mm x 2mm) that were soldered onto the source and gate pads,while Figure 4 (b) shows a single seven-post assembly solderedonto the device. Figure 4 (c) shows the solder bump intercon-nection of the IGBT chip. The as-packaged devices, which areessentially Chip Scale Packages, can be readily tested on a high-power curve tracer for static performance and in a circuit testerfor dynamic switching characteristics.

Gate

Source

Gate

Source

Figure 4. (a) Seven individual metal posts, (b) a singleseven-post assembly and (c) solder-bump interconnectionof IGBT.

These Chip Scale Packaged power devices enable the realiza-tion of three-dimensional packaging of integrated power elec-tronics modules shown in Figure 2. Several specific 3-D powermodule structures, as illustrated in Figure 5, have been devel-oped for different applications using the CSPs introduced above.The power CSPs are sandwiched between two metallic layers.The substrates are etched to the desired pattern. The bottom

layer is an AlN DBC. The top layer can be a doubled-sidedcopper-clad laminate or AlN DBC. The IGBTs and diodes areencapsulated using thermally conductive adhesive to help dissi-pate and distribute heat. For the structure shown in Figure 5 (a),driver and control circuits are built on top. For the design inFigure 5 (b), double sided cooling is realized. Driver and controlcircuits are built on the side of the power stage. This structure isof special interest for high power application.

Integrated Communications, Gate Drives and Protection

Solder Bump/Metal post Encapsulation Underfill

DeviceDevice

DBC Substrate

Double-sided Flex

Device Device

(a)

Metal Layers

Device DeviceDevice

Dielectric

Device

Heat Sink

Solder bump/Metal post

UnderfillEncapsulation

Heat Sink

Device

Dielectric

(b)

Figure 5. Schematic structure of 3-D power modules.

The manufacture process for wirebonding is also a big con-cern. It was indicated that the most important limitation ofwirebond has to do with the economics of chip usage itself7.Wirebonding cannot be performed easily in manufacturing overthe active area of chip compared to area-array solder bump con-nections, so the size of the chip is larger by about one-third withthe wirebonded chip23 . This difference will increase cost, as itdirectly relates to the number of chips per wafer7. Recent coststudy also shows that area array solder bump Flip Chip is cheaperthan wirebonding24 . Furthermore, wirebonding process for powerchip packaging can cause reliability problems. The wirebondingtechnique for most of active power chips is ultrasonic orthermosonic wedge bonding. Bonding pressure, power, and tem-perature are the sensitive factors determining bonding quality.With a poor bonding pressure, it is impossible to form a goodcontact between wire and bonding pad. This fact may lead to alow fracture strength at the bonding interface. Chip surface crack-ing during the wirebonding operation was observed as shown inFigure 6, and also was reported by other groups25,31-32. As onecan see from Figure 6, heel cracking and necking in the terminalside is also a failure source, especially for soft wires. Due to thisnecking effect, the wirebond sometimes fails at the heel first un-der the pull test, as shown in Figure 6 (b). Actually, during




410

wedge bonding process, the wires are first bonded on the padsand then they are pulled with a high force to get the needed wirelength and to make the loop. These movements apply a me-chanical stress at the heel of wires25 .

(a)

(b)

Figure 6. Chip surface cracking and wirebond heelcracking and necking during the wirebonding operation.

than the contact resistance between area bonds and chip pad.Figure 7 shows the average contact resistance of in-house madewirebonding, commercial wirebonding, and area bonding. Theinconsistency of the contact resistance makes the wirebondingworse. In Figure 7, the standard deviation of the contact resis-tances of six bonding on one IGBT chip is calculated and indi-cated in the Figure. One can see that the contact resistance ofwirebonding is widely scattered (from 9.8 to 20.3 m! for in-house made wirebonding and from 5.1 to 13.4 m! for commer-cial wirebonding), while that of area bonding is quite consistent.One would attribute this to the fact that wirebonding is sensitiveto several process parameters, while the area bonding is a single-step reflow process, which is easily controlled. This inconsis-tency contact resistance causes uneven current distribution amongwirebonds. The contact resistance for both the wirebond andarea bond to the substrate is quite low and consistent. Alto-gether, area bonding cuts down interconnect resistance by about65% compared to commercial wirebonding. Both posted andsolder bumped power device chip-scale packages have lower con-duction resistance due to the elimination of the wirebonds andother external interconnections such as the leadframe. Figure 8is the typical test data for CSP IGBT and commercially packagedIGBT1. Compared with the commercially packaged IGBT, theVCE(sat) and Ron of CSP IGBT are improved by about 17%, and30%, respectively.

02468

101214161820

1

Different Bonding

Con

tact

Res

ista

nce

(m Ω ΩΩΩ)

In-house wire bonding In-house wire bonding Area Bonding

Figure 7. Contact resistance for different bonding onpower chip pads.

2

2.5

3

3.5

4

4.5

5

Commercial packagedIGBT device

Area array IGBT CSP

Packages

V CE

15

25

35

45

Ron

Vce Ron

Figure 8. VCE and Ron for different IGBT packages.

Solder bump and metal post area array technologies use sol-der reflow process. This offers high process yield and high qual-ity bonding. The solder bump and metal post techniques make itpossible for the power-processing elements of a power module tobe in the form of low-profile surface mount packages.

3. Electrical Performance

Contact resistance between the interconnect bonding andpower chip pads, conduction resistance/voltage drop of the powerdevices, and parasitic inductance are the most important electri-cal parameters in power electronics packaging. The followingparagraphs summarize the test results of these parameters.

Contact resistance and conduction resistance/voltage drop:These experimental tests show that wirebonding have higher elec-trical resistance than solder bump and metal post area bonding.The typical resistance value of wirebond itself is 2-3 m!, whilethat of the area bonds is about 0.2 m!. The contact resistancebetween bonding wire and power chip pad is significantly higher




Parasitic inductance: is self-inductance and the mutual in-ductance of die bonding, circuit tracks, and leads. This induc-tance slows down the turn-on of the IGBT by an amount that isproportional to the di/dt of the collector current and causes turn-off overvoltage spikes and turn-on voltage drops. This not onlyincreases switching losses, but also can result in a peak voltageexceeding the rating of the devices. Figure 9 compares the volt-age overshoot characterized by switching tests. The 3-D modulehad about 8.7% voltage overshoot, while the commercial IGBTdevice and wirebond IGBT module had about 14%, and 20.8%voltage overshoot, respectively. Wirebond module has large para-sitic inductance associated mainly with the packaging of termi-nal leads, which is related to the planar packaging techniques.Since the bottom conductor pads have to accommodate bothwirebonds and terminal leads that carry a high current density,they end up occupying a large area of the module substrate (non-silicon area) and contribute to parasitic inductance. As moreIGBTs are paralleled, the inductance of the conductor pads be-comes more dominant. Parasitic modeling results showed26 -27

that the low-profile solder interconnects have a significantly lowerparasitic inductance, consistent with the observation of lower turn-off voltage overshoot. Modeling work attributed the majoritypart of reduction in parasitic inductance to the flexibility in lay-ing out shorter current tracks as well as the benefit of cancelingeffect of mutual inductance in the multilayer structures.

620

640

660

680

700

720

740

Wirebond IGBTmodule

Commercialpackaged IGBT

device

3-D IGBT moduel

Packages

Peak

vol

tage

5

15

25

Ove

rsho

ot p

enta

geMagnitude percentage

A Finite Element thermal analysis18, 28 indicated that 20-43%heat can be removed through the area joints.

Encapsulation Underfill

Top substrate

Solder bump/metal post

Power device

DBC

Figure 10. Three-dimensional thermal paths of 3-D modules.

5. Reliability Considerations

One major failure mechanisms encountered in the state-of-the-art wirebond power modules subjected to thermal and/orpower cycling is wirebond lift-off29-35 . Bonding wires are subjectto a thermal stress due to the large CTE mismatch between alu-minum wires and silicon chips when there are temperaturechanges during thermal/power cycling. This leads to bond fa-tigue and eventually failure. As mentioned earlier, poor bond-ing, potential chip surface cracking, and mechanical stress at theheel of wires35 due to the wirebonding process are also the sourcesof failure. The current imbalance in bonding wires, due to theinconsistency of contact resistance, proximity effect36,37 couldcause some thermal problem, or even burn out the wirebond con-nection. Most of the IGBT chips of the failed modules are burnedout either catastrophically or locally31-32. The emitter and gatebonding wires are observed to be either fused or lifted-open, asshown in Figure 11.

(a) (b) (c)Figure 11. Wirebond lifted-open or fused due to currentimbalance among bonding wires.

Electromigration might happen at a current density of about104 A/cm2 and at high temperature31,38 . The inconsistent contactresistance, high parasitics associated with the bonding wires, andthe proximity effect of the wires cause uneven current distribu-tion among the IGBT wirebonds and cells (within one chip aswell as among the paralleled chips). If the current distributesnon-uniformly among the IGBT chips, or wire debonding occursat first, then the current density in some wires will be much higherthan the average value and cause severe electromigration. Inaddition, high temperature plays an important role in thick wireelectromigration, which accelerates the migration process.

The high current in the wirebonds generates high electro-magnetic field, and since the wirebonds are so close to each other,

Figure 9. The peak voltages and overshoot percentages fordifferent packages.

4. Thermal Management

Wirebond modules are limited to one directional heat dissipa-tion. The area array CSPs have an additional thermal path, thetop solder bumps or metal posts. This makes three-dimensionalcooling possible. One can see from the 3-D power module struc-tures in Figure 2 that three-dimensional heat dissipation is real-ized, as show in Figure 10. The main thermal path is the back ofthe power device. Due to the very short length and large contactarea of a solder joint, the solder joint interconnection itself is agood thermal path. Thermally conductive encapsulant is the thirdthermal path, which helps transport heat away from power chips.




412

strong mechanical forces are generated between wirebonds. Thisalso affects the overall reliability of the power modules.

The CTE mismatching between silicon chip and the substrateis the most important issue in area array 3-D modules. The areabonding techniques offer opportunities to reduce thermal stressby optimizing solder joint geometry, using compliant substrateand underfilling1-3,15. The electrical modeling work also pointedout much uniform current distribution in the low-profile areaarray interconnects26-27. Thermal cycling test showed that the areabonding is quite reliable1.

6. Conclusion

The area bonding techniques and three-dimensional packag-ing structures have improved electrical performance, improvedthermal management of power modules, and reduced sizes (im-proved power density). Area bonding offers lower and consis-tent contact resistance and can carry large current. The inter-connect resistance is cut down by 65% and the on-state resis-tance of the IGBT is reduced by about 30%. The parasitic induc-tance (and thus turn-off voltage overshoot) of die bonding andcircuit tracks inside the 3-D modules is about 40% of that ofwirebond modules. Therefore, power loss (conduction loss andswitching loss) is greatly reduced. 3-D heat flow boosts heatdissipation capability in the proposed module structures. Thearea array interconnect techniques provide a solution of full inte-gration of power devices, passive components, gate driver, andcontrol circuitry.

Continued research is poised to take this successful imple-mentation (at medium power levels) of area bond packaging tech-niques, to high-power, and long-term reliability applications.

Acknowledgments

The authors would like to thank Dr. Chendong Bai, Dr. ShatilHaque, Sihua Wen, and Dan Huff for their assistance. The au-thors also give gratitude to Xiukuan Jing for his help with thepulse-switch tests and power stage tests. This work was sup-ported by the Office of Naval Research and ERC Program of theNational Science Foundation.

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About the authors

Xingsheng Liu received his B.S. Degree in Physics in 1995from Shaanxi Normal University in China and his M.S. Degreein Semiconductor Physics in 1998 from Beijing University inChina. Currently, he is a Ph.D. student in the Center for PowerElectronics Systems at Virginia Tech. Xingsheng Liu’s researchinterests include microelectronics, optoelectronics, and powerelectronics packaging, processing and applications of electronicand optoelectronic materials and components/devices, process-ing of thick and thin film materials, and materials characteriza-tion. Xingsheng Liu is a member of the IEEE-Components, Pack-aging, and Manufacturing Technology and the InternationalMicroelectronics and Packaging Society (IMAPS).

Dr. Guo-Quan Lu received his Ph.D. Degree in Applied Phys-ics/Materials Science from Harvard University in 1990. From1990 to 1992, Dr. Lu worked for Alcoa Electronic Packaging,Inc., at Alcoa Technical Center, Pittsburgh, Pennsylvania. In1992, Dr. Lu joined the faculty of the Department of MaterialsScience and Engineering at Virginia Tech. Currently, he is anAssociate Professor jointly appointed between the Department ofMaterials Science and Engineering and the Bradley Departmentof Electrical and Computer Engineering. Dr. Lu teaches coursesin both departments. His research interests include processingand applications of electronic and optoelectronic materials, com-ponents/devices, and microelectronic and power electronic pack-ages. Dr. Lu holds two U.S. patents and has published over 50papers in journals and conference proceedings.

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