PLC Modicon 840USE48600_1

Breite: 185Höhe: 23012 mm Buchrücken (1 mm für 10 Blatt bzw. 1mm für 20 Seiten)bis 40 Seiten kein Rücken!Cover-Nr.33001214.00

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Schneider Automation S. A.245, Route des Lucioles - BP 147F-06903 Sophia-AntipolisTel.: (33) 4 92 96 20 00Fax: (33) 4 93 65 37 15

Schneider Automation GmbHSteinheimer Straße 117D-63500 SeligenstadtTel.: (49) 61 82 81-0Fax: (49) 61 82 81-33 06

Schneider Automation, Inc.One High StreetNorth Andover, MA 01845, USATel.: (1) 978 794 0800Fax: (1) 978 975 9010

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Breite: 185 mmHöhe: 230 mm

Concept

LL984 Functions & Functionblocks

Version 2.2

Volume 1

Block Library

840 USE 486 00

04/99

Data, Illustrations, AlterationsData and illustrations are not binding. We reserve the right to alter products in line with our policyof continuous product development. If you have any suggestions for improvements oramendments or have found errors in this publication, please notify us using the form on one ofthe last pages of this publication.

TrainingSchneider Automation offers suitable further training on the system.

HotlineSee addresses for the Technical Support Centers at the end of this publication.

TrademarksAll terms used in this publication to denote Schneider Automation products are trademarks ofSchneider Automation.

All other terms used in this publication to denote products may be registered trademarks and/ortrademarks of the corresponding Corporations.Microsoft and MS-DOS are registered trademarks of Microsoft Corporation, Windows is abrandname of Microsoft Corporation in the USA and other countries.IBM is a registered trademark of International Business Machines Corporation.Intel is a registered trademark of the Intel Corporation.

CopyrightAll rights are reserved. No part of this document may be reproduced or transmitted in any formor by any means, electronic or mechanical, including copying, processing or by online filetransfer, without permission in writing by Schneider Automation. You are not authorized totranslate this document into any other language.

1995–99 Schneider Automation GmbH. All rights reserved

Contents

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Contents

Info 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbols used 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terms and abbreviations used 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional documentation 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Validity note 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1 General 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Instruction 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 Operation 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Nodes, In– and Outputs 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Instruction Groups 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 ASCII Communication Instructions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Counters and Timers Instructions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Fast I/O Instructions 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Loadable DX 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Math Instructions 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 Matrix Instructions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.7 Miscellaneous 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.8 Move Instructions 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.9 Skips/Specials 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.10 Special Instructions 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.11 Coils, Contacts and Interconnects 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Closed Loop Control / Analog Values 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Set Point and Process Variable 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 PCFL Subfunctions 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 A PID Example 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.4 PID2 Level Control Example 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Formatting Messages for ASCII READ/WRIT Operations 25. . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Format Specifiers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Special Set-up Considerations for Control/Monitor Signals Format 27. . . . . . . . . . . . . . .

1.5 Interrupt Handling 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Interrupt-related Performance 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Interrupt Priorities 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 Instructions that Cannot Be Used in an Interrupt Handler 30. . . . . . . . . . . . . . . . . . . . . . . 1.5.4 Interrupt with BMDI/ID/IE 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Subroutine Handling 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Installation of DX Loadables 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Chapter 2 Coils, Contacts and Interconnects 35. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Coils 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Normal Coil 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Retentive Coil 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Contacts 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Contact Normally Open 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Contact Normally Closed 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Contact Pos Trans 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Contact Neg Trans 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Interconnects (Shorts) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Horizontal Short 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Vertical Short 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Descriptions 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD16 Add 16 Bit 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD Addition 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND Logical And 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD Binary to Binary Code 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLKM Block Move 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLKT Block to Table 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMDI Block Move with Interrupts Disabled 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BROT Bit Rotate 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHS Configure Hot Standby 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CKSM Check Sum 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMPR Compare Register 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMP Complement a Matrix 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCTR Down Counter 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIOH Distributed I/O Health 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIV Divide 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLOG Data Logging for PCMCIA Read/Write Support 71. . . . . . . . . . . . . . . . . . . . . . . . . DRUM DRUM Sequencer 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DV16 Divide 16 Bit 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH Extended Math 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–ADDDP Double Precision Addition 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–ADDFP Floating Point Addition 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–ADDIF Integer + Floating Point Addition 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–ANLOG Base 10 Antilogarithm 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–ARCOS Floating Point Arc Cosine of an Angle (in Radians) 92. . . . . . . . . . . . . . EMTH–ARSIN Floating Point Arcsine of an Angle (in Radians) 94. . . . . . . . . . . . . . . . . . EMTH–ARTAN Floating Point Arc Tangent of an Angle (in Radians) 96. . . . . . . . . . . . . EMTH–CHSIN Changing the Sign of a Floating Point Number 98. . . . . . . . . . . . . . . . . . EMTH–CMPFP Floating Point Comparison 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–CMPIF Integer–Floating Point Comparison 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–CNVDR Floating Point Conversion of Degrees to Radians 104. . . . . . . . . . . . . . EMTH–CNVFI Floating Point to Integer Conversion 106. . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–CNVIF Integer–to–Floating Point Conversion 108. . . . . . . . . . . . . . . . . . . . . . . . . .

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EMTH–CNVRD Floating Point Conversion of Radians to Degrees 110. . . . . . . . . . . . . . EMTH–COS Floating Point Cosine of an Angle (in Radians) 112. . . . . . . . . . . . . . . . . . . EMTH–DIVDP Double Precision Division 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–DIVFI Floating Point Divided by Integer 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–DIVFP Floating Point Division 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–DIVIF Integer Divided by Floating Point 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–ERLOG Floating Point Error Report Log 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–EXP Floating Point Exponential Function 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–LNFP Floating Point Natural Logarithm 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–LOG Base 10 Logarithm 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–LOGFP Floating Point Common Logarithm 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–MULDP Double Precision Multiplication 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–MULFP Floating Point Multipliation 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–MULIF Integer x Floating Point Multiplication 136. . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–PI Load the Floating Point Value of p 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–POW Raising a Floating Point Number to an Integer Power 140. . . . . . . . . . . . . EMTH–SINE Floating Point Sine of an Angle (in Radians) 142. . . . . . . . . . . . . . . . . . . . . EMTH–SQRFP Floating Point Square Root 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–SQRT Square Root 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–SQRTP Process Square Root 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–SUBDP Double Precision Subtraction 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–SUBFI Floating Point – Integer Subtraction 153. . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–SUBFP Floating Point Subtraction 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–SUBIF Integer – Floating Point Subtraction 157. . . . . . . . . . . . . . . . . . . . . . . . . . . EMTH–TAN Floating Point Tangent of an Angle (in Radians) 159. . . . . . . . . . . . . . . . . . . EUCA Engineering Unit Conversion and Alarms 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIN First In 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FOUT First Out 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTOI Floating Point to Integer 175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HLTH History and Status Matrices 176. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSBY Hot Stand By Control System 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBKR Indirect Block Read 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBKW Indirect Block Write 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICMP Input Compare 193. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Interrupt Disable 197. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IE Interrupt Enable 199. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMIO Immediate I/O 201. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMOD Interrupt Module Instruction 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITMR Interrupt Timer 210. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITOF Integer to Floating Point 214. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JSR Jump to Subroutine 215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAB Label for a Subroutine 217. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LOAD Load Flash 219. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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MAP 3 MAP Transaction 221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MBIT Modify Bit 226. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MBUS MBUS Transaction 228. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MRTM Multi–Register Transfer Module 234. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSTR Master 237. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MU16 Multiply 16 Bit 271. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUL Multiply 272. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Info

This documentation will help you configure the LL984–instructions from Concept.

Volume 1

Ch. 1 Provides general information about LL984–instructions, instruction groups, closed loopcontrol, formatting messages for ASCII Read/Write operations, interrupt handling,subroutine handling and installation of Loadables.

Ch. 2 Provides information about coils, contacts and interconnects.

Instruction Descriptions Contains the instruction descriptions arranged alphabetically from A to M according totheir abbreviations.

Volume 2

Ch. 1 Provides general information about LL984–instructions, instruction groups, closed loopcontrol, formatting messages for ASCII Read/Write operations, interrupt handling,subroutine handling and installation of Loadables.

Instruction Descriptions Contains the instruction descriptions arranged alphabetically from N to Z according totheir abbreviations.

Glossary Contains the glossary arranged alphabetically from A to Z.

Info

222

Symbols used

NoteThis symbol is used to emphasize important factors.

CautionThis symbol refers to frequently occurring error sources.

WarningThis symbol points to sources of danger that may cause financial and/orhealth–related damages or may have other serious consequences.

ExpertThis symbol is used for more in–depth information directed specifically at experts(special training required). Skipping this information in no way impedes theunderstanding of the document, nor does it restrict standard application of the product.

TipThis symbol is used to emphasize the explanation of special tips when working with theproduct.

This symbol identifies application examples.

� Proceed as follows:This marks the beginning of a series of applications that must execute in orderto achieve a certain product function.

STOP

Example

Info

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22

Terms and abbreviations used

Numbers are written according to international practice as well as according to approvedSI (Système International d’ Unités) presentation: Each thousand is separated by aspace, along with use of the decimal point, e. g. 12 345.67.

Additional documentation

Bezeichnung TypInstallation Instruction 840 USE 482 00User Manual (Volume 1 + Volume 2) 840 USE 483 00IEC Block Library (Volume 1 + Volume 2 + Volume 3) 840 USE 484 00Modicon TSX Quantum PLC Series, Hardware User’s Manual 840 USE 100 00Modbus Plus Network, User’s Manual 890 USE 100 00Modlink User’s Guide Modicon GM–MLNK–001User’s Guide Modicon IBM Host Based Devices GM–HBDS–001User’s Guide BM85 Modbus Plus Bridge / Multiplexer GM–BM85–001Planning and Installation Guide Modicon Quantum Hot Standby System 840 USE 106 00

Validity note

This documentation is valid for Concept Version 2.2 under Microsoft Windows 95,Windows 98 or Windows NT.

NoteFor additional up–to–date notes, please refer to the file README.WRI of Concept.

Info

224

5


20

General

In this chapter you find general information about

� Instructions� Instruction groups� Closed loop control� Formatting messages for ASCII Read/Write operations� Interrupt handling� Subroutine Handling� Installation of Loadables

1

General

206

1.1 Instruction

Programming for electrical controls involves a user who implements Operational Codedinstructions in the form of visual objects organized in a recognizable ladder form. Theprogram objects designed, at the user level, is converted to computer usable OP codesduring the download process. the Op codes are decoded in the CPU and acted upon bythe controllers firmware functions to implement the desired control.

Each instruction is composed of an operation, nodes required for the operation and in–and outputs.

Figure 1 Parameter assignment with the instruction DV16 as an example

Instruction

OutputsOperation Nodese.g. DV16

top nodeTop input

Middle input

Bottom input

Top output

Middle output

Bottom outputDV16

bottom node

middle node

Inputs

1.1.1 Operation

The operation determines which functionality is to be executed by the instruction, e.g.shift register, conversion operations.

1.1.2 Nodes, In– and Outputs

The nodes and in– and outputs determines what the operation will be executed with.

General

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20

1.2 Instruction Groups

All instructions are attached to one of the following groups:

� ASCII Communication Instructions� Counters and Timers Instructions� Fast I/O Instructions� Loadable DX� Math Instructions� Matrix Instructions� Miscellaneous� Move Instructions� Skips/Specials� Special Instructions� Coils, Contacts and Interconnects

DIOHPCFLPID2STAT

Instruction Selection

Close Help

Group

Counters/TimersMathMoveMatrixSpecialSkips/SpecialsMiscellaneousASCII Functions

Help on Instruction

Element

BLKMBLKTFINFOUTIBKRIBKWR>TSRCHT>RT>TTBLK

DLOGEMATH

MSTR

SCIF

LABRETSKPCSKPR

READWRIT

DCTRT.01T0.1T1.0T1MS

BMDIIDIEIMIOIMOD

Fast I/O Instruction

AD16ADDBCDDIVDV16FTOIITOFMU16MULSU16SUBTEST

ANDBROTCMPRCOMPMBITNBITNCBTNOBTORRBITSBITSENSXOR

CHSDRUMEUCAHLTHHSBYICMPMAP3MBUSMRTMPEER

Loadable DX

XMRDXMWT

JSR

ITMR

UCTR

SAVE

LOAD

CKSM

General

208

1.2.1 ASCII Communication Instructions

Instruction Meaning Available at PLC familyQuantum Compact Momentum Atrium

READ Read ASCII messages yes no no noWRIT Write ASCII messages yes no no no

PLCs that support ASCII messaging use instructions called READ and WRIT to handlethe sending of messages to display devices and the receiving of messages from inputdevices. These instructions provide the routines necessary for communication betweenthe ASCII message table in the PLC’s system memory and an interface module at theRemote I/O drops.

Further information on page 25

1.2.2 Counters and Timers Instructions


UCTR Counts up from 0 to a preset va-lue

yes yes yes yes

DCTR Counts down from a preset valueto 0

yes yes yes yes

T1.0 Timer that increments in seconds yes yes yes yesT0.1 Timer that increments in tenths of

a secondyes yes yes yes

T.01 Timer that increments in hun-dredths of a second

yes yes yes yes

T1MS Timer that increments in one milli-second

yes (CPU242 02only)

yes yes yes

General

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1.2.3 Fast I/O Instructions

The following instructions are designed for a variety of functions known generally as fastI/O updating. They fall into three categories:


BMDI Block move with interrupts disa-bled

yes yes no yes

ID Disable interrupt yes yes no yesIE Enable interrupt yes yes no yesIMIO Immediate I/O instruction yes yes no yesIMOD Interrupt module instruction yes yes no yesITMR Interval timer interrupt no yes no yes

Further information on page 29

NoteThe Fast I/O Instructions are only available after configuring a CPU without extension.

1.2.4 Loadable DX


CHS Hot standby (Quantum) yes no no noDRUM DRUM sequenzer yes yes no yesEUCA Engineering unit conversion and

alarmsyes yes no yes

HLTH History and status matrices yes yes no yesHSBY Hot standby control system yes no no yesICMP Input comparison yes yes no yesMAP3 MAP 3 Transaction no no no noMBUS MBUS Transaction no no no noMRTM Multi–register transfer module yes yes no yesPEER PEER Transaction no no no noXMIT RS 232 Master Mode yes yes yes no

Further information for installation of Loadables on page 33

Further information to XMIT you will find in the ”Modicon XMIT Loadable User Guide, 840USE 113 00”.

General

2010

1.2.5 Math Instructions

Two groups of instructions that support basic math operations are available. The firstgroup comprises four integer-based instructions: ADD, SUB, MUL and DIV

The second group contains five comparable instructions, AD16, SU16, TEST, MU16 andDV16, that support signed and unsigned 16-bit math calculations and comparisons.

Three additional instructions, ITOF, FTOI and BCD, are provided to convert the formatsof numerical values (from integer to floating point, floating point to integer, binary to BCDand BCD to binary). Conversion operations are usful in expanded math.

Integer Based Instructions


ADD Addition yes yes yes yesDIV Division yes yes yes yesMUL Multiplication yes yes yes yesSUB Subtraction yes yes yes yes

Comparable Instructions


AD16 Add 16 bit yes yes yes yesDV16 Divide 16 bit yes yes yes yesMU16 Multiply 16 bit yes yes yes yesSU16 Subtract 16 bit yes yes yes yesTEST Test of 2 values yes yes yes yes

Format Conversion


BCD Conversion from binary to binarycode or binary code to binary

yes yes yes yes

FTOI Conversion from floating point tointeger

yes yes yes yes

ITOF Conversion from integer to floa-ting point

yes yes yes yes

General

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1.2.6 Matrix Instructions

A matrix is a sequence of data bits formed by consecutive 16-bit words or registersderived from tables. DX matrix functions operate on bit patterns within tables.

Just as with move instructions, the minimum table length is 1 and the maximum tablelength depends on the type of instruction you use and on the size of the CPU (24-bit) inyour PLC.

Groups of 16 discretes can also be placed in tables. The reference number used is thefirst discrete in the group, and the other 15 are implied. The number of the first discretemust be of the first of 16 type 000001, 100001, 000017, 100017, 000033, 100033, ... ,etc..


AND Logical AND yes yes yes yesBROT Bit rotate yes yes yes yesCMPR Compare register yes yes yes yesCOMP Complement a matrix yes yes yes yesMBIT Modify bit yes yes yes yesNBIT Bit control yes yes no yesNCBT Normally open bit yes yes no yesNOBT Normally closed bit yes yes no yesOR Logical OR yes yes yes yesRBIT Reset bit yes yes no yesSBIT Set bit yes yes no yesSENS Sense yes yes yes yesXOR Exclusive OR yes yes yes yes

1.2.7 Miscellaneous


CKSM Check sum yes yes yes yesDLOG Data Logging for

PCMCIA Read/Write Supportno yes no no

EMTH Extended Math Functions yes yes yes yesLOAD Load flash no yes no noMSTR Master yes yes yes yesSAVE Save flash no yes no noSCIF Sequential control interfaces yes yes no yesXMRD Extended memory read yes no no yesXMWT Extended memory write yes no no yes

General

2012

1.2.8 Move Instructions


BLKM Block move yes yes yes yesBLKT Table to block move yes yes yes yesFIN First in yes yes yes yesFOUT First out yes yes yes yesIBKR Indirect block read yes yes no yesIBKW Indirect block write yes yes no yesR –>T Register to tabel move yes yes yes yesSRCH Search table yes yes yes yesT–>R Table to register move yes yes yes yesT–>T Table to table move yes yes yes yesTBLK Table to block move yes yes yes yes

1.2.9 Skips/Specials


JSR Jump to subroutine yes yes yes yesLAB Label for a subroutine yes yes yes yesRET Return from a subroutine yes yes yes yesSKPC Skip (constant) yes yes yes yesSKPR Skip (register) yes yes yes yes

The SKP instruction is a standard instruction in all PLCs. It should be used with caution.

WarningSKP is a dangerous instruction that should be used carefully. If inputs and outputsthat normally effect control are unintentionally skipped (or not skipped), the resultcan create hazardous conditions for personnel and application equipment.

STOP

General

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1.2.10 Special Instructions

These instructions are used in special situations to measure statistical events on theoverall logic system or create special loop control situations


DIOH Distributed I/O health yes no no yesPCFL Process control function library yes yes no yesPID2 Proportional integral derivative yes yes yes yesSTAT Status yes yes yes yes

1.2.11 Coils, Contacts and Interconnects

Coils, Contacts and Interconnects are availabel at all PLC families

� Normal coil� Memory-retentive, or latched, coil� Normally open (N.O.) contact� Normally closed (N.C.) contact� Positive transitional (P.T.) contact� Negative transitional (N.T.) contact� Horizontal Short� Vertical Short

General

2014

1.3 Closed Loop Control / Analog Values

An analog closed loop control system is one in which the deviation from an ideal processcondition is measured, analyzed and adjusted in an attempt to obtain and maintain zeroerror in the process condition. Provided with the Enhanced Instruction Set is aproportional-integral-derivative function block called PID2, which allows you to establishclosed loop (or negative feedback) control in ladder logic.

1.3.1 Set Point and Process Variable

The desired (zero error) control point, which you will define in the PID2 block, is calledthe set point (SP). The conditional measurement taken against SP is called the processvariable (PV). The difference between the SP and the PV is the deviation or error (E). Eis fed into a control calculation that produces a manipulated variable (Mv) used to adjustthe process so that PV = SP (and, therefore, E = 0).

Process

ControlEnd Device

Control Calculation

Mv

PV

SP

–

+E

Process Transmitter

PV (Input)(Output)

General

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1.3.2 PCFL Subfunctions

The PCFL instruction gives you access to a library of process control functions utilizinganalog values. PCFL operations fall into three major categories:

� Advanced Calculations� Signal Processing� Regulatory Control

Advanced CalculationsAdvanced calculations are used for general mathematical purposes and are not limited toprocess control applications. With advanced calculations, you can create custom signalprocessing algorithms, derive states of the controlled process, derive statisticalmeasures of the process, etc.

Simple math routines have already been offered in the EMTH instruction. The calculationcapability included in PCFL is a textual equation calculator for writing custom equationsinstead of programming a series of math operations one by one.

Signal ProcessingSignal processing functions are used to manipulate process and derived process signals.They can do this in a variety of ways; they linearize, filter, delay and otherwise modify asignal. This category would include functions such as an Analog Input/Output, Limiters,Lead/Lag and Ramp generators.

Regulatory ControlRegulatory functions perform closed loop control in a variety of applications. Typically,this is a PID (proportional integral derivative) negative feedback control loop. The PIDfunctions in PCFL offer varying degrees of functionality. Function PID has the samegeneral functionality as the PID2 instruction but uses floating point math and representssome options differently. PID is beneficial in cases where PID2 is not suitable because ofnumerical concerns such as round-off.

General

2016

Y � YP � YI � YD � Bias integral bit ONY � YP � YD � Bias � BT integral bit OFF

with the following high/low output limits:Yhigh � Y � Ylow

withYP, YI, YD � f(XD)XD � SP � X � (GRZ � (1 � KGRZ))XD � SP � X

gain reductiongain reduction zone not used

Proportional CalculationYP � KP � XD proportional bit ONYP � 0

Integral Calculation

YI � YI � KP ��tTI

�XD_1 � XD

2integral bit ON

YI � 0

Derivative Calculation

YI � 0

DXD � X_1 � XDXD � XD � X_1

base dervative or PV

YD �(TD1 � YD) � (TD � KP � DXD)

�t � TD1derivative bit ON

General Equations

where:

Y = manipulated variable output YP = proportional part of the calculation YI = integral part of the calculation YD = derivative part of the calculation Bias = constant added to input BT = bumpless transfer register SP = set point KP = proportional gain ∆t = time since last solve TI = integral time constant TD = derivative time constant TD1 = derivative time lag XD = error term, deviation XD_1 = previous error term X = process input X_1 = previous process input

General

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CONTROL DEVIATION

SP

GAIN

X(n)

+

–

0

1

1

0

1

0

0

1

1

0

– GAIN

a)

b)

c)

ManualAutomatic

Halt Y (n)

MODE SELECT

SUMMING

Anti–Windup–Reset

HIGH

LOW

+

TI

TD

a)

b)

c)

SET POINT

INPUT

JUNCTION

OPERATING

PROPORTIONAL

INTEGRAL

1 = DERIVATIVE ON

1 = INTEGRAL ON

CONTROL

1 = PROPORTION ON

MODES

CONTROLOUTPUT

Anti–Windup Limits

DERVATIVE Contributions

0 = base Derivitave on XD1 = base Derivative on X

P+I+D

General

2018

1.3.3 A PID Example

PID Example

This example illustrates how a typical PID loop could be configured using PCFL functionPID. The calculation begins with the AIN function, which takes raw input simulated tocause the output to run between approximately 20 and 22 when the engineering unitscale is set to 0 ... 100.

T0.1

400185

# 3

# 14

PCFL

400100

AIN

# 39

PCFL

400120

LKUP

# 14

PCFL

400160

RAMP

# 8

PCFL

400190

MODE

# 44

PCFL

400200

PID

000100

# 9

PCFL

400250

AOUT 000100

# 2

BLKM

400120

400112

# 2

BLKM

400200

400157

# 2

BLKM

400190

400172

# 2

BLKM

400206

400196

# 2

BLKM

400250

400242

The process variable over time should look something like this:

Time

Process Variable Value

20

22

Example

General

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20

Main PID Ladder LogicThe AIN output is block moved to the LKUP function, which is used to scale the inputsignal. We do this because the input sensor is not likely to produce highly linearreadings; the result is an ideal linear signal:

0

100

80

60

40

20

50

20 40 60 80 10050Input

Actual Input

Linearized Signal

7 Points DefinedIn Look Up table

*

*

*

*

**

The look-up table output is block moved to the PID function. RAMP is used to control therise (or fall) of the set point for the PID controller with regard to the rate of ramp and thesolution interval. In this example, the set point is established in another logic section tosimulate a remote setting. The MODE function is placed after the RAMP so that we canswitch between the RAMP-generated set point or a manual value.

General

2020

Simulated ProcessThe PID function is actually controlling the process simulated by this logic:

T0.1

400188

# 3

# 20

PCFL

400260

LLAG

# 20

PCFL

400280

LLAG

# 32

PCFL

400300

DELAY

# 9

PCFL

400340

AOUT

000103

000103

# 1

BLKM

400260

400242

# 1

BLKM

400280

400278

# 1

BLKM

400300

400298

# 1

BLKM

400340

400330

# 1

BLKM

400100

400348000103

400100: 878(Dec)

The process simulator is comprised of two LLAG functions that act as a filter and input toa DELAY queue that is also a PCFL function block. This arrangement is the equivalent ofa second-order process with dead time.

The solution intervals for the LLAG filters do not affect the process dynamics and werechosen to give fast updates. The solution interval for the DELAY queue is set at 1000 mswith a delay of 5 intervals,i.e. 5 s. The LLAG filters each have lead terms of 4 s and lagterms of 10 s. The gain for each is 1.0.

In process control terms the transfer function can be expressed as:

GP(S) �(4S � 1)(4S � 1)e�5S

(10S � 1)(10S � 1)

The AOUT function is used only to convert the simulated process output control valueinto a range of 0 ... 4 095, which simulates a field device. This integer signal is used asthe process input in the first network.

General

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20

PID ParametersThe PID controller is tuned to control this process at 20.0, using the Ziegler-Nicholstuning method. The resulting controller gain is 2.16, equivalent to a proportional band of46.3%.

The integral time is set at 12.5 s/repeat (4.8 repeats/ min). The derivative time is initially3 s, then reduced to 0.3 s to de–emphasize the derivative effect.

An AOUT function is used after the PID. It conditions the PID control output by scalingthe signal back to an integer for use as the control value.

The entire control loop is preceded by a 0.1 s timer. The target solution interval for theentire loop is 1 s, and the full solve is 1 s. However, the nontime-dependent functionsthat are used (AIN, LKUP, MODE, and AOUT) do not need to be solved every scan. Toreduce the scan time impact, these functions are scheduled to solve less frequently. Theexample has a loop solve every 3 s, reducing the average scan time dramatically.

NoteIt is still important to be aware of the maximum scan impact. When programming otherloops, you will not want all of the loops to solve on the same scan

General

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1.3.4 PID2 Level Control Example

PID2 Level Control Example

Here is a simplified P&I diagram for an inlet separator in a gas processing plant. There isa two-phase inlet stream: liquid and gas.

Condensate

Gas

Vent

PlantInlet

Inlet Vent

Blowdown

PV–1

LV

FCI/P 1

LC 1

LT 1

LSH 1

FCVInlet Block

LT–1 = 4 ... 20 mA level transmitterI/P–1 = 4 ... 20 mA current to pneumatic converter

LSH–1 = high level switch, normally closedLSL–1 = low level switch, normally open

I/P–1 = Mv to control the flow into tank T–1LC–1 = level controller

LV–1 = control valve, fail CLOSED

LSL 1

The liquid is dumped from the tank to maintain a constant level. The control objective isto maintain a constant level in the separator. The phases must be separated beforeprocessing; separation is the role of the inlet separator, PV–1. If the level controller,LC–1, fails to perform its job, the inlet separator could fill, causing liquids to get into thegas stream; this could severely damage devices such as gas compressors.

Example

General

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The level is controlled by device LC–1, a Quantum controller connected to an analoginput module; I/P–1 is connected to an analog output module. We can implement thecontrol loop with the following 984 ladder logic:

400113

SUB

#0

300001

SUB

#0

400102

#30

PID2

400200

400101000101

400500

000102

000103

The first SUB block is used to move the analog input from LT–1 to the PID2 analog inputregister, 40113. The second SUB block is used to move the PID2 output Mv to the I/Omapped output I/P–1. Coil 00101 is used to change the loop from AUTO to MANUALmode, if desired. For AUTO mode, it should be ON.

Specify the set point in mm for input scaling (E.U.). The full input range will be 0 ... 4000mm (for 0 ... 4095 raw analog). Specify the register content of the top node in the PID2block as follows:

Register ContentNumeric

ContentMeaning

Comments

400100 Scaled PV (mm) PID2 writes this400101 2000 Scaled SP (mm) Set to 2000 mm (half full) initial-

ly400102 0000 Loop output (0 ... 4095 PID2 writes this; keep it set to 0

to be safe400103 3500 Alarm High Set Point (mm) If the level rises above 3500

mm, coil 000102 goes ON400104 1000 Alarm Low Set Point (mm) If the level drops below 1000

mm, coil 000103 goes ON400105 0100 PB (%) The actual value depends on

the process dynamics

General

2024

Register CommentsContentMeaning

ContentNumeric

400106 0500 Integral constant (5.00 repeats/min)

The actual value depends onthe process dynamics

400107 0000 Rate time constant (per min) Setting this to 0 turns off the de-rivative mode

400108 0000 Bias (0 ... 4095) This is set to 0, since we havean integral term

400109 4095 High windup limit (0 ... 4095) Normally set to the maximum400110 0000 Low windup limit (0 ... 4095) Normally set to the minimum400111 4000 High engineering range (mm) The scaled value of the process

variable when the raw input isat 4095

400112 0000 Low engineering range (mm) The scaled value of the processvariable when the raw input isat 0

400113 Raw analog measure (0 ...4095)

A copy of the input from theanalog input module register(300001) copied by the firstSUB

400114 0000 Offset to loop counter register Zero disables this feature.Normally, this is not used

400115 0000 Max loops solved per scan See register 400114400116 0102 Pointer to reset feedback If you leave this as zero, the

PID2 function automaticallysupplies a pointer to the loopoutput register. If the actual out-put (400500) could be changedfrom the value supplied byPID2, then this register shouldbe set to 500 (400500) to calcu-late the integral properly

400117 4095 Output clamp high (0 ... 4095) Normally set to maximum400118 0000 Output clamp low (0 ... 4095) Normally set to minimum400119 0015 Rate Gain Limit Constant (2 ...

30)Normally set to about 15. Theactual value depends on hownoisy the input signal is. Sincewe are not using derivative mo-de, this has no effect on PID2

400120 0000 Pointer to track input Used only if the PRELOAD fea-ture is used. If the PRELOAD isnot used, this is normally zero

The values in the registers in the 400200 destination block are all set by the PID2 block.

General

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1.4 Formatting Messages for ASCII READ/WRITOperations

The ASCII messages used in the READ and WRIT instructions can be created via yourpanel software using the format specifiers described below. Format specifiers arecharacter symbols that indicate:

� The ASCII characters used in the message� Register content displayed in ASCII character format� Register content displayed in hexadecimal format� Register content displayed in integer format� Subroutine calls to execute other message formats

1.4.1 Format Specifiers

/ Meaning ASCII return (CR) and linefeed (LF)Field width None (defaults to 1)Prefix None (defaults to 1)

Input format Outputs CR, LF; no ASCII characters acceptedOutput format Outputs CR, LF

” ” Meaning Enclosure for octal control codeField width Three digits enclosed in double quotesPrefix None

Input format Accepts three octal control charactersOutput format Outputs three octal control characters

‘ ’ Meaning Enclosure for ASCII text characters

Field width 1 ... 128 charactersPrefix None (defaults to 1)Input format Inputs number of upper and/or lower case printable characters

specified by the field widthOutput format Outputs number of upper and/or lower case printable characters

specified by the field width

X Meaning Space indicator—e.g., 14X indicates 14 spaces left open fromthe point where the specifier occurs

Field width None (defaults to 1)

Prefix 1 ... 99 spacesInput format Inputs specified number of spacesOutput format Outputs specified number of spaces

General

2026

( ) Meaning Repeat contents of the parentheses—e.g., 2 (4X, I5) saysrepeat 4X, I5 two times

Field width None

Prefix 1 ... 255Input format Repeat format specifiers in parentheses the number of times

specified by the prefixOutput format Repeat format specifiers in parentheses the number of times

specified by the prefix

I Meaning Integer—e.g., I5 specifies five integer characters

Field width 1 ... 8 characters

Prefix 1 ... 99Input format Accepts ASCII characters 0 ... 9. If the field width is not satis-

fied, the most significant characters in the field are padded withzeros

Output format Outputs ASCII characters 0 ... 9. If the field width is not satis-fied, the most significant characters in the field are padded withzeros. The overflow field consists of asterisks.

L Meaning Leading zeros—e.g., L5 specifies five leading zeros

Field width 1 ... 8 charactersPrefix 1 ... 99

Input format Accepts ASCII characters 0 ... 9. If the field width is not satis-fied, the most significant characters in the field are padded withzeros

Output format Outputs ASCII characters 0 ... 9. If the field width is not satis-fied, the most significant characters in the field are padded withzeros. The overflow field consists of asterisks.

A Meaning Alphanumeric—e.g., A27 specifies 27 alphanumeric charac-ters, no suffix allowed

Field width None (defaults to 1)

Prefix 1 ... 99Input format Accepts any 8-bit character except reserved delimiters such as

CR, LF, ESC, BKSPC, DEL.Output format Outputs any 8-bit character

O Meaning Octal—e.g., O2 specifies two octal characters

Field width 1 ... 6 charactersPrefix 1 ... 99Input format Accepts ASCII characters 0 ... 7. If the field width is not satis-

fied, the most significant characters are padded with zeros.Output format Outputs ASCII characters 0 ... 7. If the field width is not satis-

fied, the most significant characters are padded with zeros. Nooverflow indicators.

General

27


20

B Meaning Binary—e.g., B4 specifies four binary characters


Input format Accepts ASCII characters 0 and 1. If the field width is not satis-fied, the most significant characters are padded with zeros.

Output format Outputs ASCII characters 0 and 1. If the field width is not satis-fied, the most significant characters are padded with zeros. Nooverflow indicators.

H Meaning Hexadecimal—e.g., H2 specifies two hex characters


Input format Accepts ASCII characters 0 ... 9 and A ... F. If the field width isnot satisfied, the most significant characters are padded withzeros.

Output format Outputs ASCII characters 0 ... 9 and A ... F. If the field width isnot satisfied, the most significant characters are padded withzeros. No overflow indicators.

1.4.2 Special Set-up Considerations for Control/Monitor Signals Format

To control and monitor the signals used in the messaging communication, specify code1002 in the first register of the control block (the register displayed in the top node). Viathis format, you can control the RTS and CTS lines on the port used for messaging.

TipIn this format, only the local port can be used for messaging—i.e., a parent PLC cannotmonitor or control the signals on a child port. Therefore, the port number specified in thefifth implied node of the control block must always be 1.

The first three registers in the data block (the displayed register and the first and secondimplied registers in the middle node) have predetermined content:

Register ContentDisplayed (see Figure 2) Stores the control mask wordFirst implied (see Figure 3) Stores the control data wordSecond implied (see Figure 4) Stores the status word

General

2028

Figure 2 Control Mask Word

1 = control RTS0 = do not control RTS

1 2 3 54 6 7 8 9 10 11 1312 14 1615

1 = port can be taken0 = port cannot be taken

Figure 3 Control Data Word

1 = activate RTS0 = deactivate RTS

1 2 3 54 6 7 8 9 10 11 1312 14 1615

1 = take port0 = return port

Figure 4 Status Word

1 2 3 54 6 7 8 9 10 11 1312 14 1615

1 = port taken1 = port ACTIVE as Modbus slave

1 = RTS ON1 = CTS ON

1 = DSR ON

These three data block registers are required for this format, and therefore the allowablerange for the length value (specified in the bottom node) is 3 ... 255.

General

29


20

1.5 Interrupt Handling

1.5.1 Interrupt-related Performance

The interrupt-related instructions operate with minimum processing overhead. Theperformance of interrupt-related instructions is especially critical. Using a interval timerinterrupt (ITMR) instruction adds about 6% to the scan time of the scheduled ladderlogic—this increase does not include the time required to execute the interrupt handlersubroutine associated with the interrupt.

The following table shows the minimum and maximum interrupt latency times you canexpect:

Interrupt Latency TimesITMR overhead No work to do 60 �s/msResponse time Minimum 98 �s

Maximum during logic solve andModbus command reception

400 �s

Total overhead (not counting normal logic solve time) 155 �s

These latency times assume only one interrupt at a time.

1.5.2 Interrupt Priorities

The PLC uses the following rules to choose which interrupt handler to execute in theevent that multiple interrupts are received simultaneously:

� An interrupt generated by an interrupt module has a higher priority than an interruptgenerated by a timer.

� Interrupts from modules in lower slots of the local backplane have priority overinterrupts from modules in the higher slots.

� Within a local slot, lower input bit on an interrupt module have higher priority thanhigher input bits on that module.

If the PLC is executing an interrupt handler subroutine when a higher priority interrupt isreceived, the current interrupt handler is completed before the new interrupt handler isbegun.

General

2030

1.5.3 Instructions that Cannot Be Used in an Interrupt Handler

The following (nonreenterant) ladder logic instructions cannot be used inside an interrupthandler subroutine:

� MSTR� READ/WRIT� PCFL/EMTH� T1.0, T0.1, T.01 and T1MS timers (will not set error bit 2, timer results invalid)� Equation Networks� User loadables (will not set error bit 2)

If any of these instructions are placed in an interrupt handler, the subroutine will beaborted, the error output on the ITMR or IMOD instruction that generated the interruptwill go ON, and bit 2 in the status register will be set.

1.5.4 Interrupt with BMDI/ID/IE

Three interrupt mask/unmask control instructions are available to help protect data inboth the normal (scheduled) ladder logic and the (unscheduled) interrupt handlingsubroutine logic. These are the Interrupt Disable (ID) instruction, the Interrupt Enable (IE)instruction, and the Block Move with Interrupts Disabled (BMDI) instruction.

An interrupt that is executed in the timeframe after an ID instruction has been solved andbefore the next IE instruction has been solved is buffered. The execution of a bufferedinterrupt takes place at the time the IE instruction is solved. If two or more interrupts ofthe same type occur between the ID ... IE solve, the mask interrupt overrun error bit isset, and the subroutine initiated by the interrupts is executed only one time

The BMDI instruction can be used to mask both a timer-generated and localI/O-generated interrupts, perform a single block data move, then unmask the interrupts. Itallows for the exchange of a block of data either within the subroutine or at one or moreplaces in the scheduled logic program.

BMDI instructions can be used to reduce the time between the disable and enable ofinterrupts. For example, BMDI instructions can be used to protect the data used by theinterrupt handler when the data is updated or read by Modbus, Modbus Plus, Peer Copor Distributed I/O (DIO).

General

31


20

1.6 Subroutine Handling

JSR / LAB Method

The example below shows a series of three user logic networks, the last of which is usedfor an up-counting subroutine. Segment 3 has been removed from the order-of-solvetable in the segment scheduler:

Segment 001Network 00001

Network 00002

Network 00001

000001JSR

00000110001

Segment 002

Network 00001

Segment 003

LAB000001

ADD000001

400256 RET000001

000001JSR

000001

Scheduled Logic Flow

Subroutine Segment

SUB

400256

000010

400256SUB

400256

400256

400256

400999

When input 100001 to the JSR block in network 2 of segment 1 transitions from OFF toON, the logic scan jumps to subroutine #1 in network 1 of segment 3.

Example

General

2032

The subroutine will internally loop on itself ten times, counted by the ADD block. The firstnine loops end with the JSR block in the subroutine (network 1 of segment 3) sendingthe scan back to the LAB block. Upon completion of the tenth loop, the RET block sendsthe logic scan back to the scheduled logic at the JSR node in network 2 of segment 1.

General

33


20

1.7 Installation of DX Loadables

The DX loadable instructions are only available if you have installed them.

With the installation of the Concept software, DX loadables are located on your harddisk. Now you have to unpack and install the loadables you want to use as follows:

Step 1 With the menu command Project → Configurator you open the configurator

Step 2 With Configure → Loadables... you open the dialog box Loadables

Step 3 Press the command button Unpack... to open the standard Windows dialog boxUnpack Loadable File where the multifile loadables (DX loadables) can beselected. Select the loadable file you need, click the button OK and it is inserted into thelist box Available:.

Step 4 Now press the command button Install=> to install the loadable selected in the listbox Available:. The installed loadable will be displayed in the list box Installed:.

Step 5 Press the command button Edit... to open the dialog box LoadableInstruction Configuration. Change the opcode if necessary or accept thedefault. You can assign an opcode to the loadable in the list box Opcode in order toenable user program access through this code. An opcode that is already assigned to aloadable, will be identified by a *. click the button OK.

Step 6 Click the button OK in the dialog box Loadables.

Configuration loadables count is adjusted. The installed loadable is available forprogramming at the menu ”Objects → List Instructions → DX Loadable”.

General

2034

35


20

Coils, Contacts and Interconnects

In this chapter you find information about

� Coils� Contacts� Interconnects (Shorts)

2


2036

2.1 Coils

A coil is a discrete output that is turned ON and OFF by power flow in the logic program.A single coil is tied to a 0x reference in the PLC’s state RAM. Because output values areupdated in state RAM by the PLC, a coil may be used internally in the logic program orexternally via the I/O map to a discrete output unit in the control system. When a coil isON, it either passes power to a discrete output circuit or changes the state of an internalrelay contact in state RAM.

There are two types of coils:

� A normal coil� A memory-retentive, or latched, coil

2.1.1 Normal Coil

A normal coil is a discrete output shown as a 0x reference.

A normal coil is ON or OFF, depending on power flow in the program.

A ladder logic network can contain up to seven coils, no more than one per row. When acoil is placed in a row, no other logic elements or instruction nodes can appear to theright of the coil’s logic–solve position in the row. Coils are the only ladder logic elementsthat can be inserted in column 11 of a network.

To define a discrete reference for the coil, select it in the editor and click to open a dialogbox called Coil.

Symbol

????

WarningWhen a discrete input (1x) is disabled, signals from its associated inputfield device have no control over its ON/OFF state. When a discrete output(0x) is disabled, the PLC’s logic scan has no control over the ON/OFFstate of the output. When a discrete input or output has been disabled,you can change its current ON/OFF state with the Force command.

There is an important exception when you disable coils. Data move anddata matrix instructions that use coils in their destination node recognizethe current ON/OFF state of all coils in that node, whether they are

STOP


37


20

disabled or not. If you are expecting a disabled coil to remain disabled insuch an instruction, you may cause unexpected or undesirable effects inyour application.

When a coil or relay contact has been disabled, you can change its stateusing the Force ON or Force OFF command. If a coil or relay is enabled, itcannot be forced.

2.1.2 Retentive Coil

If a retentive (latched) coil is energized when the PLC loses power, the coil will comeback up in the same state for one scan when the PLC’s power is restored.

To define a discrete reference for the coil, select it in the editor and click to open a dialogbox called Retentative coil (latch).

Symbol

????

L


2038

2.2 Contacts

Contacts are used to pass or inhibit power flow in a ladder logic program. They arediscrete—i.e., each consumes one I/O point in ladder logic. A single contact can be tiedto a 0x or 1x reference number in the PLC’s state RAM, in which case each contactconsumes one node in a ladder network.

Four kinds of contacts are available:

� Normally open (N.O.) contacts� Normally closed (N.C.) contacts� Positive transitional (P.T.) contacts� Negative transitional (N.T.) contacts

2.2.1 Contact Normally Open

A normally open (NO) contact passes power when it is ON.

To define a discrete reference for the NO contact, select it in the editor and click to opena dialog called Normally open contact.

Symbol

????

2.2.2 Contact Normally Closed

A normally closed (NC) contact passes power when it is OFF.

To define a discrete reference for the NC contact, double ckick on it in the ladder node toopen a dialog called normally closed contact.

Symbol

????


39


20

2.2.3 Contact Pos Trans

A positive transitional (PT) contact passes power for only one scan as it transitions fromOFF to ON.

To define a discrete reference for the PT contact, select it in the editor and click to open adialog called Positive transition contact.

Symbol

????

2.2.4 Contact Neg Trans

A negative transitional (NT) contact passes power for only one scan as it transitions fromON to OFF.

To define a discrete reference for the NT contact, select it in the editor and click to opena dialog called Contact negative transition .

Symbol

????


2040

2.3 Interconnects (Shorts)

Shorts are simply straight-line connections between contacts and/or instructions in aladder logic network. Shorts may be inserted horizontally or vertically in a network.

Two kinds of shorts are available:

� Horizontal Short� Vertical Short

2.3.1 Horizontal Short

A short is a straight–line connection between contacts and/or nodes in an instructionthrough which power flow can be controlled. A scan is the time it takes for the PLC tosolve all scheduled logic in the program, service the I/O drops, and perform systemoverhead.

A horizontal short is used to extend logic out across a row in a network without breakingthe power flow. Each horizontal short consumes one node in the network, and uses aword of memory in the PLC.

Symbol

2.3.2 Vertical Short

A vertical short connects contacts or nodes in an instruction positioned one above theother in a column. Vertical shorts can also connect inputs or outputs in an instruction tocreate either–or conditions. When two contacts are connected by a vertical short, poweris passed when one or both contacts receive power.

The vertical short is unique in two ways:

� It can coexist in a network node with another element or nodal value� It does not consume any PLC memory

Symbol

41


20

Instruction Descriptions

The instruction descriptions are arranged alphabetically according to their abbreviations.

AD16

43


20

AD16Add 16 Bit

1 Brief Description

The AD16 instruction performs signed or unsigned 16-bit addition on value 1 (its topnode) and value 2 (its middle node), then posts the sum in a 4x holding register in thebottom node.

2 Representation

2.1 Symbol

value 1

AD16

sum

value 2

2.2 Parameter Description

Parameters State RAMReference

Data Type Meaning

Top input 0x, 1x None ON = enables value 1 + value 2

Bottom input 0x, 1x None ON = signed operationOFF = unsigned operation

value 1(top node)

3x, 4x INT, UINT Addend, can be displayed explicitly as an inte-ger (range 1 ... 65 535) or stored in a register

value 2(middle node)


sum(bottom node)

4x INT, UINT Sum of 16 bit addition

Top output 0x None ON = successful completion of the operationBottom output 0x None ON = overflow in the sum:

sum > 65 535 in unsigned operation–32 768 > sum > 32 767 in signed operation

ADD

2044

ADDAddition

1 Brief Description

The ADD instruction adds unsigned value 1 (its top node) to unsigned value 2 (its middlenode) and stores the sum in a holding register in the bottom node.

2 Representation

2.1 Symbol

value 1

ADD

sum

value 2



Data Type Meaning

Top input 0x , 1x None ON = add value 1 and value 2value 1(top node)

3x, 4x INT, UINT Addened, can be displayed explicitly as an in-teger (range 1 ... 9 999) or stored in a register



sum(bottom node)

4x INT, UINT Sum

Bottom output 0x None ON = overflow in the sum: sum > 9 999

AND

45


20

ANDLogical And

1 Brief Description

The AND instruction performs a Boolean AND operation on the bit patterns in the sourceand destination matrices. The ANDed bit pattern is then posted in the destination matrix,overwriting its previous contents:

0 0

1

1 1 0

0

1

source bits

0

0 1

0

destination bitsAND AND AND AND

Warning AND will override any disabled coils within the destination matrix withoutenabling them. This can cause personal injury if a coil has disabled an operationfor maintenance or repair because the coil’s state can be changed by the ANDoperation.

2 Representation

2.1 Symbol

source

AND

length

destination

matrix

matrix

STOP

AND

2046



Data Type Meaning

Top input 0x, 1x None Initiates ANDsource matrix(top node)

0x , 1x, 3x, 4x BOOL, WORD First reference in the source matrix.

destinationmatrix(middle node)

0x, 4x BOOL, WORD First reference in the destination matrix

length(bottom node)

INT, UINT Matrix length; range 1 ... 100.

Top output 0x None Echoes state of the top input

3 Detailed Description

3.1 Parameter DescriptionMatrix Length (Bottom Node)The integer entered in the bottom node specifies the matrix length, i.e. the number ofregisters or 16-bit words in the two matrices. The matrix length can be in the range1 ... 100. A length of 2 indicates that 32 bits in each matrix will be ANDed.

BCD

47


20

BCDBinary to Binary Code

1 Brief Description

The BCD instruction can be used to convert a binary value to a binary coded decimal(BCD) value or a BCD value to a binary value. The type of conversion to be performed iscontrolled by the state of the bottom input.

2 Representation

2.1 Symbol

source

BCD

#1

register

destinationregister



Data Type Meaning

Top input 0x, 1x None ON = enable conversion

Bottom input 0x, 1x None ON = BCD → binary conversionOFF = binary → BCD conversion

Source regi-ster(top node)

3x, 4x INT, UINT Source register where the numerical value tobe converted is stored

Destinationregister(middle node)

4x INT, UINT Destination register where the converted nu-merical value is posted

#1(bottom node)

INT, UINT Constant value, can not be changed

Top output 0x None Echoes the state of the top inputBottom output 0x None ON = error in the conversion operation

BLKM

2048

BLKMBlock Move

1 Brief Description

The BLKM (block move) instruction copies the entire contents of a source table to adestination table in one scan.

WarningBLKM will override any disabled coils within a destination table without enablingthem. This can cause injury if a coil has been disabled for repair or maintenancebecause the coil’s state can change as a result of the BLKM instruction.

2 Representation

2.1 Symbol

source

BLKM

table

destination

table

table

length



Data Type Meaning

Top input 0x, 1x None ON = initiates block move

source table(top node)

0x, 1x, 3x, 4x ANY_BIT Source table that will have its contents copiedin the block move

destinationtable(middle node)

0x, 4x ANY_BIT Destination table where the contents of thesource table will be copied in the block move

table length(bottom node)

INT, UINT Table size (number of registers or 16-bitwords) for both the source and destination ta-bles; they are of equal length. Range: 1 ... 100.

Top output 0x None Echos the state of the top input

STOP

BLKT

49


20

BLKTBlock to Table

1 Brief Description

The BLKT (block-to-table) instruction combines the functions of R–>T and BLKM in asingle instruction. In one scan, it can copy data from a source block to a destinationblock in a table. The source block is of a fixed length. The block within the table is of thesame length, but the overall length of the table is limited only by the number of registersin your system configuration.

WarningBLKT is a powerful instruction that can corrupt all the 4x registers in your PLCwith data copied from the source block. You should use external logic inconjunction with the middle or bottom input to confine the value in the pointer to asafe range.

2 Representation

2.1 Symbol

source

BLKT

block length

pointer

block

STOP

BLKT

2050



Data Type Meaning

Top input 0x, 1x None ON = initiates the DX moveMiddle input 0x, 1x None ON = hold pointerBottom input 0x, 1x None ON = reset pointer to zerosource block(top node)

4x BYTE, WORD First holding register in the block of contiguousregisters whose content will be copied to ablock of registers in the destination table.

pointer(middle node)

4x BYTE, WORD Pointer to the destination table

block length(bottom node)

INT, UINT Block length (number of 4x registers) of thesource block and of the destination block. Ran-ge: 1 ... 100.

Top output 0x None ON = operation successfulMiddle output 0x None ON = error / move not possible


3.1 Parameter DescriptionMiddle and Bottom InputThe middle and bottom input can be used to control the pointer so that source data is notcopied into registers that are needed for other purposes in the logic program.

When the middle input is ON, the value in the pointer register is frozen while the BLKToperation continues. This causes new data being copied to the destination to overwritethe block data copied on the previous scan.

When the bottom input is ON, the value in the pointer register is reset to zero. Thiscauses the BLKT operation to copy source data into the first block of registers in thedestination table.

Pointer (Middle Node)The 4x register entered in the middle node is the pointer to the destination table. The firstregister in the destination table is the next contiguous register after the pointer, e.g. if thepointer register is 400107, then the first register in the destination table is 400108.

NoteThe destination table is segmented into a series of register blocks, each of which is thesame length as the source block. Therefore, the size of the destination table is a multipleof the length of the source block, but its overall size is not specifically defined in theinstruction. If left uncontrolled, the destination table could consume all the 4x registersavailable in the PLC configuration.

BLKT

51


20

The value stored in the pointer register indicates where in the destination table thesource data will begin to be copied. This value specifies the block number within thedestination table.

BMDI

2052

BMDIBlock Move with Interrupts Disabled

NoteThis instruction is only available after configuring a CPU without extension.

1 Brief Description

The BMDI instruction masks the interrupt, initiates a block move (BLKM) operation, thenunmasks the interrupts.

Further Information you will find in the chapter ”General” on page 29.

2 Representation

2.1 Symbol

source

BMDI

table

destination

table

table

length

BMDI

53


20



Data Type Meaning

Top input 0x, 1x None ON = masks interrupt, initiates a block move,then unmasks the interrupts


0x, 1x, 3x, 4x INT, UINT,WORD

Source table that will have its contents copiedin the block move

destinationtable(middle node)

0x, 4x INT, UINT,WORD

Destination table where the contents of thesource table will be copied in the block move

table length(bottom node)

INT, UINT Integer value, specifies the table size, i.e. thenumber of registers, in the source and destina-tion tables (they are of equal length). Range:1 ... 100.

Top output 0x None Echoes the state of the top input

BROT

2054

BROTBit Rotate

1 Brief Description

The BROT (bit rotate) instruction shifts the bit pattern in a source matrix, then posts theshifted bit pattern in a destination matrix. The bit pattern shifts left or right by one positionper scan.

WarningBROT will override any disabled coils within a destination matrix without enablingthem. This can cause injury if a coil has been disabled for repair or maintenance ifBROT unexpectedly changes the coil’s state.

2 Representation

2.1 Symbol

source

BROT

length

destination

matrix

matrix

STOP

BROT

55


20



Data Type Meaning

Top input 0x, 1x None ON = shifts bit pattern in source matrix by one

Middle input 0x, 1x None ON= shift leftOFF = shift right

Bottom input 0x, 1x None OFF = exit bit falls out of the destination matrixON = exit bit wraps to start of the destinationmatrix

source matrix(top node)

0x, 1x, 3x, 4x ANY_BIT First reference in the source matrix, i.e. in thematrix that will have its bit pattern shifted

destinationmatrix(middle node)

0x, 4x ANY_BIT First reference in the destination matrix, i.e. inthe matrix that shows the shifted bit pattern

length(bottom node)

0x INT, UINT Matrix length; range: 1 ... 100

Top output 0x None Echoes state of the top inputMiddle output 0x None OFF = exit bit is 0

ON = exit bit is 1


3.1 Parameter DescriptionMatrix Length (Bottom Node)The integer value entered in the bottom node specifies the matrix length, i.e. the numberof registers or 16-bit words in each of the two matrices. The source matrix anddestination matrix have the same length. The matrix length can range from 1 ... 100, e.g.a matrix length of 100 indicates 1600 bit locations

Result of the Shift (Middle Output)The middle output indicates the sense of the bit that exits the source matrix (the leftmostor rightmost bit) as a result of the shift.

CHS

2056

CHSConfigure Hot Standby

NoteThis instruction is only available, if you have unpacked and installed the DX Loadables;further information in the chapter ”General” on page 33.

1 Brief Description

The logic in the CHS loadable is the engine that drives the Hot Standby capability in aQuantum PLC system. Unlike the HSBY instruction, the use of the CHS instruction in theladder logic program is optional. However, the loadable software itself must be installedin the Quantum PLC in order for a Hot Standby system to be implemented.

2 Representation

2.1 Symbol

command

CHS

length

nontransfer

register

area

CHS

57


20



Data Type Meaning

Top input 0x, 1x None Execute Hot Standby (unconditionally)

Middle input 0x, 1x None ON = Enable command register

Bottom input 0x, 1x None ON = Enable nontransfer areaOFF = nontransfer area will not be used andthe Hot Standby status register will not exist

command re-gister(top node)

4x INT, UINT,WORD

Hot Standby command register

nontransferarea(middle node)

4x INT, UINT,WORD

First register in the nontransfer area of stateRAM

length(bottom node)

INT, UINT Number of registers of the Hot Standby non-transfer area in state RAM; range 4 ... 8000

Top output 0x None Hot Standby system ACTIVEMiddle output 0x None PLC cannot communicate with its CHS moduleBottom output 0x None Configuration extension screens are defining

the Hot Standby configuration


3.1 Mode of FunctioningHot Standby System Configuration via the CHS InstructionProgram the CHS instruction in network 1, segment 1 of your ladder logic program andunconditionally connect the top input to the power rail via a horizontal short (as the HSBYinstruction is programmed in a 984 Hot Standby system)

This method is particularly useful if you are porting Hot Standby code from a 984application to a Quantum application. The structure of the CHS instruction is almostexactly the same as the HSBY instruction. You simply remove the HSBY instruction fromthe 984 ladder logic and replace it with a CHS instruction in the Quantum logic.

If you are using the CHS instruction in ladder logic, the only difference between it and theHSBY instruction is the use of the bottom output. This output senses whether or notmethod 2 has been used. If the Hot Standby configuration extension screens have beenused to define the Hot Standby configuration, the configuration parameters in thescreens will override any different parameters defined by the CHS instruction at systemstartup.

For detailes discussion of the issues related to the configuration extension capabilities ofa Quantum Hot Standby system, refer to the Modicon Quantum Hot Standby SystemPlanning and Installation Guide.

CHS

2058

3.2 Parameter DescriptionExecut Hot Standby (Top Input)When the CHS instruction is inserted in ladder logic to control the Hot Standbyconfiguration parameters, its top input must be connected directly to the power rail by ahorizontal short. No control logic, such as contacts, should be placed between the railand the input to the top node.

WarningAlthough it is legal to enable and disable the nontransfer area while the HotStandby system is running, we strongly discourage this practice. It can lead toerratic behavior in the Hot Standby system.

Command Register (Top Node)The 4x register entered in the top node is the Hot Standby command register; eight bitsin this register are used to configure and control Hot Standby system parameters:

1 2 3 4 5 6 7 8 12 13 14 15 16

0 = Swap Modbus port 3 address during switchover1 = Do not swap Modbus port 3 address during switchover


9 10 11


Disable keyswitch override = 0Enable keyswitch override = 1

Controller A in OFFLINE mode = 0Controller A in RUN mode = 1

Controller B in OFFLINE mode = 0Controller B in RUN mode = 1

Force standby offline if there is a logic mismatch = 0Do not force standby offline if there is a logic mismatch = 1

Allow exec upgrade only after application stops = 0Allow exec upgrade without stopping application = 1

12

The Hot Standby command register must be outside of the nontransfer area of stateRAM.

STOP

CHS

59


20

Nontransfer Area (Middle Node)The 4x register entered in the middle node is the first register in the nontransfer area ofstate RAM. The nontransfer area must contain at least four registers, the first three ofwhich have a predefined usage:

Register ContentDisplayed and first implied Reverse transfer registers for passing information from the

standby to the primary PLCSecond implied CHS status register, see Figure 1

The content of the remaining registers is application-specific; the length is defined in theparameter ”length” (bottom node).

Figure 1 CHS Status Register

1 2 3 4 5 6 7 8 12 13 14 15 169 10 11

This PLC in OFFLINE mode =This PLC running in primary mode =This PLC running in standby mode =

0 101

1 1

0 101

1 1

The other PLC in OFFLINE mode =The other PLC running in primary mode =

The other PLC running in standby mode =

10PLCs have matching logic =

PLCs do not have matching logic =

1This PLC’s switch set to B =0This PLC’s switch set to A =

1 = middle output ON (indicating an error condition)

1 = top output ON (indicating Hot Standby system is running)

The 4x registers in the nontransfer area are never transferred from the primary to thestandby PLC during the logic scans. One reason for scheduling additional registers in thenontransfer area is to reduce the impact of state RAM transfer on the total system scantime.

CKSM

2060

CKSMCheck Sum

1 Brief Description

Several PLCs that do not support Modbus Plus come with a standard checksum (CKSM)instruction. CKSM has the same opcode as the MSTR instruction and is not provided inexecutive firmware for PLCs that support Modbus Plus.

2 Representation

2.1 Symbol

source

CKSM

length

result/count



Data Type Meaning

Top input 0x, 1x None Initiates checksum calculation of source table

Middle input 0x,1x None Cksm select 1Bottom input 0x, 1x None Cksm select 2source(top node)

4x INT; UINT First holding register in the source table. Thechecksum calculation is performed on the regi-sters in this table.

result/count(middle node)

4x INT, UINT First of two contiguous registers

length(bottom node)

INT Number of 4x registers in the source table;range: 1 ... 255

Top output 0x None ON = calculation successfulBottom output 0x None ON = implied register count > length or implied

register count =0

CKSM

61


20


3.1 Parameter DescriptionInputsThe states of the inputs indicate the type of checksum calculation to be performed:

CKSM Calculation Top Input Middle Input Bottom InputStraight Check ON OFF ONBinary Addition Check ON ON ONCRC–16 ON ON OFFLRC ON OFF OFF

Result / Count (Middle Node)The 4x register entered in the middle node is the first of two contiguous 4x registers.

� The displayed register stores the result of the checksum calculation� The implied register posts a value that specifies the number of registers selected

from the source table as input to the calculation; the value posted in the impliedregister must be <= length of source table

CMPR

2062

CMPRCompare Register

1 Brief Description

The CMPR instruction compares the bit pattern in matrix a against the bit pattern inmatrix b for miscompares. In a single scan, the two matrices are compared bit position bybit position until a miscompare is found or the end of the matrices is reached (withoutmiscompares).

2 Representation

2.1 Symbol

matrix a

CMPR

length

pointerregister

CMPR

63


20



Data Type Meaning

Top input 0x, 1x None ON = intiiates compare operation

Middle input 0x, 1x None OFF = restart at last miscompareON = restart at the beginning

matrix a(top node)

0x, 1x, 3x, 4x ANY_BIT First reference in matrix a, one of the two ma-trices to be compared

pointer regi-ster(midlle node)

4x WORD Pointer to matrix b: the first register in matrix bis the next contiguous 4x register following thepointer register

length(bottom node)

INT, UINT Matrix length; range: 1 ... 100

Top output 0x None Echoes state of the top inputMiddle output 0x None ON = miscompare detectedBottom output 0x None ON = miscompared bit in matrix a is 1

OFF = miscompared bit in matrix a is 0


3.1 Parameter DescriptionPointer Register (Middle Node)The pointer register entered in the middle node must be a 4x holding register. It is thepointer to matrix b, the other matrix to be compared. The first register in matrix b is thenext contiguous 4x register following the pointer register.

The value stored inside the pointer register increments with each bit position in the twomatrices that is being compared. As bit position 1 in matrix a and matrix b is compared,the pointer register contains a value of 1; as bit position 2 in the matrices are compared,the pointer value increments to 2; etc.

When the outputs signal a miscompare, you can check the accumulated count in thepointer register to determine the bit position in the matrices of the miscompare.

Matrix Length (Bottom Node)The integer value entered in the bottom node specifies a length of the two matrices, i.e.the number of registers or 16-bit words in each matrix. (Matrix a and matrix b have thesame length.) The matrix length can range from 1 ... 100, i.e. a length of 2 indicates thatmatrix a and matrix b contain 32 bits.

COMP

2064

COMPComplement a Matrix

1 Brief Description

The COMP instruction complements the bit pattern, i.e. changes all 0’s to 1’s and all 1’sto 0’s, of a source matrix, then copies the complemented bit pattern into a destinationmatrix. The entire COMP operation is accomplished in one scan.

WarningCOMP will override any disabled coils in the destination matrix without enablingthem. This can cause injury if a coil has been disabled for repair or maintenancebecause the coil’s state can be changed by the COMP operation.

2 Representation

2.1 Symbol

source

COMP

length

destination

STOP

COMP

65


20



Data Type Meaning

Top input 0x, 1x None ON = initiates the complement operation

source(top node)

0x, 1x, 3x, 4x ANY_BIT First reference in the source matrix,which contains the original bit patternbefore the complement operation

destination(middle node)

0x, 4x ANY_BIT First reference in the destination matrixwhere the complemented bit pattern willbe posted

length(bottom node)

INT, UINT Matrix length; range: 1 ... 100.



3.1 Parameter DescriptionMatrix Length (Bottom Node)The integer value entered in the bottom node specifies a matrix length, i.e. the number ofregisters or 16-bit words in the matrices. Matrix length can range from 1 ... 100. A lengthof 2 indicates that 32 bits in each matrix will be complemented.

DCTR

2066

DCTRDown Counter

1 Brief Description

The DCTR instruction counts control input transitions from OFF to ON down from acounter preset value to zero.

2 Representation

2.1 Symbol

DCTR

counter

accumulated

preset

count



Data Type Meaning

Top input 0x, 1x None OFF → ON = initiates the counter operation

Bottom input 0x, 1x None OFF = accumulated count is reset to presetvalueON = counter accumulating

counter pre-set(top node)

3x, 4x INT, UINT, Preset value, can be displayed explicitly as aninteger (range 1 ... 65 535) or stored in a regi-ster

accumulatedcount(bottom node)

4x INT, UINT Count value (actual value); which decrementsby one on each transition from OFF to ON ofthe top input until it reaches zero.

Top output 0x None ON = accumulated count = 0Bottom output 0x None ON = accumulated count > 0

DIOH

67


20

DIOHDistributed I/O Health

1 Brief Description

The DIOH instruction lets you retrieve health data from a specified group of drops on thedistributed I/O network. It accesses the DIO health status table, where health data formodules in up to 189 distributed drops is stored.

2 Representation

2.1 Symbol

source

DIOH

length

destination

(1 ... 192)



Data Type Meaning

Top input 0x, 1x None ON = initiates the retrieval of the specified sta-tus words from the DIO health table into thedestination table

source(top node)

INT, UINT Source value (four–digit constant in the formxxyy)

destination(middle node)

4x INT, UINT,WORD

First holding register in the destination table,i.e. in a block of contiguous registers wherethe retrieved health status information is stored

Length(bottom node)

INT, UINT Length of the destination table, range 1 ... 64

Top output 0x None Echoes the state of the top inputBottom output 0x None ON = invalid source entry

DIOH

2068


3.1 Parameter DescriptionSource Value (Top Node)The source value entered in the top node is a four-digit constant in the form xxyy,where:

� xx is a decimal value in the range 00 ... 16, indicating the slot number in which therelevant DIO processor resides. The value 00 can always be used to indicate theModbus Plus ports on the PLC, regardless of the slot in which it resides

� yy is a decimal value in the range 1 ... 64, indicating the drop number on theappropriate token ring.

For example, if you are interested in retrieving drop status starting at distributed drop #1on a network being handled by a DIO processor in slot 3, enter 0301 in the top node.

Length of Destination Table (Bottom Node)The integer value entered in the bottom node specifies the length, i.e. the number of 4xregisters, in the destination table. The length is in the range 1 ... 64

NoteIf you specify a length that excedes the number of registers available, the instruction willreturn status information only for the registers available. For example, if you specify the63rd word in the DIOH health status table in the middle node register and then request alength of 5, the instruction will give you only two registers (the 63rd and 64th statuswords) in the destination table.

DIV

69


20

DIVDivide

1 Brief Description

The DIV instruction divides unsigned value 1 (its top node) by unsigned value 2 (itsmiddle node) and posts the quotient and remainder in two contiguous holding registers inthe bottom node.

2 Representation

2.1 Symbol

value 1

DIV

result/

value 2

remainder

DIV

2070



Data Type Meaning

Top input 0x, 1x None ON = value 1 divided by value 2

Middle input 0x, 1x None ON = decimal remainderOFF = fraction remainder

value 1(top node)

3x, 4x INT, UINT Dividend, can be displayed explicitly as an in-teger (range 1 ... 9 999) or stored in two conti-guous registers (displayed for high–order half,implied for low–order half)


3x, 4x INT, UINT Divisor, can be displayed explicitly as an inte-ger (range 1 ... 9 999) or stored in a register

result /re-mainder(bottom node)

4x INT, UINT First of two contiguous holding registers: displayed: result of divisionimplied: remainder (either a decimal or a frac-tion, depending on the state of middle input)

Top output 0x None ON = division successfulMiddle output 0x None ON = overflow:

if result > 9 999, a 0 value is returnedBottom output 0x None ON = value 2 = 0

Quotient of Instruction DIV

The state of the middle input indicates whether the remainder will be expressed as adecimal or as a fraction. For example, if value 1 = 8 and value 2 = 3, the decimalremainder (middle input ON) is 6666; the fractional remainder (middle input OFF) is 2.

Example

DLOG

71


20

DLOGData Logging for PCMCIA Read/Write Support

NoteThis instruction is only available with the PLC family TSX Compact.

1 Brief Description

PCMCIA read and write support consists of a configuration extension to be implementedusing a DLOG instruction. The DLOG instruction provides the facility for an application tocopy data to a PCMCIA flash card, copy data from a PCMCIA flash card, erase individualmemory blocks on a PCMCIA flash card, and to erase an entire PCMCIA flash card. Thedata format and the frequency of data storage are controlled by the application.

NoteThe DLOG instruction will only operate with PCMCIA linear flash cards that use AMDflash devices.

2 Representation

2.1 Symbol

control

DLOG

length

data

block

area

DLOG

2072



Data Type Meaning

Top input 0x, 1x None ON = DLOG operation enabled, it should re-main ON until the operation has completedsuccessfully or an error has occurred.

Middle input 0x, 1x None ON = stops the currently active operationcontrol block(top node)

4x INT, UINT First of five contiguous registers in the DLOGcontrol block

data area(middle node)

4x INT, UINT First 4x register in a data area used for thesource or destination of the specified operation

length(bottom node)

INT, UINT Maximum number of registers reserved for thedata area, range: 0 ... 100.

Top output 0x None Echoes state of the top inputMiddle output 0x None ON = error during DLOG operation (operation

terminated unsuccessfully)Bottom output 0x None ON = DLOG operation finishes successfully

(operation successful)

DLOG

73


20


3.1 Parameter DescriptionControl Block (Top Node)The 4x register entered in the top node is the first of five contiguous registers in theDLOG control block. The control block defines the function of the DLOG command, thePCMCIA flash card window and offset, a return status word, and a data word countvalue.

Register Function Content

Displayed Error Status Displays DLOG errors in HEX values

First implied Operation Type 1 = Write to PCMCIA Card; 2 = Read to PCMCIA Card ;3 = Erase One Block; 4 = Erase Entire Card Content

Second implied Window(Block Identifier)

This register identifies a particular block (PCMCIAmemory window) located on the PCMCIA card(1 block=128k bytes)The number of blocks are dependent on the memory sizeof the PCMCIA card. (e.g.. 0 ... 31 Max. for a 4MegPCMCIA card).

Third implied Offset(Byte Addresswithin the Block)

Particular range of bytes located within a particular blockon the PCMCIA card.Range: 1 ... 128k bytes

Fourth implied Count Number of 4x registers to be written or read to thePCMCIA card. Range: 0 ... 100.

NotePCMCIA Flash Card address are address on a Window:Offset basis. Windows have aset size of 128k bytes (65.535 words (16–bit values)). No Write or Read operation cancross the boundary from one window to the next. Therefore, offset (third implied register)plus length (fourth implied register) must always be less or equal to 128k bytes (65.535words).

Data Area (Middle Node)The 4x register entered in the middle node is the first register in a contiguous block of 4xword registers, that the DLOG instruction will use for the source or destination of theoperation specified in the top node’s control block.

Operation State RamReference

Function

Write 4x Source Address

Read 4x Destination Address

Erase Block none None

Erase Card none None

DLOG

2074

Length (Bottom Node)The integer value entered in the bottom node is the length of the data area — i.e., themaximum number of words (registers) allowed in a transfer to/from the PCMCIA flashcard. The length can range from 0 ... 100.

3.2 Error CodesThe displayed register of the control block contains the following DLOG errors inHex–code:

Table 1 Hex Error Codes DLOG

Error Code in Hex Content1 The count parameter of the control block > the DLOG block length during

a WRITE operation (01)2 PCMCIA card operation failed when intially started (write/read/erase)3 PCMCIA card operation failed during execution (write/read/erase)

DRUM

75


20

DRUMDRUM Sequencer


1 Brief Description

The DRUM instruction operates on a table of 4x registers containing data representingeach step in a sequence. The number of registers associated with this step data tabledepends on the number of steps required in the sequence. You can pre–allocateregisters to store data for each step in the sequence, thereby allowing you to add futuresequencer steps without having to modify application logic.

DRUM incorporates an output mask that allows you to selectively mask bits in theregister data before writing it to coils. This is particularly useful when all physicalsequencer outputs are not contiguous on the output module. Masked bits are not alteredby the DRUM instruction, and may be used by logic unrelated to the sequencer.

2 Representation

2.1 Symbol

step

DRUM

length

step data

pointer

table

DRUM

2076



Data Type Meaning

Top input 0x, 1x None ON = initiates DRUM sequencer

Middle input 0x, 1x None ON = step pointer increments to next stepBottom input 0x, 1x None ON = reset step pointer to 0step pointer(top node)

4x INT, UINT Current step number

step data ta-ble(middle node)

4x INT, UINT First register in a table of step data information

length(bottom node)

INT, UINT Number of application–specific registers–usedin the step data table, range: 1 .. 999

Top output 0x None Echos state of the top inputMiddle output 0x None ON = step pointer value = lengthBottom output 0x None ON = Error


3.1 Parameter DescriptionStep Pointer (Top Node)The 4x register entered in the top node stores the current step number. The value in thisregister is referenced by the DRUM instruction each time it is solved. If the middle inputto the block is ON, the contents of the register in the top node are incremented to thenext step in the sequence before the block is solved

DRUM

77


20

Step Data Table (Middle Node)The 4x register entered in the middle node is the first register in a table of step datainformation. The first six registers in the step data table hold constant and variable datarequired to solve the block:

Register Name Content

Displayed masked output data Loaded by DRUM each time the block is solved;contains the contents of the current step dataregister masked with the outputmask register

First implied current step data Loaded by DRUM each time the block is solved;contains data from the step pointer, causes theblock logic to automatically calculate registeroffsets when accessing step data in the step datatable

Second implied output mask Loaded by user before using the block, DRUMwill not alter output mask contents during logicsolve; contains a mask to be applied to the datafor each sequencer step

Third implied machine ID number Identifies DRUM/ICMP blocks belonging to aspecific machine configuration; value range: 0 ...9 999 (0 = block not configured); all blocksbelonging to same machine configuration havethe same machine ID number

Fourth implied profile ID number Identifies profile data currently loaded to thesequencer; value range: 0... 9 999 (0 = block notconfigured); all blocks with the same machine IDnumber must have the same profile ID number

Fifth implied steps used Loaded by user before using the block, DRUMwill not alter steps used contents during logicsolve; contains between 1 ... 999 for 24 bit CPUs,specifying the actual number of steps to besolved; the number must be 2 table length in thebottom node

The remaining registers contain data for each step in the sequence.

Length (Bottom Node)The integer value entered in the bottom node is the length—i.e., the number ofapplication–specific registers–used in the step data table. The length can range from1 ... 999 in a 24–bit CPU.

The total number of registers required in the step data table is the length + 6. The lengthmust be greater or equal to the value placed in the steps used register in the middlenode.

DV16

2078

DV16Divide 16 Bit

1 Brief Description

The DV16 instruction performs a signed or unsigned division on the 16-bit values in thetop and middle nodes (value 1 / value 2), then posts the quotient and remainder in twocontiguous 4x holding registers in the bottom node.

2 Representation

2.1 Symbol

value 1

DV16

quotient

value 2

DV16

79


20



Data Type Meaning

Top input 0x, 1x None ON = enables value 1 / value 2

Middle input 0x, 1x None OFF = decimal remainderON = fractional remainder


value 1(top node)

3x, 4x INT, UINT, Dividend, can be displayed explicitly as an in-teger (range 1 ... 65 535) or stored in two con-tiguous registers (displayed for high–order half,implied for low–order half)


3x, 4x INT, UINT Divisor, can be displayed explicitly as an inte-ger (range 1 ... 65 535, enter e.g. #65535)or stored in a register

quotient(bottom node)

4x INT, UINT First of two contiguous holding registers: displayed: result of divisionimplied: remainder (either a decimal or a frac-tion, depending on the state of middle input)

Top output 0x None ON = Divide operation completed successfullyMiddle output 0x None ON = overflow:

quotient > 65 535 in unsigned operation–32 768 > quotient > 32 767 in signed opera-tion

Bottom output 0x None ON = value 2 = 0

Quotient of Instruction DV16

The state of the middle input indicates whether the remainder will be expressed as adecimal or as a fraction. For example, if value 1 = 8 and value 2 = 3, the decimalremainder (middle input OFF) is 6666; the fractional remainder (middle input ON) is 2.

Example

EMTH

2080

EMTHExtended Math

1 Brief Description

This instruction accesses a library of double-precision math, square root and logarithmcalculations and floating point (FP) arithmetic functions.

The EMTH instruction allows you to select from a library of 38 extended math functions.Each of the functions has an alphabetical indicator of variable subfunctions that can beselected from a pulldown menu in your panel software and appears in the bottom node.EMTH control inputs and outputs are function-dependent.

2 Representation

2.1 Symbol

topTop input

Middle input

Bottom input

Top output

Middle output

Bottom outputEMTH

subfunction

middle

node

node

EMTH

81


20



Data Type Meaning

Top input 0x, 1x None Depends on the EMTH function you select,see Table 1

Middle input 0x, 1x None Depends on the EMTH function you selectBottom input 0x, 1x None Depends on the EMTH function you selecttop node 3x, 4x DINT, UDINT,

REALTwo consecutive registers, usually 4x holdingregisters but, in the integer math cases, either4x or 3x registers

middle node 4x DINT, UDINT,REAL

Two, four, or six consecutive registers, depen-ding on the function you are implementing.

subfunction(bottom node)

An alphabetical lable, identifing the EMTHfunction, see Table 1

Top output 0x None Depends on the EMTH function you select,see Table 1

Middle output 0x None Depends on the EMTH function you selectBottom output 0x None Depends on the EMTH function you select


3.1 Parameter DescriptionInputs, Outputs and Bottom NodeThe implementation of inputs to and outputs from the block depends on the EMTHfunction you select. An alphabetical indicator of variable subfunctions appears in thebottom node identifing the EMTH function you have chosen from the library.

EMTH

2082

Table 1 EMTH Function (Indicator)

EMTH Function Subfunction Active Inputs Active OutputsDouble Precision MathAddition ADDDP Top Top and MiddleSubtraction SUBDP Top Top, Middle and BottomMultiplication MULDP Top Top and MiddleDivision DIVDP Top and Middle Top, Middle and BottomInteger MathSquare root SQRT Top Top and MiddleProcess square root SQRTP Top Top and MiddleLogarithm LOG Top Top and MiddleAntilogarithm ANLOG Top Top and MiddleFloating Point MathInteger-to-FP conversion CNVIF Top TopInteger + FP ADDIF Top TopInteger – FP SUBIF Top TopInteger x FP MULIF Top TopInteger / FP DIVIF Top TopFP – Integer SUBFI Top TopFP / Integer DIVFI Top TopInteger-FP comparison CMPIF Top TopFP-to-Integer conversion CNVFI Top Top and MiddleAddition ADDFP Top TopSubtraction SUBFP Top TopMultiplication MULFP Top TopDivision DIVFP Top TopComparison CMPFP Top Top, Middle and BottomSquare root SQRFP Top TopChange sign CHSIN Top Top

Load Value of � PI Top TopSine in radians SINE Top TopCosine in radians COS Top TopTangent in radians TAN Top TopArcsine in radians ARSIN Top TopArccosine in radians ARCOS Top TopArctangent in radians ARTAN Top TopRadians to degrees CNVRD Top TopDegrees to radians CNVDR Top TopFP to an integer power POW Top TopExponential function EXP Top TopNatural log LNFP Top TopCommon log LOGFP Top TopReport errors ERLOG Top Top and Middle

EMTH

83


20

3.2 Floating Point EMTH FunctionsTo make use of the floating point (FP) capability, the four-digit integer values used instandard math instructions must be converted to the IEEE floating point format. Allcalculations are then performed in FP format and the results must be converted back tointeger format.

The IEEE Floating Point StandardEMTH floating point functions require values in 32-bit IEEE floating point format. Eachvalue has two registers assigned to it, the eight most significant bits representing theexponent and the other 23 bits (plus one assumed bit) representing the mantissa and thesign of the value.

NoteFloating point calculations have a mantissa precision of 24 bits, which guarantees theaccuracy of the seven most significant digits. The accuracy of the eighth digit in an FPcalculation can be inexact.

It is virtually impossible to recognize a FP representation on the programming panel.Therefore, all numbers should be converted back to integer format before you attempt toread them.

Dealing with Negative Floating Point NumbersStandard integer math calculations do not handle negative numbers explicitly. The onlyway to identify negative values is by noting that the SUB function block has turned thebottom output ON.

If such a negative number is being converted to floating point, perform the Integer-to-FPconversion (EMTH function CNVIF), then use the Change Sign function (EMTH functionCHSIN) to make it negative prior to any other FP calculations.

EMTH–ADDDP

2084

EMTH–ADDDPDouble Precision Addition

1 Brief Description

NoteThis instruction is a subfunction of the EMTH instruction. It belongs to the category”Double Precision Math”.

2 Representation

2.1 Symbol

operand 1

EMTH

ADDDP

operand 2and sum



Data Type Meaning

Top input 0x, 1x None ON = adds operands and posts sum in desi-gnated registers

operand 1(top node)

4x DINT, UDINT Operand 1 (first of two contiguous registers)

operand 2and sum(middle node)

4x DINT, UDINT Operand 2 and sum (first of six contiguous re-gisters)

ADDDP(bottom node)

Selection of the subfunction ADDDP

Top output 0x None ON = operation successfulMiddle output 0x None ON = operand out of range or invalid

EMTH–ADDDP

85


20


3.1 Parameter DescriptionOperand 1 (Top Node)The first of two contiguous 4x registers is entered in the top node. The second 4x registeris implied. Operand 1 is stored here.

Each register holds a value in the range 0 000 ... 9 999, for a combined double precisionvalue in the range 0 ... 99 999 999. The low-order half of operand 1 is stored in thedisplayed register, and the high-order half is stored in the implied register.

Operand 2 and Sum (Middle Node)The first of six contiguous 4x registers is entered in the middle node. The remaining fiveregisters are implied:

� The displayed register and the first implied register store the low-order andhigh-order halves of operand 2, respectively, for a combined double precision valuein the range 0 ... 99 999 999

� The value stored in the second implied register indicates whether an overflowcondition exists (a value of 1 = overflow)

� The third and fourth implied registers store the low-order and high-order halves ofthe double precision sum, respectively

� The fifth implied register is not used in the calculation but must exist in state RAM

EMTH–ADDFP

2086

EMTH–ADDFPFloating Point Addition

1 Brief Description

NoteThis instruction is a subfunction of the EMTH instruction. It belongs to the category”Floating Point Math”.

2 Representation

2.1 Symbol

value 1

EMTH

ADDFP

value 2and sum



Data Type Meaning

Top input 0x, 1x None ON = enables FP addition

value 1(top node)

4x REAL Floating point value 1 (first of two contiguousregisters)

value 2 andsum(middle node)

4x REAL Floating point value 2 and the sum (first of fourcontiguous registers)

ADDFP(bottom node)

Selection of the subfunction ADDFP

Top output 0x None ON = operation successful

EMTH–ADDFP

87


20


3.1 Parameter DescriptionFloating Point Value 1 (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. FP value 1 in the addition is stored here.

Floating Point Value 2 and Sum (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. FP value 2 is stored in the displayed register and the firstimplied register. The sum of the addition is stored in FP format (see page 83) in thesecond and third implied registers.

EMTH–ADDIF

2088

EMTH–ADDIFInteger + Floating Point Addition

1 Brief Description


2 Representation

2.1 Symbol

integer

EMTH

ADDIF

FP andsum



Data Type Meaning

Top input 0x, 1x None ON = initiates integer + FP operation

integer(top node)

4x DINT, UDINT Integer value (first of two contiguous registers)

FP and sum(middle node)

4x REAL FP value and sum (first of four contiguous regi-sters)

ADDIF(bottom node)

Selection of the subfunction ADDIF


EMTH–ADDIF

89


20


3.1 Parameter DescriptionInteger Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The double precision integer value to be added to the FP value is stored here.

FP Value and Sum (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The displayed register and the first implied register store theFP value to be added in the operation, and the sum is posted in the second and thirdimplied registers. The sum is posted in FP format (see page 83).

EMTH–ANLOG

2090

EMTH–ANLOGBase 10 Antilogarithm

1 Brief Description

NoteThis instruction is a subfunction of the EMTH instruction. It belongs to the category”Integer Math”.

2 Representation

2.1 Symbol

source

EMTH

ANLOG

result



Data Type Meaning

Top input 0x, 1x None ON = enables antilog(x) operation

source(top node)

3x, 4x INT, UINT Source value

result(middle node)

4x DINT, UDINT Result (first of two contiguous registers)

ANLOG(bottom node)

Selection of the subfunction ANLOG

Top output 0x None ON = operation successfulMIddle output 0x None ON = an error or value out of range

EMTH–ANLOG

91


20


3.1 Parameter DescriptionSource Value (Top Node)The top node is a single 4x holding register or 3x input register. The source value, i.e. thevalue on which the antilog calculation will be performed, is stored here in the fixeddecimal format 1.234. It must be in the range 0 ... 7 999, representing a source value upto a maximum of 7.999.

Result (Middle Node)The first of two contiguous 4x registers is entered in the middle node. The secondregister is implied. The result of the antilog calculation is posted here in the fixed decimalformat 12345678.

The most significant bits are posted in the displayed register, and the least significant bitsare posted in the implied register. The largest antilog value that can be calculated is99770006 (9977 posted in the displayed register and 0006 posted in the impliedregister).

EMTH–ARCOS

2092

EMTH–ARCOSFloating Point Arc Cosine of an Angle (in Radians)

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

ARCOS

arc cosineof value



Data Type Meaning

Top input 0x, 1x None ON = calculates arc cosine of the value

value(top node)

4x REAL FP value indicating the cosine of an angle (firstof two contiguous registers)

arc cosine ofvalue(middle node)

4x REAL Arc cosine in radians of the value in the topnode (first of four contiguous registers)

ARCOS(bottom node)

Selection of the subfunction ARCOS


EMTH–ARCOS

93


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. An FP value indicating the cosine of an angle between 0 ... p radians is storedhere. This value must be in the range of –1.0 ... +1.0; if not:

� The arc cosine is not computed� An invalid result is returned� An error is flagged in the EMTH–ERLOG function (see page 122)

Arc Cosine of Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The arc cosine in radians of the FP value in the top node is posted in the second andthird implied registers. The displayed register and the first implied register are not usedbut their allocation in state RAM is required.

TipTo preserve registers, you can make the 4x reference numbers assigned to the displayedregister and the first implied register in the middle node equal to the register referencesin the top node, since the first two middle-node registers are not used.

EMTH–ARSIN

2094

EMTH–ARSINFloating Point Arcsine of an Angle (in Radians)

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

ARSIN

arcsine ofvalue



Data Type Meaning

Top input 0x, 1x None ON = calculates the arcsine of the value

value(top node)

4x REAL FP value indicating the sine of an angle (first oftwo contiguous registers)

arcsine of va-lue(middle node)

4x REAL Arcsine of the value in the top node (first offour contiguous registers)

ARSIN(bottom node)

Selection of the subfunction ARSIN


EMTH–ARSIN

95


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. An FP value indicating the sine of an angle between –�/2 ... �/2 radians is storedhere. This value (the sine of an angle) must be in the range of –1.0 ... +1.0; if not:

� The arcsine is not computed� An invalid result is returned� An error is flagged in the EMTH–ERLOG function (see page 122)

Arcsine of Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The arcsine of the value in the top node is posted in the second and third impliedregisters in FP format (see page 83) The displayed register and the first implied registerare not used but their allocation in state RAM is required.


EMTH–ARTAN

2096

EMTH–ARTANFloating Point Arc Tangent of an Angle (in Radians)

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

ARTAN

arc tangentof value



Data Type Meaning

Top input 0x, 1x None ON = calculates the arc tangent of the value

value(top node)

4x REAL FP value indicating the tangent of an angle(first of two contiguous registers)

arc tangent ofvalue(middle node)

4x REAL Arc tangent of the value in the top node (first offour contiguous registers)

ARTAN(bottom node)

Selection of the subfunction ARTAN


EMTH–ARTAN

97


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. An FP value indicating the tangent of an angle between –�/2 ... �/2 radians isstored here. Any valid FP value is allowed.

Arc Tangent of Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The arc tangent in radians of the FP value in the top node is posted in the second andthird implied registers. The displayed register and the first implied register are not usedbut their allocation in state RAM is required.


EMTH–CHSIN

2098

EMTH–CHSINChanging the Sign of a Floating Point Number

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

CHSIN

–(value)


Parameter State RAMReference

Data Type Meaning

Top input 0x, 1x None ON = changes the sign of FP value

value(top node)

4x REAL Floating point value (first of two contiguousregisters)

– (value)(middle node)

4x REAL Floating point value with changed sign (first offour contiguous registers)

CHSIN(bottom node)

Selection of the subfunction CHSIN


EMTH–CHSIN

99


20


3.1 Parameter DescriptionFloating Point Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The FP value whose sign will be changed is stored here.

Floating Point Value with changed sign (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The top node FP value in the top node is posted in the second and third impliedregisters. The displayed register and the first implied register in the middle node are notused in the operation but their allocation in state RAM is required.


EMTH–CMPFP

20100

EMTH–CMPFPFloating Point Comparison

1 Brief Description


2 Representation

2.1 Symbol

value 1

EMTH

CMPFP

value 2



Data Type Meaning

Top input 0x, 1x None ON = initiates comparison

value 1(top node)

4x DINT, UDINT First floating point value (first of two contiguousregisters)


4x REAL Second floating point value (first of four conti-guous registers)

CMPFP(bottom node)

Selection of the subfunction CMPFP

Top output 0x None ON = operation successfulMiddle output 0x None ON = value 1 > value 2 when the bottom out-

put is OFFBottom output 0x None ON = value 1 < value 2 when the middle output

is OFF

EMTH–CMPFP

101


20


3.1 Mode of FunctioningWhen EMTH function CMPFP compares its two FP values, the combined states of themiddle and the bottom output indicate their relationship:

Middle Output Bottom Output RelationshipON OFF value 1 > value 2OFF ON value 1 < value 2ON ON value 1 = value 2

3.2 Parameter DescriptionValue 1 (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The first FP value (value 1) to be compared is stored here.

Value 2 (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The second FP value (value 2) to be compared is entered inthe displayed register and the first implied register; the second and third implied registersare not used in the comparison but their allocation in state RAM is required.

EMTH–CMPIF

20102

EMTH–CMPIFInteger–Floating Point Comparison

1 Brief Description


2 Representation

2.1 Symbol

integer

EMTH

CMPIF

FP



Data Type Meaning

Top input 0x, 1x None ON = initiates comparison

integer(top node)


FP(middle node)

4x REAL Floating point value (first of four contiguousregisters)

CMPIF(bottom node)

Selection of the subfunction CMPIF

Top output 0x None ON = operation successfulMiddle output 0x None ON = integer > FP when the bottom output is

OFFBottom output 0x None ON = integer < FP when the middle output is

OFF

EMTH–CMPIF

103


20


1.1 Mode of FunctioningWhen EMTH function CMPIF compares its integer and FP values, the combined statesof the middle and the bottom output indicate their relationship:

Middle Output Bottom Output RelationshipON OFF integer > FPOFF ON integer < FPON ON integer = FP

1.2 Parameter DescriptionInteger Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The double precision integer value to be compared is stored here.

Floating Point Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The FP value to be compared is entered in the displayedregister and the first implied register; the second and third implied registers are not usedin the comparison but their allocation in state RAM is required.

EMTH–CNVDR

20104

EMTH–CNVDRFloating Point Conversion of Degrees to Radians

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

CNVDR

result



Data Type Meaning

Top input 0x, 1x None ON = initiates conversion of value 1 to value 2

value(top node)

4x REAL Value in FP format of an angle in degrees (firstof two contiguous registers)

result(middle node)

4x REAL Converted result (in radians) in FP format (firstof four contiguous registers)

CNVDR(bottom node)

Selection of the subfunction CNVDR


EMTH–CNVDR

105


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The value in FP format (see page 83) of an angle in degrees is stored here.

Result in Radians (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The converted result in FP format (see page 83) of the top-node value (in radians) isposted in the second and third implied registers. The displayed register and the firstimplied register are not used but their allocation in state RAM is required.


EMTH–CNVFI

20106

EMTH–CNVFIFloating Point to Integer Conversion

1 Brief Description


2 Representation

2.1 Symbol

FP

EMTH

CNVFI

integer



Data Type Meaning

Top input 0x, 1x None ON = initiates FP to integer conversion

FP(top node)

4x REAL Floating point value to be converted (first oftwo contiguous registers)

integer(middle node)

4x DINT, UDINT Integer value (first of four contiguous registers)

CNVFI(bottom node)

Selection of the subfunction CNVFI

Top output 0x None ON = operation successfulBottom output 0x None OFF = positive integer value

ON = negative integer value

EMTH–CNVFI

107


20


3.1 Parameter DescriptionInteger Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The double precision integer result of the conversion is stored in the second and thirdimplied registers. This value should be the largest integer value possible that is ≤ the FPvalue. For example, the FP value 3.5 is converted to the integer value 3, while the FPvalue –3.5 is converted to the integer value –4.

The displayed register and the first implied register in the middle node are not used in theconversion but their allocation in state RAM is required.

TipTo preserve registers, you can make the 4x reference numbers assigned to the displayedregister and the first implied register in the middle node equal to the register referencesin the top node, since the first two middle-node registers are not used

4 Runtime Errors

If the resultant integer is too large for double precision integer format (> 99 999 999), theconversion still occurs but an error is logged in the EMTH_ERLOG function (see page122).

EMTH–CNVIF

20108

EMTH–CNVIFInteger–to–Floating Point Conversion

1 Brief Description


2 Representation

2.1 Symbol

integer

EMTH

CNVIF

result



Data Type Meaning

Top input 0x, 1x None ON = initiates integer–to FP conversion

integer(top node)


result(middle node)

4x REAL Result (first of four contiguous registers)

CNVIF(bottom node)

Selection of the subfunction CNVIF


EMTH–CNVIF

109


20


3.1 Parameter DescriptionInteger Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The double precision integer value to be converted to 32-bit FP format (seepage 83) is stored here.

Result (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The FP result of the conversion is posted in the second andthird implied registers. The displayed register and the first implied register are not used inthe function but their allocation in state RAM is required.


4 Runtime Errors

If an invalid integer value ( > 9 999) is entered in either of the two top-node registers, theFP conversion will be performed but an error will be reported and logged in theEMTH–ERLOG function (see page 122). The result of the conversion may not becorrect.

EMTH–CNVRD

20110

EMTH–CNVRDFloating Point Conversion of Radians to Degrees

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

CNVRD

result



Data Type Meaning

Top input 0x, 1x None ON = initiates conversion of value 1 to value 2

value(top node)

4x REAL Value in FP format of an angle in radians (firstof two contiguous registers)

result(middle node)

4x REAL Converted result (in degrees) in FP format(first of four contiguous registers)

CNVRD(bottom node)

Selection of the subfunction CNVRD


EMTH–CNVRD

111


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The value in FP format (see page 83) of an angle in radians is stored here.

Result in Degrees (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The converted result in FP format (see page 83) of the top-node value (in degrees) isposted in the second and third implied registers. The displayed register and the firstimplied register are not used but their allocation in state RAM is required.


EMTH–COS

20112

EMTH–COSFloating Point Cosine of an Angle (in Radians)

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

COS

cosine ofvalue



Data Type Meaning

Top input 0x, 1x None ON = calculates the cosine of the value

value(top node)

4x REAL FP value indicating the value of an angle inradians (first of two contiguous registers)

cosine of va-lue(middle node)

4x REAL Cosine of the value in the top node (first of fourcontiguous registers)

COS(bottom node)

Selection of the subfunction COS


EMTH–COS

113


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. An FP value indicating the value of an angle in radians is stored here. Themagnitude of this value must be < 65 536.0; if not:

� The cosine is not computed� An invalid result is returned� An error is flagged in the EMTH–ERLOG function (see page 122)

Cosine of Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The cosine of the value in the top node is posted in the second and third impliedregisters in FP format (see page 83). The displayed register and the first implied registerare not used but their allocation in state RAM is required.


EMTH–DIVDP

20114

EMTH–DIVDPDouble Precision Division

1 Brief Description


2 Representation

2.1 Symbol

operand 1

EMTH

DIVDP

operand 2quotientremainder



Data Type Meaning

Top input 0x, 1x None ON = operand 1 divided by operand 2 and re-sult posted in designated registers

Middle input 0x, 1x None ON = decimal remainderOFF = fractional remainder

operand 1(top node)


operand 2quotientremainder(middle node)

4x DINT, UDINT Operand 2, quotient and remainder (first of sixcontiguous registers)

DIVDP(bottom node)

Selection of the subfunction DIVDP

Top output 0x None ON = operation successfulMiddle output 0x None ON = an operand out of range or invalidBottom output 0x None ON = operand 2 = 0

EMTH–DIVDP

115


20



Each register holds a value in the range 0000 ... 9 999, for a combined double precisionvalue in the range 0 ... 99 999 999. The low-order half of operand 1 is stored in thedisplayed register, and the high-order half is stored in the implied register.

Operand 2, Quotient and Remainder (Middle Node)The first of six contiguous 4x registers is entered in the middle node. The remaining fiveregisters are implied:


� The second and third implied registers store an eight-digit quotient� The fourth and fifth implied registers store the remainder, if the remainder is

expressed as a fraction, it is eight digits long and both registers are used; if theremainder is expressed as a decimal, it is four digits long and only the fourthimplied register is used

4 Runtime Errors

Since division by 0 is illegal, a 0 value causes an error, an error trapping routine sets theremaining middle-node registers to 0000 and turns the bottom output ON.

EMTH–DIVFI

20116

EMTH–DIVFIFloating Point Divided by Integer

1 Brief Description


2 Representation

2.1 Symbol

FP

EMTH

DIVFI

integer andquotient



Data Type Meaning

Top input 0x, 1x None ON = initiates FP / integer operation

FP(top node)


integer andquotient(middle node)

4x DINT, UDINT Integer value and quotient (first of four contigu-ous registers)

DIVFI(bottom node)

Selection of the subfunction DIVFI


EMTH–DIVFI

117


20


3.1 Parameter DescriptionFloating Point Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The FP value to be divided by the integer value is stored here.

Integer Value and Quotient (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The double precision integer value that divides the FP valueis posted in the displayed register and the first implied register, and the quotient is postedin the second and third implied registers. The quotient is posted in FP format (seepage 83).

EMTH–DIVFP

20118

EMTH–DIVFPFloating Point Division

1 Brief Description


2 Representation

2.1 Symbol

value 1

EMTH

DIVFP

value 2 andqoutient



Data Type Meaning

Top input 0x, 1x None ON = initiates value 1 / value 2 operation

value 1(top node)


value 2 andquotient(middle node)

4x REAL Floating point value 2 and the quotient (first offour contiguous registers)

DIVFP(bottom node)

Selection of the subfunction DIVFP


EMTH–DIVFP

119


20


3.1 Parameter DescriptionFloating Point Value 1 (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. FP value 1, which will be divided by the value 2, is stored here.

Floating Point Value 2 and Quotient (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. FP value 2, the value by which value 1 is divided, is stored inthe displayed register and the first implied register. The quotient is posted in FP format(see page 83) in the second and third implied registers.

EMTH–DIVIF

20120

EMTH–DIVIFInteger Divided by Floating Point

1 Brief Description


2 Representation

2.1 Symbol

integer

EMTH

DIVIF

FP andquotient



Data Type Meaning

Top input 0x, 1x None ON = initiates integer / FP operation

integer(top node)


FP and quo-tient(middle node)

4x REAL FP value and quotient (first of four contiguousregisters)

DIVIF(bottom node)

Selection of the subfunction DIVIF


EMTH–DIVIF

121


20


3.1 Parameter DescriptionInteger Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The double precision integer value to be divided by the FP value is stored here.

FP Value and Quotient (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The displayed register and the first implied register store theFP value to be divided in the operation, and the quotient is posted in the second andthird implied registers. The quotient is posted in FP format (see page 83).

EMTH–ERLOG

20122

EMTH–ERLOGFloating Point Error Report Log

1 Brief Description


2 Representation

2.1 Symbol

not used

EMTH

ERLOG

error data



Data Type Meaning

Top input 0x, 1x None ON = retrieves a log of error types since lastinvocation

not used(top node)

4x INT, UINT,DINT, UDINT,REAL

Not used in the operation (first of two contigu-ous registers)

errror data(middle node)

4x INT, UINT,DINT, UDINT,REAL

Error log register (first of six contiguous regi-sters)

ERLOG(bottom node)

Selection of the subfunction ERLOG

Top output 0x None ON = retrieval successfulMiddle output 0x None ON = nonzero values in error log register

OFF = all zeros in error log register

EMTH–ERLOG

123


20


3.1 Parameter DescriptionNot used (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. These two registers are not used in the operation but their allocation in stateRAM is required.

Error Data (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The second implied register is used as the error log register:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Not UsedFunction Code ofLast Error Logged

If the bit is set to 1, then the specific error condition exists for that bit.

Exponential Function Power too LargeInteger/FP Conversion Error

Invalid FP Value or Operation

FP OverflowFP Underflow

Error Log Register

The third implied register has all its bits cleared to zero. The displayed register and thefirst implied register are not used but their allocation in state RAM is required.

TipTo preserve registers, you can make the 4x reference numbers assigned to the displayedregister and the first implied register in the middle node equal to the register referencesin the top node, since these registers must be allocated but none are used.

EMTH–EXP

20124

EMTH–EXPFloating Point Exponential Function

1 Brief Description

NoteThis instruction is an subfunction of the EMTH instruction. It belongs to the category”Floating Point Math”.

2 Representation

2.1 Symbol

value

EMTH

EXP

result



Data Type Meaning

Top input 0x, 1x None ON = calculates exponential function of thevalue

value(top node)

4x REAL Value in FP format (first of two contiguous regi-sters)

result(middle node)

4x REAL Exponential of the value in the top node (firstof four contiguous registers)

EXP(bottom node)

Selection of the subfunction EXP


EMTH–EXP

125


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. A value in FP format (see page 83) in the range –87.34 ... +88.72 is stored here.

If the value is out of range, the result will either be 0 or the maximum value. No error willbe flagged.

Result (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The exponential of the value in the top node is posted in FP format (see page 83) in thesecond and third implied registers. The displayed register and the first implied registerare not used but their allocation in state RAM is required


EMTH–LNFP

20126

EMTH–LNFPFloating Point Natural Logarithm

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

LNFP

result



Data Type Meaning

Top input 0x, 1x None ON = calculates the natural log of the value

value(top node)

4x REAL Value > 0 in FP format (first of two contiguousregisters)

result(middle node)

4x REAL Natural logarithm of the value in the top node(first of four contiguous registers)

LNFP(bottom node)

Selection of the subfunction LNFP


EMTH–LNFP

127


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. A value > 0 is stored here in FP format (see page 83).

If the value ≤ 0, an invalid result will be returned in the middle node and an error will belogged in the EMTH–ERLOG function (see page 122).


The natural logarithm of the value in the top node is posted in FP format (see page 83) inthe second and third implied registers. The displayed register and the first impliedregister are not used but their allocation in state RAM is required.


EMTH–LOG

20128

EMTH–LOGBase 10 Logarithm

1 Brief Description


2 Representation

2.1 Symbol

source

EMTH

LOG

result



Data Type Meaning

Top input 0x, 1x None ON = enables log(x) operation

source(top node)

3x, 4x DINT, UDINT Source value (first of two contiguous registers)

result(middle node)

4x INT, UINT Result

LOG(bottom node)

Selection of the subfunction LOG

Top output 0x None ON = operation successfulMiddle output 0x None ON = an error or value out of range

EMTH–LOG

129


20


3.1 Parameter DescriptionSource Value (Top Node)The first of two contiguous 3x or 4x registers is entered in the top node. The secondregister is implied. The source value upon which the log calculation will be performed isstored in these registers.

If you specify a 4x register, the source value may be in the range 0 ... 99 999 99. Thelow-order half of the value is stored in the implied register, and the high-order half isstored in the displayed register.

If you specify a 3x register, the source value may be in the range 0 ... 9 999. The logcalculation is done on only the value in the displayed register; the implied register isrequired but not used.

Result (Middle Node)The middle node contains a single 4x holding register where the result of the base 10 logcalculation is posted. The result is expressed in the fixed decimal format 1.234, and istruncated after the third decimal position.

The largest result that can be calculated is 7.999, which would be posted in the middleregister as 7999.

EMTH–LOGFP

20130

EMTH–LOGFPFloating Point Common Logarithm

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

LOGFP

result



Data Type Meaning

Top input 0x, 1x None ON = calculates the common log of the value

value(top node)

4x REAL Value > 0 in FP format (first of two contiguousregisters)

result(middle node)

4x REAL Common log of the value in the top node (firstof four contiguous registers)

LOGFP(bottom node)

Selection of the subfunction LOGFP


EMTH–LOGFP

131


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. A value > 0 is stored here in FP format (see page 83).

If the value ≤ 0, an invalid result will be returned in the middle node and an error will belogged in the EMTH–ERLOG function (see page 122).


The common logarithm of the value in the top node is posted in FP format (see page 83)in the second and third implied registers. The displayed register and the first impliedregister are not used but their allocation in state RAM is required.


EMTH–MULDP

20132

EMTH–MULDPDouble Precision Multiplication

1 Brief Description


2 Representation

2.1 Symbol

operand 1

EMTH

MULDP

operand 2/product



Data Type Meaning

Top input 0x, 1x None ON = operand 1 x operand 2 and product po-sted in designated registers

operand 1(top node)


operand 2 /product(middle node)

4x DINT, UDINT Operand 2 and product (first of six contiguousregisters)

MULDP(bottom node)

Selection of the subfunction MULDP

Top output 0x None ON = operation successfulMiddle output 0x None ON = operand out of range

EMTH–MULDP

133


20



Each register holds a value in the range 0000 ... 9 999, for a combined double precisionvalue in the range 0 ... 99 999 999. The low-order half of operand 1 is stored in thedisplayed register, and the high-order half is stored in the implied register.

Operand 2 and Product (Middle Node)The first of six contiguous 4x registers is entered in the middle node. The remaining fiveregisters are implied:


� The last four implied registers store the double precision product in the range0 ... 9 999 999 999 999 999

EMTH–MULFP

20134

EMTH–MULFPFloating Point Multipliation

1 Brief Description


2 Representation

2.1 Symbol

value 1

EMTH

MULFP

value 2 andproduct



Data Type Meaning

Top input 0x, 1x None ON = initiates FP multiplication

value 1(top node)


value 2 andproduct(middle node)

4x REAL Floating point value 2 and the product (first offour contiguous registers)

MULFP(bottom node)

Selection of the subfunction MULFP


EMTH–MULFP

135


20


3.1 Parameter DescriptionFloating Point Value 1 (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. FP value 1 in the multiplication operation is stored here.

Floating Point Value 2 and Product (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. FP value 2 in the multiplication operation is stored in thedisplayed register and the first implied register. The product of the multiplication is storedin FP format (see page 83) in the second and third implied registers.

EMTH–MULIF

20136

EMTH–MULIFInteger x Floating Point Multiplication

1 Brief Description


2 Representation

2.1 Symbol

integer

EMTH

MULIF

FP andproduct



Data Type Meaning

Top input 0x, 1x None ON = initiates integer–x FP operation

integer(top node)


FP and pro-duct(middle node)

4x REAL FP value and product (first of four contiguousregisters)

MULIF(bottom node)

Selection of the subfunction MULIF


EMTH–MULIF

137


20


3.1 Parameter DescriptionInteger Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The double precision integer value to be multiplied by the FP value is storedhere.

FP Value and Product (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The displayed register and the first implied register store theFP value to be multiplied in the operation, and the product is posted in the second andthird implied registers. The product is posted in FP fomat (see page 83).

EMTH–PI

20138

EMTH–PILoad the Floating Point Value of �

1 Brief Description


2 Representation

2.1 Symbol

not used

EMTH

PI

FP valueof PI



Data Type Meaning

Top input 0x, 1x None ON = loads FP value of � to middle node regi-ster

not used(top node)

4x REAL First of two contiguous registers

FP value of �(middle node)

4x REAL FP value of � (first of four contiguous registers)

PI(bottom node)

Selection of the subfunction PI


EMTH–PI

139


20


3.1 Parameter DescriptionNot used (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. These registers are not used but their allocation in state RAM is required.

Floating Point Value of � (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The FP value of p is posted in the second and third implied registers. The displayedregister and the first implied register are not used but their allocation in state RAM isrequired.


EMTH–POW

20140

EMTH–POWRaising a Floating Point Number to an Integer Power

1 Brief Description


2 Representation

2.1 Symbol

FP value

EMTH

POW

integerand result



Data Type Meaning

Top input 0x, 1x None ON = calculates FP value raised to the powerof integer value

FP value(top node)

4x REAL FP value (first of two contiguous registers)

integer andresult(middle node)

4x INT, UINT Integer value and result (first of four contigu-ous registers)

POW(bottom node)

Selection of the subfunction POW


EMTH–POW

141


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The FP value to be raised to the integer power is stored here.

Integer and Result (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The bit values in the displayed register must all be cleared to zero. An integer valuerepresenting the power to which the top-node value will be raised is stored in the firstimplied register. The result of the FP value being raised to the power of the integer valueis stored in the second and third implied registers.

EMTH–SINE

20142

EMTH–SINEFloating Point Sine of an Angle (in Radians)

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

SINE

sine ofvalue



Data Type Meaning

Top input 0x, 1x None ON = calculates the sine of the value

value(top node)


sine of value(middle node)

4x REAL Sine of the value in the top node (first of fourcontiguous registers)

SINE(bottom node)

Selection of the subfunction SINE


EMTH–SINE

143


20


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. An FP value indicating the value of an angle in radians is stored here. Themagnitude of this value must be < 65 536.0; if not:

� The sine is not computed� An invalid result is returned� An error is flagged in the EMTH–ERLOG function (see page 122)

Sine of Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The sine of the value in the top node is posted in the second and third implied registersin FP format (see page 83). The displayed register and the first implied register are notused but their allocation in state RAM is required.


EMTH–SQRFP

20144

EMTH–SQRFPFloating Point Square Root

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

SQRFP

result



Data Type Meaning

Top input 0x, 1x None ON = initiates square root on FP value

value(top node)


result(middle node)

4x REAL Result in FP format (first of four contiguousregisters)

SQRFP(bottom node)

Selection of the subfunction SQRFP


EMTH–SQRFP

145


20


3.1 Parameter DescriptionFloating Point Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The FP value on which the square root operation is performed is stored here.


The result of the square root operation is posted in FP format (see page 83) in thesecond and third implied registers. The displayed register and the first implied register inthe middle node are not used in the operation but their allocation in state RAM isrequired.


EMTH–SQRT

20146

EMTH–SQRTSquare Root

1 Brief Description


2 Representation

2.1 Symbol

source

EMTH

SQRT

result



Data Type Meaning

Top input 0x, 1x None ON = initiates a standard square root operation

source(top node)


result(middle node)

4x DINT, UDINT Result (first of two contiguous registers)

SQRT(bottom node)

Selection of the subfunction SQRT

Top output 0x None ON = operation successfulMiddle output 0x None ON = source value out of range

EMTH–SQRT

147


20


3.1 Parameter DescriptionSource Value (Top Node)The first of two contiguous 3x or 4x registers is entered in the top node. The secondregister is implied. The source value, i.e. the value for which the square root will bederived, is stored here.

If you specify a 4x register, the source value may be in the range 0 ... 99 999 99. Thelow-order half of the value is stored in the implied register, and the high-order half isstored in the displayed register.

If you specify a 3x register, the source value may be in the range 0 ... 9 999. The squareroot calculation is done on only the value in the displayed register; the implied register isrequired but not used.

Result (Middle Node)Enter the first of two contiguous 4x registers in the middle node. The second register isimplied. The result of the standard square root operation is stored here.

The result is stored in the fixed-decimal format: 1234.5600. where the displayedregister stores the four-digit value to the left of the first decimal point and the impliedregister stores the four-digit value to the right of the first decimal point. Numbers after thesecond decimal point are truncated; no round-off calculations are performed.

EMTH–SQRTP

20148

EMTH–SQRTPProcess Square Root

1 Brief Description


The process square root function tailors the standard square root function for closed loopanalog control applications. It takes the result of the standard square root result,multiplies it by 63.9922 (the square root of 4 095) and stores that linearized result in themiddle-node registers.

2 Representation

2.1 Symbol

source

EMTH

SQRTP

linearizedresult

EMTH–SQRTP

149


20



Data Type Meaning

Top input 0x, 1x None ON = initiates process square root operation

source(top node)


linearized re-sult(middle node)

4x DINT, UDINT LInearized result (first of two contiguous regi-sters)

SQRTP(bottom node)

Selection of the subfunction SQRTP

Top output 0x None ON = operation successfulMIddle output 0x None ON = source value out of range


3.1 Parameter DescriptionSource Value (Top Node)The first of two contiguous 3x or 4x registers is entered in the top node. The secondregister is implied. The source value, i.e. the value for which the square root will bederived, is stored in these two registers. In order to generate values that have meaning,the source value must not exceed 4 095. In a 4x register group the source value willtherefore be stored in the implied register, and in a 3x register group the source value willbe stored in the displayed register.

Linearized Result (Middle Node)The first of two contiguous 4x registers is entered in the middle node. The secondregister is implied. The linearized result of the process square root operation is storedhere.

The result is stored in the fixed-decimal format: 1234.5600. where the displayedregister stores the four-digit value to the left of the first decimal point and the impliedregister stores the four-digit value to the right of the first decimal point. Numbers after thesecond decimal point are truncated; no round-off calculations are performed.

EMTH–SQRTP

20150

Process Square Root Function

Look at the instruction example below for a quick overview of how the process squareroot is calculated.

300030

EMTH

SQRTP

400030

Suppose a source value of 2000 is stored in register 300030 of EMTH function SQRTP.First, a standard square root operation is performed:

2000�� 0044.72

which is then multiplied by 63.9922, yielding a linearized result of 2861.63. The linearizedresult is placed in registers 400030 and 400031 in the middle node of the EMTHinstruction:

� Register 400030 stores the high-order half (2861)� Register 400031 stores the low-order half (6300)

The process square root is often used to linearize signals from differential pressure flowtransmitters so that they may be used as inputs in closed loop control operations.

Example

EMTH–SUBDP

151


20

EMTH–SUBDPDouble Precision Subtraction

1 Brief Description


2 Representation

2.1 Symbol

operand 1

EMTH

SUBDP

operand 2/difference



Data Type Meaning

Top input 0x, 1x None ON = subtracts operand 2 from operand 1 andposts difference in designated registers

operand 1(top node)


operand 2 /difference(middle node)

4x DINT, UDINT Operand 2 and difference (first of six contigu-ous registers)

SUBDP(bottom node)

Selection of the subfunction SUBDP

Top output 0x None ON = operand 1 > operand 2Middle output 0x None ON = operand 1 = operand 2Bottom output 0x None ON = operand 1 < operand 2

EMTH–SUBDP

20152



Each register holds a value in the range 0000 ... 9999, for a combined double precisionvalue in the range 0 ... 99 999 999. The low-order half of operand 1 is stored in thedisplayed register, and the high-order half is stored in the implied register.

Operand 2 and Difference (Middle Node)The first of six contiguous 4x registers is entered in the middle node. The remaining fiveregisters are implied:


� The second and third implied registers store the low-order and high-order halves,respectively, of the absolute difference in double precision format

� The value stored in the fourth implied register indicates whether or not theoperands are in the valid range (1 = out of range and 0 = in range)

� The fifth implied register is not used in the calculation but must exist in state RAM

EMTH–SUBFI

153


20

EMTH–SUBFIFloating Point – Integer Subtraction

1 Brief Description


2 Representation

2.1 Symbol

FP

EMTH

SUBFI

integer anddifference



Data Type Meaning

Top input 0x, 1x None ON = initiates FP – integer operation

FP(top node)


integer anddifference(middle node)

4x DINT, UDINT Integer value and difference (first of four conti-guous registers)

SUBFI(bottom node)

Selection of the subfunction SUBFI


EMTH–SUBFI

20154


3.1 Parameter DescriptionFloating Point Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The FP value from which the integer value is subtracted is stored here.

Integer Value and Difference (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The displayed register and the first implied register store thedouble precision integer value to be subtracted from the FP value, and the difference isposted in the second and third implied registers. The difference is posted in FP format(see page 83).

EMTH–SUBFP

155


20

EMTH–SUBFPFloating Point Subtraction

1 Brief Description

NoteThis instruction is an subfunction of the EMTH instruction. It belongs to the category”Floating Point Math”.

2 Representation

2.1 Symbol

value 1

EMTH

SUBFP

value 2 anddifference



Data Type Meaning

Top input 0x, 1x None ON = initiates FP value 1 – value 2 subtraction

value 1(top node)


value 2 anddifference(middle node)

4x REAL Floating point value 2 and the difference (firstof four contiguous registers)

SUBFP(bottom node)

Selection of the subfunction SUBFP


EMTH–SUBFP

20156


3.1 Parameter DescriptionFloating Point Value 1 (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. FP value 1 (the value from which value 2 will be subtracted) is stored here.

Floating Point Value 2 and Difference (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. FP value 2 (the value to be subtracted from value 1) is storedin the displayed register and the first implied register. The difference of the subtraction isstored in FP format (see page 83) in the second and third implied registers.

EMTH–SUBIF

157


20

EMTH–SUBIFInteger – Floating Point Subtraction

1 Brief Description


2 Representation

2.1 Symbol

integer

EMTH

SUBIF

FP anddifference



Data Type Meaning

Top input 0x, 1x None ON = initiates integer – FP operation

integer(top node)


FP and diffe-rence(middle node)

4x REAL FP value and difference (first of four contigu-ous registers)

SUBIF(bottom node)

Selection of the subfunction SUBIF


EMTH–SUBIF

20158


3.1 Parameter DescriptionInteger Value (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. The double precision integer value from which the FP value is subtracted isstored here.

FP Value and Difference (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied. The displayed register and the first implied register store theFP value to be subtracted from the integer value, and the difference is posted in thesecond and third implied registers. The difference is posted in FP format (see page 83).

EMTH–TAN

159


20

EMTH–TANFloating Point Tangent of an Angle (in Radians)

1 Brief Description


2 Representation

2.1 Symbol

value

EMTH

TAN

tangent ofvalue



Data Type Meaning

Top input 0x, 1x None ON = calculates the tangent of the value

value(top node)


tangent of va-lue(middle node)

4x REAL Tangent of the value in the top node (first offour contiguous registers)

TAN(bottom node)

Selection of the subfunction TAN


EMTH–TAN

20160


3.1 Parameter DescriptionValue (Top Node)The first of two contiguous 4x registers is entered in the top node. The second register isimplied. An FP value indicating the value of an angle in radians is stored here. Themagnitude of this value must be < 65536.0; if not:

� The tangent is not computed� An invalid result is returned� An error is flagged in the EMTH–ERLOG function (see page 122)

Tangent of Value (Middle Node)The first of four contiguous 4x registers is entered in the middle node. The remainingthree registers are implied.

The tangent of the value in the top node is posted in the second and third impliedregisters in FP format (see page 83). The displayed register and the first implied registerare not used but their allocation in state RAM is required.


EUCA

161


20

EUCAEngineering Unit Conversion and Alarms


1 Brief Description

The use of ladder logic to convert binary-expressed analog data into decimal units canbe memory-intensive and scan-time intensive operation. The Engineering UnitConversion and Alarms (EUCA) loadable is designed to eliminate the need for extra userlogic normally required for these conversions. EUCA scales 12 bits of binary data(representing analog signals or other variables) into engineering units that are readilyusable for display, data logging, or alarm generation.

Using Y = mX + b linear conversion, binary values between 0 ... 4095 are converted to ascaled process variable (SPV). The SPV is expressed in engineering units in the range0 ... 9 999.

One EUCA instruction can perform up to four separate engineering unit conversions. Italso provides four levels of alarm checking on each of the four conversions:

� High absolute (HA)� High warning (HW)� Low warning (LW)� Low absolute (LA)

EUCA

20162

2 Representation

2.1 Symbol

alarm

EUCA

nibble#

parametertable

status

(1 ... 4)



Data Type Meaning

Top input 0x, 1x None ON initiates the conversion

Middle input 0x, 1x None Alarm input

Bottom input 0x, 1x None Error input

alarm status(top node)

4x INT, UINT, Alarm status for as many as four EUCA con-versions

parameter ta-ble(middle node)

4x INT, UINT, First of nine contiguous holding registers in theEUCA parameter table

nibble #(1...4)(bottom node)

INT, UINT Integer value,indicates which one of the fournibbles in the alarm status register to use

Top output 0x None Echoes the state of the top inputMiddle output 0x None ON if the middle input is ON or if the result of

the EUCA conversion crosses a warning levelBottom output 0x None ON if the bottom input is ON or if a parameter

is out of range

EUCA

163


20


3.1 Parameter DescriptionAlarm Status (Top Node)The 4x register entered in the top node displays the alarm status for as many as fourEUCA conversions, which can be performed by the instruction. The register issegmented into four four-bit nibbles. Each four-bit nibble represents the four possiblealarm conditions for an individual EUCA conversion. The most significant nibblerepresents the first conversion, and the least significant nibble represents the fourthconversion:

Nibble 1 Nibble 2 Nibble 3 Nibble 4

HA1 HW1 LW1 LA1 HA2 HW2 LW2 LA2 HA3 HW3 LW3 LA3 HA4 HW4 LW4 LA4

(first conversion) (second conversion) (third conversion) (fourth conversion)

� An HA alarm is set when the SPV exceeds the user-defined high alarm valueexpressed in engineering units

� An HW alarm is set when SPV exceeds a user-defined high warning valueexpressed in engineering units

� An LW alarm is set when SPV is less than a user-defined low warning valueexpressed in engineering units

� An LA alarm is set when SPV is less than a user-defined low alarm valueexpressed in engineering units

Only one alarm condition can exist in any EUCA conversion at any given time. If the SPVexceeds the high warning level the HW bit will be set. If the HA is exceeded, the HW bitis cleared and the HA bit is set. The alarm bit will not change after returning to a lesssevere condition until the deadband (DB) area has also been exited.

EUCA

20164

Parameter Table (Middle Node)The 4x register entered in the middle node is the first of nine contiguous holding registersin the EUCA parameter table:

Register Content RangeDisplayed Binary value input by the user 0 ... 4 095First implied SPV calculated by the EUCA blockSecond implied High engineering unit (HEU), maxi-

mum SPV required and set by theuser (top of the scale)

LEU < HEU ≤ 99 999

Third implied Low engineering unit (LEU), mini-mum SPV required and set by theuser (bottom end of the scale)

0 ≤ LEU < HEU

Fourth implied DB area in SPV units, below HAlevels and above LA levels thatmust be crossed before the alarmstatus bit will reset

0 ≤ DB < (HEU – LEU)

Fifth implied HA alarm value in SPV units HW < HA ≤ HEUSixth implied HW alarm value in SPV units LW < HW < HASeventh implied LW alarm value in SPV units LA < LW < HWEighth implied LA alarm value in SPV units LEU ≤ LA < LW

NoteAn error is generated if any value is out of the range defined above

EUCA

165


20

4 Examples

EUCA Example 1

This example demonstrates the principles of EUCA operation. The binary value ismanually input in the displayed register in the middle node, and the result is visuallyavailable in the SPV register (the first implied register in the middle node).

The illustration below shows an input range equivalent of a 0 ... 100 V measure,corresponding to the whole binary 12-bit range:

90

70

60

50

40

30

20

10

0

80

100

V

V

LSBMSB

1 1 1 1 1 1 1 1 1 1 1 1 = 4095 or FFF hex

000000000000 = 0 or 000 hex

unused

(Displayed register in the middle node)

A range of 0 ... 100 V establishes 50 V for nominal operation. EUCA provides a marginon the nominal side of both warning and alarm levels (deadband). If an alarm threshold isexceeded, the alarm bit becomes active and stays active until the signal becomesgreater (or less) than the DB setting—5 V in this example.

Example

EUCA

20166

SetupProgramming the EUCA block is accomplished by selecting the EUCA loadable andwriting in the data as illustrated in the figure below:

# 0001

EUCA

400450

400440

Reference Data400440400450400451400452400453400454400455400456400457400458

STATUSINPUTSPVHIGH_unitLOW_unitDead_BandHIGH_ALARMHIGH_WARNLOW_ALARMLOW_WARN

00000000000000001871 DEC

46 DEC100 DEC

0 DEC5 DEC

70 DEC60 DEC40 DEC30 DEC

The nine middle-node registers are set using the reference data editor. DB is 5 Vfollowed by 10 V increments of high and low warning. The actual high and low alarm isset at 20 V above and below nominal. On a graph, the example looks like this:

90

70

60

50

40

30

20

10

0

80

100

V

V

Normal

= Dead Band

High Warning

High Alarm

Low Warning

Low Alarm

*46

NoteThe example value shows a decimal 46, which is in the normal range. No alarm isset—i.e., register 400440 = 0.

EUCA

167


20

You can now verify the instruction in a running PLC by entering values in register 400450that fall into the defined ranges. The verification is done by observing the bit change inregister 400440 where:

1 = High Alarm

1 = High Warning

1 = Low Warning1 = Low Alarm

EUCA Example 2

If the input of 0 ... 4095 indicates the speed of a drive system of 0 ... 5000 rpm, you couldset up a EUCA instruction as follows:

The binary value in 400210 results in an SPV of 4835 decimal, which exceeds the highabsolute alarm level, sets the HA bit in 400209, and powers the EUCA alarm node.

Maximum Speed 5 000 rpmMinimum Speed 0 rpmDB 100 rpmHA Alarm 4 800 rpmHW Alarm 4 450 rpmLW Alarm 2 000 rpmLA Alarm 1 200 rpm

# 0001

EUCA

400210

400209Reference Data400209400210400211400212400213400214400215400216400217400218

STATUSINPUTSPVMAX_SPEEDMIN_SPEEDDead_BandHIGH_ALARMHIGH_WARNLOW_ALARMLOW_WARN

10000000000000003960 DEC4835 DEC5000 DEC

0 DEC100 DEC

4000 DEC4450 DEC2000 DEC1200 DEC

The N.O. contact is used to suppress alarm checks when the drive system is shutdown,or during initial start up allowing the system to get above the Low alarm RPM level.

Example

EUCA

20168

5000 rpm4950490048504800475047004650460045504500445044004350430042504200

0

*

*

*

*

*

**

**

**

*

**

*

*

*

High Warning 400209 = 4000 hex

High Absolute400209 = 8000 hex

Warning – DB400209 = 4000 hex

Return to normal400209 = 0000 hex

*

Varying the binary value in register 400210 would cause the bits in nibble 1 of register400209 to correspond with the changes illustrated above. The DB becomes effectivewhen the alarm or warning has been set—then the signal falls into the DB zone.

The alarm is maintained, thus taking what would be a switch chatter condition out of amarginal signal level. This point is exemplified in the chart above, where after setting theHA alarm and returning to the warning level at 4700 the signal crosses in and out of DBat the warning level (4450) but the warning bit in 400209 stays ON.

The same action would be seen if the signal were generated through the low settings.

EUCA Example 3

You can chain up to four EUCA conversions together to make one alarm status register.Each conversion writes to the nibble defined in the block bottom node. In the programexample below, each EUCA block writes it‘s status (based on the table values for thatblock) into a four bit (nibble) of the status register 400209.

Example

EUCA

169


20

# 0001

EUCA

400210

400209

Reference Data400209 STATUS 0000001001001000

000023

# 0002

EUCA

400220

400209

# 0003

EUCA

400230

400209

# 0004

EUCA

400240

400209

000002

000003

000023 000004

# 1

BLKM

000033

400209

The status register can then be transferred using a BLKM instruction to a group ofdiscretes wired to illuminate lamps in an alarm enunciator panel.

As you observe the status content of register 400209 you see; no alarm in block 1, anLW alarm in block 2, an HW alarm in Block 3, and an HA alarm in block 4.

The alarm conditions for the four blocks can be represented with the following tablesettings:

Conversion 1 Conversion 2 Conversion 3 Conversion 4

Input 400210 = 2048 400220 = 1220 400230 = 3022 400240 = 3920

Scaled # 400211 = 2501 400221 = 1124 400231 = 7379 400241 = 0770

HEU 400212 = 5000 400222 = 3300 400232 = 9999 400242 = 0800

LEU 400213 = 0000 400223 = 0200 400233 = 0000 400243 = 0100

DB 400214 = 0015 400224 = 0022 400234 = 0100 400244 = 0006

Hi Alarm 400215 = 40000 400225 = 2900 400235 = 8090 400245 = 0768

Hi Warn 400216 = 3500 400226 = 2300 400236 = 7100 400246 = 0680

Lo Warn 400217 = 2000 400227 = 1200 400237 = 3200 400247 = 0280

Lo Alarm 400218 = 1200 400228 = 0430 400238 = 0992 400248 = 0230

FIN

20170

FINFirst In

1 Brief Description

The FIN instruction is used to produce a first-in queue. An FOUT instruction needs to beused to clear the register at the bottom of the queue. An FIN instruction has one controlinput and can produce three possible outputs.

2 Representation

2.1 Symbol

source

FIN

queue

queue

data

pointer

length



Data Type Meaning

top input 0x, 1x None ON = copies source bit pattern into queue

source data(top node)

0x, 1x, 3x, 4x ANY_BIT Source data, will be copied to the top of thedestination queue in the current logic scan

queue pointer(middle node)

4x WORD First of a queue of 4x registers, containsqueue pointer; the next contiguous register isthe first register in the queue

queue length(bottom node)

INT, UINT Number of 4x registers in the destinationqueue. Range: 1 ... 100

Top output 0x None Echoes state of the top inputMiddle output 0x None ON = queue full, no more source data can be

copied to the queueBottom output 0x None ON = queue empty (value in queue pointer re-

gister = 0)

FIN

171


20


3.1 Mode of FunctioningThe FIN instruction is used to produce a first-in queue. It copies the source data from thetop node to the first register in a queue of holding registers. The source data is alwayscopied to the register at the top of the queue. When a queue has been filled, no furthersource data can be copied to it.

1111 2222 3333

1111 2222

1111

FIN FIN FIN

Source Source Source

Queue Queue Queue

1111 2222 3333

NoteAn FOUT instruction needs to be used to clear the register at the bottom of the queue.

3.2 Parameter DescriptionSource Data (Top Node)When using register types 0x or 1x:

� First 0x reference in a string of 16 contiguous coils or discrete outputs� First 1x reference in a string of 16 discrete inputs

Queue Pointer (Middle Node)The 4x register entered in the middle node is a queue pointer. The first register in thequeue is the next contiguous 4x register following the pointer. For example, if the middlenode displays a a pointer reference of 400100, then the first register in the queue is400101.

The value posted in the queue pointer equals the number of registers in the queue thatare currently filled with source data. The value of the pointer cannot exceed the integermaximum queue length value specified in the bottom node.

If the value in the queue pointer equals the integer specified in the bottom node, themiddle output passes power and no further source data can be written to the queue untilan FOUT instruction clears the register at the bottom of the queue.

FOUT

20172

FOUTFirst Out

1 Brief Description

WarningFOUT will override any disabled coils within a destination register withoutenabling them. This can cause injury if a coil has been disabled for repair ormaintenance because the coil’s state can change as a result of the FOUToperation.

The FOUT instruction works together with the FIN instruction to produce a first in-first out(FIFO) queue. It moves the bit pattern of the holding register at the bottom of a full queueto a destination register or to word that stores 16 discrete outputs.

An FOUT instruction has one control input and can produce three possible outputs.

2 Representation

2.1 Symbol

source

FOUT

queue

destination

pointer

register

length

STOP

FOUT

173


20



Data Type Meaning

Top input 0x, 1x None ON = clears source bit pattern from thequeue

source poin-ter(top node)

4x WORD First of a queue of 4x registers, containssource pointer; the next contiguous regi-ster is the first register in the queue

destinationregister(middle node)

0x, 4x ANY_BIT Destination register

queue length(bottom node)

INT, UINT Number of 4x registers in the queue.Range: 1 ... 100

Top output 0x None Echoes state of ithe top inputMiddle output 0x None ON = queue full, no more source data

can be copied to the queueBottom output 0x None ON = queue empty (value in queue

pointer register = 0)


3.1 Mode of FunctioningThe FOUT instruction works together with the FIN instruction to produce a first in-first out(FIFO) queue. It moves the bit pattern of the holding register at the bottom of a full queueto a destination register or to word that stores 16 discrete outputs.

4444 444433332222

22221111

Queue

FIN

Source

Queue

3333FIN

1111

33332222 FOUT

Queue Destination

3333

1111Source

TipThe FOUT instruction should be placed before the FIN instruction in the ladder logicFIFO to ensure removal of the oldest data from a full queue before the newest data isentered. If the FIN block were to appear first, any attempts to enter the new data into afull queue would be ignored.

FOUT

20174

3.2 Parameter DescriptionSource Data (Top Node)In the FOUT instruction, the source data comes from the 4x register at the bottom of afull queue. The next contiguous 4x register following the source pointer register in the topnode is the first register in the queue. For example, if the top node displays pointerregister 400100, then the first register in the queue is 400101.

The value posted in the source pointer equals the number of registers in the queue thatare currently filled. The value of the pointer cannot exceed the integer maximum queuelength value specified in the bottom node. If the value in the source pointer equals theinteger specified in the bottom node, teh middle output passes power and no further FINdata can be written to the queue until the FOUT instruction clears the register at thebottom of the queue to the destination register.

Destination Register (Middle Node)The destination specified in the middle node can be a 0x reference or 4x register. Whenthe queue has data and the top input to the FOUT passes power, the source data iscleared from the bottom register in the queue and is written to the destination register.

FTOI

175


20

FTOIFloating Point to Integer

1 Brief Description

The FTOI instruction performs the conversion of a floating value to a signed or unsignedinteger (stored in two contiguous registers in the top node), then stores the convertedinteger value in a 4x register in the middle node.

2 Representation

2.1 Symbol

FP

FTOI

1

convertedinteger



Data Type Meaning

Top input 0x, 1x None ON = enables conversion


FP (top node) 4x REAL First of two contiguous holding registers wherethe floating point value is stored

converted in-teger(middle node)

4x INT, UINT Converted integer value is posted here

1(bottom node)

INT, UINT A constant value of 1 (can not be changed)

Top output 0x None ON = integer conversion completed success-fully

Bottom output 0x None ON = converted integer value is out of range:unsigned integer > 65 535–32 768 > signed integer > 32 767

HLTH

20176

HLTHHistory and Status Matrices


1 Brief Description

The HLTH instruction creates history and status matrices from internal memory registersthat may be used in ladder logic to detect changes in PLC status and communicationcapabilities with the I/O. It can also be used to alert the user to changes in a PLCSystem. HLTH has two modes of operation, learn and monitor.

2 Representation

2.1 Symbol

history

HLTH

length

status

HLTH

177


20



Data Type Meaning

Top input 0x, 1x None ON initiates the designated operation

Middle input 0x, 1x None Learn / monitor modeBottom input 0x, 1x None Learn / monitor modehistory(top node)

4x INT, UINT,WORD

History matrix (first in a block of contiguousregisters, range: 6 ... 135)

status(middle node)

4x INT, UINT,WORD

Status matrix (first in a block of contiguous re-gisters, range: 3 ... 132)

length(bottom node)

INT, UINT Number of I/O drops to manage

Top output 0x None Echoes state of the top inputMIddle output 0x None Echoes state of the middle inputBottom output 0x None ON = Error


3.1 Mode of FunctioningLearn ModeHLTH can be initialized to learn the configuration in which it is implemented and save theinformation as a point-in-time reference called history matrix. This matrix contains:

� A user-designated drop number for communications status monitoring� User logic checksum� Disabled I/O indicator� S911 Health� Choice of single or dual cable system� I/O Map display

Monitor ModeMonitor mode enables an operation that checks PLC system conditions. Detectedchanges are recorded in a status matrix. The status matrix monitors the most recentsystem conditions and sets bit patterns to indicate detected changes. The status matrixcontains:

� Communication status of the drop designated in the history matrix� A flag to indicate when there is any disabled I/O� Flags to indicate the ”on/off” status of constant sweep and the Memory protect key

switch� Flags to indicate a battery-low condition and if Hot Standby is functional� Failed module position data� Changed user logic checksum flag� RIO lost-communication flag

HLTH

20178

3.2 Parameter DescriptionLearn / Monitor Mode (MIddle and Bottom Input)The HLTH instruction block has three control inputs and can produce three possibleoutputs. The combined states of the middle and bottom inputs control the operatingmode:

MIddle Input Bottom Input OperationON OFF Learn Mode as Dual Cable SystemON ON Learn Mode as Single Cable SystemOFF ON Monitor ModeOFF OFF Monitor Mode Update Logic Checksum

History Matrix (Top Node)The 4x register entered in the top node is the first in a block of contiguous registers thatcomprise the history matrix. The data for the history matrix is gathered by the instructionduring a learn mode operation and is set in the matrix when the mode changes tomonitor.

The history matrix can range from 6 ... 135 registers in length. Below is a description ofthe words in the history matrix. The information from word 1 is contained in the displayedregister in the top node and the information from words 2 ... 135 is stored in the impliedregisters.

� Word 1: Enter drop number (range 0 ... 32) to be monitored for retries� Word 2: High word of learned checksum� Word 3: Low word of learned checksum� Word 4: The status and a counter for multiplexing the inputs. HLTH processes 16

words of input (256 inputs) per scan. This word holds the last word location of thelast scan. The register is overwritten on every scan. The value in the counterportion of the word increases to the maximum number of inputs, then restarts at 0:

1 2 3 54 6 7 8 9 10 11 1312 14 1615

1 = at least one disabled input has been found

Count of the number of words checked for disabled inputsprior to this scan

HLTH

179


20

� Word 5: Status and a counter for multiplexing outputs to detect if one is disabled.HLTH looks at 16 words (256 outputs) per scan to find one that is disabled. It holdsthe last word location of the last scan. The block is overwritten on every scan. Thevalue in the counter portion increases to maximum outputs then restarts at 0:

1 2 3 54 6 7 8 9 10 11 1312 14 1615

1 = at least one disabled output has been found

Count of the number of words checked for disabled outputsprior to this scan

� Word 6: Hot Standby cable learned data� Words 7 ... 10: Four words that define the learned condition of drop 1� Words 11 ... 14: Four words that define the learned condition of drop 2

1 2 3 54 6 7 8 9 10 11 1312 14 1615

1 = at least one disabled output has been found

ON = cable A monitored

ON = cable B monitored

HLTH

20180

� Words 132 ... 135: Four words that define the learned condition of drop 32

The structure of the four words allocated to each drop are as follows:

Rack 1, slot 3, module found

Drop delay bit 1 (see the note below)

1 2 3 54 6 7 8 9 10 11 1312 14 1615

Drop delay bit 2Drop delay bit 3

Drop delay bit 4Drop delay bit 5



Rack 1, slot 4, module foundRack 1, slot 5, module found




Rack 1, slot 11, module foundFirst Word

NoteDrop delay bits are used by the software to delay the monitoring of the drop for fourscans after reestablishing communications with a drop. The delay value is for internaluse only and needs no user intervention.

HLTH

181


20

1 2 3 54 6 7 8 9 10 11 1312 14 1615













Second Word

1 2 3 54 6 7 8 9 10 11 1312 14 1615














Third Word

HLTH

20182

1 2 3 54 6 7 8 9 10 11 1312 14 1615











Rack 5, slot 11, module foundFourth Word

Status Matrix (Middle Node)The 4x register entered in the middle node is the first in a block of contiguous holdingregisters that will comprise the status matrix. The status matrix is updated by the HLTHinstruction during monitor mode (top input is ON and middle input is OFF).

The status matrix can range from 3 ... 132 registers in length. Below is a description ofthe words in the status matrix. The information from word 1 is contained in the displayedregister in the middle node and the information from words 2 ... 132 is stored in theimplied registers.

� Word 1 is a counter for lost-communications at the drop being monitored:

1 2 3 54 6 7 8 9 10 11 1312 14 1615

Indicates number of the drop being monitored (0 ... 32)Count of the lost communication incidents (0 ... 15)

HLTH

183


20

� Word 2 is the cumulative retry counter for the drop being monitored (the dropnumber is indicated in the high byte of word 1):

1 2 3 54 6 7 8 9 10 11 1312 14 1615

Cumulative retry count (0 ... 255)

� Word 3 updates PLC status (including Hot Standby health) on every scan:

1 2 3 54 6 7 8 9 10 11 1312 14 1615

ON = Memory protect is OFF

ON = battery bad

ON = An S911 is badON = Hot Standby not active

ON = All drops are not communicating

ON = logic checksum has changed since last learn

ON = At least one disabled 1x input detected

ON = Constant sweep enabled

ON = At least one disabled 0x output detected

� Words 4 ... 7 indicate drop 1 status; words 8 ... 11 indicate drop 2 status; etc.,through words 129 ... 132, which indicate drop 32 status.

HLTH

20184

The structure of the four words allocated to each drop is as follows:

1 2 3 54 6 7 8 9 10 11 1312 14 1615

Rack 1, slot 1, module fault






Rack 1, slot 7, module faultRack 1, slot 8, module fault






Rack 2, slot 4, module faultDrop communication fault detected

First Word

1 2 3 54 6 7 8 9 10 11 1312 14 1615









Rack 3, slot 8, module faultRack 3, slot 9, module faultSecond Word

HLTH

185


20

1 2 3 54 6 7 8 9 10 11 1312 14 1615









Rack 4, slot 11,module fault



Third Word


1 2 3 54 6 7 8 9 10 11 1312 14 1615





Cable A faultCable B fault

Fourth Word

HLTH

20186

Length (Bottom Node)The decimal value entered in the bottom node is a function of how many I/O drops youwant to monitor. Each drop requires four registers/matrix. The length value is calculatedusing the following formula:

length = (# of I/O drops x 4) + 3

This value gives you the number of registers in the status matrix. You only need to enterthis one value as the length because the length of the history matrix is automaticallyincreased by 3 registers—i.e., the size of the history matrix is length + 3.

HSBY

187


20

HSBYHot Stand By Control System


1 Brief Description

The HSBY loadable instruction manages a 984 Hot Standby control system. Thisinstruction must be placed in network 1 of segment 1 in the application logic for both theprimary and standby controllers. It allows you to program a nontransfer area in systemstate RAM: an area that protects a serial group of registers in the standby controller frombeing modified by the primary controller.

Through the HSBY instruction you can access two registers, a command register and astatus register, that allow you to monitor and control Hot Standby operations. The statusregister is the third register in the nontransfer area you specify.

2 Representation

2.1 Symbol

command

HSBY

length

nontransfer

register

area

HSBY

20188



Data Type Meaning

Top input 0x, 1x None Execute HSBY (unconditionally)

Middle input 0x, 1x None Enable command registe

Bottom input 0x, 1x None Enable nontransfer area

command re-gister(top node)

4x INT, UINT,WORD

HSBY command register

nontransferarea(middle node)

4x INT, UINT,WORD

First register reserved for the nontransfer areain state RAM

length(bottom node)

INT, UINT Number of registers of the HSBY nontransferarea in state RAM, range: 4 ... 8000

Top output 0x None Hot Standby system ACTIVEMiddle output 0x None PLC cannot communicate with its HSBY mo-

dule


3.1 Parameter DescriptionCommand Register (Top Node)The 4x register entered in the top node is the HSBY command register; eight bits in thisregister may be configured and controlled via your panel software:

1 2 3 4 5 6 7 8 12 13 14 15 16



9 10 11


Disable keyswitch override = 0Enable keyswitch override = 1

Controller A in OFFLINE mode = 0Controller A in RUN mode = 1

Controller B in OFFLINE mode = 0Controller B in RUN mode = 1

Force standby offline if there is a logic mismatch = 0Do not force standby offline if there is a logic mismatch = 1

Allow exec upgrade only after application stops = 0Allow exec upgrade without stopping application = 1

HSBY

189


20

Nontransfer Area (Middle Node)The 4x register entered in the middle node is the first register reserved for thenontransfer area in state RAM. The first three registers in the nontransfer area arespecial registers:

Register ContentDisplayed and first implied Reverse transfer registers for passing information from the

standby to the primary PLCSecond implied HSBY status register, see Figure 1

The content of the remaining registers is application-specific; the length is defined in theparameter ”length” (bottom node).

Figure 1 Status Register

1 2 3 4 5 6 7 8 12 13 14 15 169 10 11

This controller in OFFLINE mode =This controller running in primary mode =This controller running in standby mode =

0 101

1 1

0 101

1 1

The other controller in OFFLINE mode =The other controller running in primary mode =The other controller running in standby mode =

10Controllers have matching logic =

Controllers do not have matching logic =

1This controller’s toggle switch set to B =0This controller’s toggle switch set to A =

HSBY

20190

An HSBY Reverse Transfer Example

The two networks below are for a primary controller that monitors two fault lamps and areverse transfer that sends status data from the standby controller to the primarycontroller. The first network must be network 2 of segment 1; the second network mustnot be in segment 1.

Network 2, Must be segment 1

Network must not be in Segment 1

# 1

BLKM

000801

400102

000815STAT

000001

400100

000816

000813 000814

# 1

BLKM

000705

400100

000715 000813 000208

000716 000813 000209

The first BLKM function transfers the HSBY status register (400102) to internal coils(000801). The STAT instruction, which is enabled if the other controller is in standbymode, sends one status register word from the standby controller to a reverse transferregister (400100) in the primary controller.

Example

IBKR

191


20

IBKRIndirect Block Read

1 Brief Description

The IBKR (indirect block read) instruction lets you access non-contiguous registersdispersed throughout your application and copy the contents into a destination block ofcontiguous registers. This instruction can be used with subroutines or for streamliningdata access by host computers or other PLCs.

2 Representation

2.1 Symbol

source

IBKR

length

destination

table

block

(1 ... 255)



Data Type Meaning

Top input 0x, 1x None ON = initiates indirect read operation


4x INT, UINT First holding register in a source table: containvalues that are pointers to the non-contiguousregisters you want to collect in the operation.

destinationblock(middle node)

4x INT, UINT First in a block of contiguous destination regi-sters, i.e. the block to which the source datawill be copied.

length(1 ... 255)(bottom node)

INT, UINT number of registers in the source table and thedestination block, range: 1 ... 255

Top output 0x None Echoes the state of the top inputBottom output 0x None ON = error in source table

IBKW

20192

IBKWIndirect Block Write

1 Brief Description

The IBKW (indirect block write) instruction lets you copy the data from a table ofcontiguous registers into several non-contiguous registers dispersed throughout yourapplication.

2 Representation

2.1 Symbol

source

IBKW

length

destination

block

pointers

(1 ... 255)



Data Type Meaning

Top input 0x, 1x None ON = initiates indirect write operation

source block(top node)

4x INT, UINT First in a block of source registers: contain va-lues that will be copied to non-contiguous regi-sters dispersed throughout the logic program

destiantionpointers(middle node)

4x INT, UINT First in a block of contiguous destination poin-ter registers. Each of these registers containsa value that points to the address of a registerwhere the source data will be copied.

length(1 ... 255)(bottom node)

INT, UINT Number of registers in the source block andthe destination pointer block, range: 1 ... 255

Top output 0x None Echoes the state of the top inputBottom output 0x None ON = error in destination table

ICMP

193


20

ICMPInput Compare


1 Brief Description

The ICMP (input compare) instruction provides logic for verifying the correct operation ofeach step processed by a DRUM instruction. Errors detected by ICMP may be used totrigger additional error–correction logic or to shut down the system

ICMP and DRUM are synchronized through the use of a common step pointer register.As the pointer increments, ICMP moves through its data table in lock step with DRUM.As ICMP moves through each new step, it compares–bit for bit–the live input data to theexpected status of each point in its data table.

2 Representation

2.1 Symbol

step

ICMP

length

step data

pointer

table

ICMP

20194



Data Type Meaning

Top input 0x, 1x None ON = initiates the input comparison

Middle input 0x, 1x None A cascading input, telling the block that pre-vious ICMP comparison were all good,ON = compare status is passing to the middleoutput

step pointer(top node)

4x INT, UINT Current step number

step data ta-ble(middle node)

4x INT, UINT First register in a table of step data information

length(bottom node)

INT, UINT Number of application–specific registers–usedin the step data table, range: 1 .. 999

Top output 0x None Echoes state of the top inputMiddle output 0x None ON =this comparison and all previous casca-

ded ICMPs are goodBottom output 0x None ON = Error


3.1 Parameter DescriptionStep Pointer (Top Node)The 4x register entered in the top node stores the step pointer–i.e., the number of thecurrent step in the step data table. This value is referenced by ICMP each time theinstruction is solved. The value must be controlled externally by a DRUM instruction orby other user logic. The same register must be used in the top node of all ICMP andDRUM instructions that are solved as a single sequencer.

ICMP

195


20

Step Data Table (Middle Node)The 4x register entered in the middle node is the first register in a table of step datainformation. The first eight registers in the table hold constant and variable data requiredto solve the instruction:

Register Name ContentDisplayed raw input data Loaded by user from a group of sequential inputs to

be used by ICMP for current stepFirst implied current step data Loaded by ICMP each time the block is solved; con-

tains a copy of data in the step pointer; causes theblock logic to automatically calculate register offsetswhen accessing step data in the step data table

Second implied input mask Loaded by user before using the block; contains amask to be ANDed with raw input data for each step–masked bits will not be compared; masked data areput in the masked input data register

Third implied masked input data Loaded by ICMP each time the block is solved; con-tains the result of the ANDed input mask and raw in-put data

Fourth implied compare status Loaded by ICMP each time the block is solved; con-tains the result of an XOR of the masked input dataand the current step data; unmasked inputs that arenot in the correct logical state cause the associatedregister bit to go to 1–non–zero bits cause a miscom-pare, and middle output will not go ON

Fifth implied machine ID number Identifies DRUM/ICMP blocks belonging to a specificmachine configuration; value range: 0 ... 9999 (0 =block not configured); all blocks belonging to samemachine configuration have the same machine ID

Sixth implied Profie ID Number Identifies profile data currently loaded to the sequenc-er; value range: O... 9999 (0 = block not configured);all blocks with the same machine ID number musthave the same profile ID number

Seventh implied Steps used Loaded by user before using the block, DRUM will notalter steps used contents during logic solve: containsbetween 1 ... 999 for 24 bit CPUs, specifying the actu-al number of steps to be solved; the number must be≤ the table length in the bottom node of the ICMPblock

The remaining registers contain data for each step in the sequence.

Length (Bottom Node)The integer value entered in the bottom node is the length–i.e., the number ofapplication–specific registers–used in the step data table. The length can range from 1 ..999 in a 24–bit CPU.

The total number of registers required in the step data table is the length + 8. The lengthmust be > the value placed in the steps used register in the middle node.

ICMP

20196

4 Cascaded DRUM/ICMP Blocks

A series of DRUM and/or ICMP blocks may be cascaded to simulate a mechanical drumup to 512 bits wide. Programming the same 4x register reference into the top node ofeach related block causes them to cascade and step as a grouped unit without the needof any additional application logic. All DRUM/ICMP blocks with the same registerreference in the top node are automatically synchronized. The must also have the sameconstant value in the bottom node, and must be set to use the same value in the stepsused register in the middle node.

ID

197


20

IDInterrupt Disable


1 Brief Description


The ID instruction masks timer-generated and/or local I/O-generated interrupts.



2 Representation

2.1 Symbol

ID

Type

ID

20198



Data Type Meaning

Top input 0x, 1x None ON = Instruction masks timer–generated and/or local I/O generated interrupts

Type(bottom node)

INT, UINT Type of interrupt to be masked (Constant inte-ger)

Top output 0x None Echoes state of ihe top input


3.1 Parameter DescriptionType (Bottom Node)Enter a constant integer in the range 1 ... 3 in the node. The value represents the type ofinterrupt to be masked by the ID instruction, where:

Integer Value Interrupt Type3 Timer interrupt masked2 Local I/O module interrupt masked1 Both interrupt types masked

IE

199


20

IEInterrupt Enable


1 Brief Description


The IE instruction unmasks interrupts from the timer or local I/O module and responds tothe pending interrupts by executing the designated subroutines.



2 Representation

2.1 Symbol

IE

Type

IE

20200



Data Type Meaning

Top input 0x, 1x None ON = Instruction unmasks interrupts and re-sponds pending interrupts

Type(bottom node)

INT, UINT Type of interrupt to be unmasked (constantinteger)



3.1 Parameter DescriptionTop InputWhen the input is energized, the IE instruction unmasks interrupts from the timer or localI/O module and responds to the pending interrupts by executing the designatedsubroutines.

Type (Bottom Node)Enter a constant integer in the range 1 ... 3 in the node. The value represents the type ofinterrupt to be unmasked by the IE instruction, where:

Integer Value Interrupt Type3 Timer interrupt unmasked2 Local I/O module interrupt unmasked1 Both interrupt types unmasked

IMIO

201


20

IMIOImmediate I/O


1 Brief Description

The IMIO instruction permits access of specified I/O modules from within ladder logic.This differs from normal I/O processing, where inputs are accessed at the beginning ofthe logic solve for the segment in which they are used and outputs are updated at theend of the segment’s solution. The I/O modules being accessed must reside in the localbackplane with the Quantum PLC.

In order to use IMIO instructions, the local I/O modules to be accessed must bedesignated in the I/O Map in your panel software.


2 Representation

2.1 Symbol

control

IMIO

type

block

IMIO

20202



Data Type Meaning

Top input 0x, 1x None ON = enables the immediate I/O access

control block(top node)

4x INT, UINT,WORD

Control block (first of two contiguous registers)

type(bottom node)

INT, UINT Type of operation (constant integer in the ran-ge of 1 ... 3)

Top output 0x None Echoes state of the top inputBottom output 0x None Error (indicated by a code in the error status

register in the IMIO control block, see chap-ter 4 )

IMIO

203


20


3.1 Parameter DescriptionControl Block (Top Node)The 4x register in the top node is the first of two contiguous registers in the IMIO controlblock. The first (the displayed) register in the control block specifies the physical addressof the I/O module to be accessed. The second (the implied) register in the control blocklogs the error status, which is maintained by the instruction.

The high byte of the displayed register in the control block allows you to specify whichrack the I/O module to be accessed resides in, and the low byte allow you to specify slotnumber within the specified rack where the I/O module resides.

1 2 3 54 6 7 15 168 9 10 1211 13 14

Rack Number Slot Number

0 0 1 = rack 1 0 1 0 = rack 2* 0 1 1 = rack 3* 1 0 0 = rack 4** Only rack 1 is currently supported

0 0 0 0 1 = slot 10 0 0 1 0 = slot 20 0 0 1 1 = slot 30 0 1 0 0 = slot 40 0 1 0 1 = slot 50 0 1 1 0 = slot 60 0 1 1 1 = slot 70 1 0 0 0 = slot 80 1 0 0 1 = slot 90 1 0 1 0 = slot 100 1 0 1 1 = slot 110 1 1 0 0 = slot 120 1 1 0 1 = slot 130 1 1 1 0 = slot 140 1 1 1 1 = slot 151 0 0 0 0 = slot 16

The implied register in the control block will contain an error code when the instructiondetects an error (see chapter 4). This register is maintained by the IMIO instruction.

Type (Bottom Node)Enter a constant integer in the range 1 ... 3 in the bottom node. The value represents thetype of operation to be performed by the IMIO instruction, where:

Integer Value Type of Immediate Access1 Input operation: transfers data from the the specified module to state RAM2 Output operation: transfers data from state RAM to the specified module3 I/O operation: does both input and output if the specified module is bi-

directional

IMIO

20204

4 Runtime Error

The implied register in the control block will contain the following errror code when theinstruction detects an error:

Error Code Meaning2001 Invalid type specified in the bottom node2002 Problem with the specified I/O slot, either an invalid slot number entered in

the displayed register of the control block or the I/O Map does not containthe correct module definition for this slot

2003 A type 3 operation is specified in the bottom node, and the module is notbidirectional

F001 Specified I/O module is not healthy

IMOD

205


20

IMODInterrupt Module Instruction


1 Brief Description

The IMOD instruction initiates a ladder logic interrupt handler subroutine when theappropriate interrupt is generated by a local interrupt module and received by the PLC.Each IMOD instruction in an application is set up to correspond to a specific slot in thelocal backplane where the interrupt module resides. The IMOD instruction can designatethe same or a separate interrupt handler subroutine for each interrupt point on theassociated interrupt module.


2 Representation

2.1 Symbol

slot number

IMOD

number of

Controlblock

interrupts

IMOD

20206



Data Type Meaning

Top input 0x, 1x None ON = initiates an interrupt

Bottom input 0x, 1x None ON = clears a previously detected error

slot number(top node)

INT, UINT, Indicates the slot number where the local inter-rupt module resides (constant integer in therange of 1 ... 16)


4x INT, UINT,WORD

Control block (first of max. 19 contiguous regi-sters, depending on number of interrupts)

number ofinterrupts(bottom node)

INT, UINT Indicates the number of interrupts that can begenerated from the associated interrupt modu-le (constant integer in the range of 1 ... 16)

Top output 0x None Echoes state of the top inputBottom output 0x None ON = error is detected. The source of the error

can be from any one of the enabled interruptpoints on the interrupt module.


Up to 14 IMOD instructions can be programmed in a ladder logic application, one foreach possible option slot in a local backplane.

Each interrupting point on each interrupt module can initiate a different interrupt handlersubroutine.

A maximum of 64 interrupt points can be defined in a user logic application. It is notnecessary that all possible input points on a local interrupt module be defined in theIMOD instruction as interrupts.

3.1 Parameter DescriptionEnabling of the Instruction (Top Input)When the input to the top node is energized, the IMOD instruction is enabled. The PLCwill respond to interrupts generated by the local interrupt module in the designated slotnumber. When the top input is not energized, interrupts from the module in thedesignated slot are disabled and all previously detected errors are cleared including anypending masked interrupts.

Clear Error (Bottom Input)This input clears previous errors.

IMOD

207


20

Slot Number (Top Node)The top node contains a decimal in the range 1 ... 16, indicating the slot number wherethe local interrupt module resides. This number is used to index into an array of controlstructures used to implement the instruction.

NoteThe slot number in one IMOD instruction must be unique with respect to the slotnumbers used in all other IMOD instruction in an application. If not the next IMOD withthat particular slot number will have an error.

NoteThe slot numbers where the PLC and the power supply reside are illegal entries—i.e., amaximum of 14 of the 16 possible slot numbers can be used as interrupt module slots. Ifthe IMOD slot number is the same as the PLC, the IMOD will have an error.

Control Block (Middle Node)The middle node contains the first 4x register in the IMOD control block. The controlblock contains parameters required to program an IMOD instruction. The size (number ofregisters) of the control block will equal the total number of programmed interrupt points+ 3.

The first three registers in the control block contain status information, of the remainingregisters provide means for you to specify the label (LAB) number of the interrupt handlersubroutine (see chapter ”General”, page 31) that is in the last (unscheduled) segment ofthe ladder logic program.

Table 1 Control Block for IMOD

Register ContentDisplayd Function status bitsFirst implied State of inputs 1 ... 16 from the interrupt module at the time of the interruptSecond implied State of inputs 17 ... 32 from the interrupt module at the time of the inter-

rupt (invalid data for a 16-bit interrupt module)Third implied LAB number and status for the first interrupt programmed point on the

interrupt module... . . .Last implied LAB number and status for the last interrupt programmed point on the

interrupt module

IMOD

20208

Function Status Bits

Figure 1 Function Status Bits

1 2 3 54 6 7 15 168 9 10 1211 13 14

Error: Interrupt lost because of on–line editingError: Maximum number of interrupts exceeded

Error: Slot number used in previous network(see Caution 1)

0 = IMOD disabled 1 = IMOD enabled

Module not healthy or not in I/O map

Error: controller slot

Error: interrupt lost due to comm error in backplane

Caution1An error is indicated in bit 8 when two IMOD instructions are assigned the sameslot number. When this happens, it is possible to lose interrupts from the workingIMOD instruction without an indication if the number specified in the bottom nodeof the two instructions is different.

Status Bits and LAB Number for each Interrupt PointBits 1 ... 5 of the third implied through last implied registers are status bits for eachinterrupt point. Bits 7 ... 16 are used to specify the LAB number for the interrupt handlersubroutine. The LAB number is a decimal value in the range 1 ... 1023

Figure 2 Status Bits and LAB Number

1 2 3 54 6 7 15 168 9 10 1211 13 14

Execution delayed because of interrupt maskError: Invalid block in the interrupt handler subroutine

Error: Execution overrunError: Invalid LAB number

Interrupt Point Status LAB Number for the Associated Interrupt Handler

Value in the range 1 ... 1023

Error: Mask interrupt overrun

IMOD

209


20

Whenever the input to the bottom node of the IMOD instruction is enabled, the status bits(bits 1 ... 5) are cleared. If a LAB number is specified (in bits 7 ... 16) as 0 or an invalidnumber, any interrupts generated from that point are ignored by the PLC.

Number of Interrupts (Bottom Node)The bottom node contains an integer indicating the number of interrupts that can begenerated from the associated interrupt module. The size (number of registers) of thecontrol block is this number + 3.

The PLC is able to be configured for a maximum of 64 module interrupts (from all theinterrupt modules residing in the local backplane). If the number you enter in the bottomnode of an IMOD instruction causes the total number of module interrupts systemwide toexceed 64, an error is logged in bit 7 of the first register in the control block.

For example, if you use four interrupt modules in the local backplane and assign 16interrupts to each of these modules (by entering 16 in the bottom node of eachassociated IMOD instruction, the PLC will not be able to handle any more moduleinterrupts. If you attempt to create a fifth IMOD instruction, an error will be logged in thatIMOD’s control block when you specify a value in the bottom node.

ITMR

20210

ITMRInterrupt Timer


1 Brief Description

The ITRM instruction allows you to define an interval timer that generates interrupts intothe normal ladder logic scan and initiates the execution of an interrupt handlingsubroutine. The user-defined interrupt handler is a ladder logic subroutine created in thelast, unscheduled segment of ladder logic with its first network marked by a LABinstruction. Subroutine execution is asynchronous to the normal scan cycle

Up to 16 ITMR instructions can be programmed in an application. Each interval timer canbe programmed to initiate the same or different interrupt handler subroutines, controlledby the JSR/LAB method described in the chapter General on page NO TAG.

Each instance of the interval timer is delayed for a programmed interval while the PLC isrunning, then generates a processor interrupt when the interval has elapsed.

An interval timer can execute at any time during normal logic scan, including system I/Oupdating or other system housekeeping operations. The resolution of each interval timeris 1 ms. An interval can be programmed in units of 1 ms, 10 ms, 100 ms, or 1 s. Aninternal counter increments at the specified resolution.


2 Representation

2.1 Symbol

control

ITMR

timer

block

number

ITMR

211


20



Data Type Meaning

Top input 0x, 1x None ON = enables instruction


4x INT, UINT,WORD

Control block (first of three contiguous regi-sters)

timer number(bottom node)

INT, UINT Timer number assigned to this ITMR instruc-tion (must be unique with respect to all otherITMR instructions in the application); range:1 ... 16

Top output 0x None Echoes state of the top inputBottom output 0x None Error (source of the error may be in the pro-

grammed parameters or a runtime executionerror)


3.1 Parameter DescriptionTop InputWhen the top input is energized, the ITRM instruction is enabled. It begins counting theprogrammed time interval. When that interval has expired the counter is reset and thedesignated error handler logic executes.

When the top input is not energized, the following events occur:

� All indicated errors are cleared� The timer is stopped� The time count is either reset or held, depending on the state of bit 15 of the first

register in the control block (the displayed register in the top node)� Any pending masked interrupt is cleared for this timer

Control Block (Top Node)The top node contains the the first of three contiguous 4x registers in the ITMR controlblock. These registers are used to specify the parameters required to program eachITMR instruction.

ITMR

20212

The lower eight bits of the first (displayed) register in the control block allow you tospecify function control parameters, and the upper eight bits are used to display functionstatus:

1 2 3 54 6 7 15 168 9 10 1211 13 14

Execution delayed because of interrupt mask

Invalid block in the interrupt handler subroutine

Time = 0

Mask interrupt overrunExecution overrun

No LAB or invalid LABTimer number used in previous network

0 = instructiondisabled1 = instruction enabled

0 = Enable OFF resets counter1 = Enable OFF holds counter

0 = PLC stop resets counter1 = PLC stop holds counter

0 0 = 1 ms time base0 1 = 10 ms time base1 0 = 100 ms time base1 1 = 1 s time base

Function Status Function Control

In the second register of the control block, specify a value representing the interval atwhich the ITRM instruction will generate interrupts and initiate the execution of theinterrupt handler. The interval will be incremented in the units specified by bits 12 and 13of the first control block register, i.e. 1 ms, 10 ms, 100 ms, or 1 s units.

In the third register of the control block, specify a value indicating the label (LAB) numberthat will start the interrupt handler subroutine, The number must be in the range1 ... 1023.

NoteWe recommend that the size of the logic subroutine associated with the LAB beminimized so that the application does not become interrupt-driven

ITMR

213


20

Timer Number (Bottom Node)Up to 16 ITRM instructions can be programmed in an application. The interrupts aredistinguished from one another by a unique number between 1 ... 16, which you assignto each instruction in the bottom node. The lowest interrupt number has the highestexecution priority.

For example, if ITMR 4 and ITMR 5 occur at the same time, ITMR 4 is executed first.After ITMR 4 has finished, ITMR 5 generally will begin executing.

An execption would be when another ITMR interrupt with a higher priority occurs duringITMR 4’s execution. For example, suppose that ITMR 3 occurs while ITMR 5 is waitingfor ITMR 4 to finish executing. In this case, ITMR 3 begins executing when ITMR4finishes, and ITMR 5 continues to wait.

ITOF

20214

ITOFInteger to Floating Point

1 Brief Description

The ITOF instruction performs the conversion of a signed or unsigned integer value (itstop node) to a floating point (FP) value, and stores the FP value in two contiguous 4xregisters in the middle node.

2 Representation

2.1 Symbol

integer

ITOF

1

convertedFP



Data Type Meaning

Top input 0x, 1x None ON = enables conversion


integer(top node)

3x, 4x INT, UINT Integer value, can be displayed explicitly as aninteger (range 1 ... 65 535) or stored in a regi-ster

converted FP(middle node)

4x REAL Converted FP value (first of two contiguousholding registers)

1(bottom node)

INT, UINT Constant value of 1, can not be changed

Top output 0x None ON = FP conversion completed successfully

JSR

215


20

JSRJump to Subroutine

1 Brief Description

When the logic scan encounters an enabled JSR instruction, it stops the normal logicscan and jumps to the specified source subroutine in the last (unscheduled) segment ofladder logic.

You can use a JSR instruction anywhere in user logic, even within the subroutinesegment. The process of calling one subroutine from another subroutine is callednesting. The system allows you to nest up to 100 subroutines; however, we recommendthat you use no more than three nesting levels. You may also perform a recursive form ofnesting called looping, whereby a JSR call within the subroutine recalls the samesubroutine.

2 Representation

2.1 Symbol

source

JSR

#1

JSR

20216



Data Type Meaning

Top input 0x, 1x None Enables the source subroutine

source(top node)

4x INT, UINT Source pointer (indicator of the subroutine towhich the logic scan will jump), entered expli-citly as an integer or stored in a register; ran-ge: 1 ... 1 023

#1(bottom node)

INT, UINT Allways enter the constant value 1

Top output 0x None Echoes state of the top inputBottom output 0x None Error in subroutine jump

3 Example

Example to subroutine handling see chapter ”General” on page 31.

LAB

217


20

LABLabel for a Subroutine

1 Brief Description

The LAB instruction is used to label the starting point of a subroutine in the last(unscheduled) segment of user logic. This instruction must be programmed in row 1,column 1 of a network in the last (unscheduled) segment of user logic. LAB is aone-node function block

LAB also serves as a default return from the subroutine in the preceding networks. If youare executing a series of subroutine networks and you find a network that begins withLAB, the system knows that the previous subroutine is finished, and it returns the logicscan to the node immediately following the most recently executed JSR block.

2 Representation

2.1 Symbol

LAB

subroutine(1 ... 255)



Data Type Meaning

Top input 0x, 1x None Initiates the subroutine specified by the num-ber in the bottom node

subroutine(bottom node)

INT, UINT integer value, identifies the subroutine you areabout to execute, range: 1 ... 255

Top output 0x None ON = error in the specified subroutine’s initia-tion

LAB

20218


3.1 Parameter DescriptionSubroutine (Bottom Node)The integer value entered in the node identifies the subroutine you are about to execute.The value can range from 1 ... 255. If more than one subroutine network has the sameLAB value, the network with the lowest number is used as the starting point for thesubroutine.

4 Example

Example to subroutine handling see chapter ”General” on page 31.

LOAD

219


20

LOADLoad Flash

NoteThis instruction is only available with the PLC family TSX Compact.

1 Brief Description

The LOAD instruction loads a block of 4x registers (previously SAVEd) from state RAMwhere they are protected from unauthorized modification.

2 Representation

2.1 Symbol

register

LOAD

length

1, 2, 3, 4

LOAD

20220



Data Type Meaning

Top input 0x, 1x None Start LOAD operation: it should remain ONuntil the operation has completed successfullyor an error has occurred.

register(top node)

4x INT, UINT,WORD

First of max. 512 contiguous 4x registers to beloaded from state RAM

1, 2, 3, 4(middle node)

INT Integer value, which defines the specific bufferwhere the block of data is to be loaded

length(bottom node)

INT Number of words to be loaded, range: 1 ... 512

Top output 0x None ON = LOAD is activeMiddle output 0x None ON = a LOAD is requested from a buffer whe-

re no data has been SAVEd.Bottom output 0x None ON = Length not equal to SAVEd length


3.1 Parameter Description1, 2, 3, 4 (Middle Node)The middle node defines the specific buffer where the block of data is to be loaded. Four512 word buffers are allowed. Each buffer is defined by placing its corresponding valuein the middle node, that is, the value 1 respresents the first buffer, value 2 respresentsthe second buffer and so on. Tha legal values are 1, 2, 3, and 4. When the PLC isstarted all four buffers are zeroed. Therefore, you may not load data from the samebuffer without first saving it whith the instruction SAVE. When this is attempted the middleoutput goes ON. In other words, once a buffer is used, it may not be used again until thedata has been removed.

Bottom OutputThe output from the bottom node goes ON when a LOAD request is not equal to theregisters that were SAVEd. This kind of transaction is allowed, however, it is yourresponsibility to ensure this does not create a problem in your application.

MAP 3

221


20

MAP 3MAP Transaction


1 Brief Description

Ladder logic applications running in the controller initiate communication with MAPnetwork nodes through the MAP3 instruction.

2 Representation

2.1 Symbol

control

MAP3

length

block

datasource

MAP 3

20222



Data Type Meaning

Top input 0x, 1x None ON = initiates a transaction

Middle input 0x, 1x None ON = new transaction to be initiated in the sa-me scan


4x INT, UINT,WORD

Control Block (first register of a block)

data source(middle node)

4x INT, UINT,WORD

Data source (starting register)

length(bottom node)

INT, UINT Length of local data area, range: 1 ... 255)

Top output 0x None Transaction completes succesfullyMIddle output 0x None Transaction is in progressBottom output 0x None Error


3.1 Parameter DescriptionTop InputThis input initiates a transaction. To start a transaction the input must be held ON (HIGH)for at least one scan. If the S980 has resources to process the transaction, the middleoutput passes power. If resources are not available, no outputs pass power.

Once a transaction is started, it will run until a reply is received, a communications erroris detected, or a timeout occurs. The values in the Control Block, Data Source andLength must not be altered, or the transaction will not be completed and the bottomoutput will pass power. A second transaction cannot be started by the same block untilthe first one is complete.

Middle InputIf the top input is also HIGH, the middle input going ON allows a new transaction to beinitiated in the same scan, following the completion of a previous one. A new transactionbegins when the top output passes power from the first transaction.

Control Block (Top Node)The top node is the starting 4x register of a block of registers that control the block’soperation. The contents of each register is determined by the kind of operation to beperformed by the MAP3 block:

� Read or Write� Information Report� Unsolicited Status� Conclude� Abort

MAP 3

223


20

� Word 1: Destination Device Contains the destination device in bit position 9 through 16. The computer workswith this byte as the LSB and will accept a range of 1 to 255.

1 2 3 54 6 7 15 168 9 10 1211 13 14

Not Used Destination device

� Word 2: Qualifier / Function CodeContains two bytes of information The qualifier bits 1 to 8 and the Function Code inbits 9 to 16.

1 2 3 54 6 7 15 168 9 10 1211 13 14

Qualifier 0 = addressed >0 = named

Function Code 4 = Read 5 = Write

� Word 3: Network Mode / Network TypeContains two bites of information. The Mode is in bits 5 through 8 and the Type isin bits 9 through 16.

1 2 3 54 6 7 15 168 9 10 1211 13 14

Not Used 1 = Association Mode

Mode Type

7 = 7 layer MAP network

1 = Type 1 Service

MAP 3

20224

� Word 4: Function StatusWord 4 is the Function Status. An error code is returned if an error occurs in ablock initiated function. The decimal codes are:

Decimal Code Meaning1 Association request rejected4 Message timeout application response5 Invalid destination device6 Message Size Exceeded8 Invalid Function code17 Device not available19 Unsupported Network Type22 No Channel available23 MMS message not sent24 Controller control block changed25 Initiate failed26 System download in progress28 Channel not ready99 Undetermined error103 Access Denied105 Invalid Address110 Object nonexistent

� Word 5: Register A Reference TypeWord 5 is labled Register A* and contains the reference type for 4 types of Read(0x, 1x, 3x, and 4x registers) and 2 types of Write ( 0X or 4x).

� Word 6: Register B Reference NumberWord 6 is labled Register B* and contains the starting reference number in therange 1 to 99999.

� Word 7: Register C Reference LengthWord 7 is labled Register C* and contains the Quantity of references requested.

� Word 8: Register D Timeout Word 8 is labled Register D* and contains the Timeout parameter. This value setsthe manimum length of time used to complete a transaction, including retries.

Function summaryThe network controlling device may issue a function code that alters the control blockregister assignment as given above for Read/Write. Those differences for Information,Status, Conclude and Abort are identified in this summary on the bottom of your screen

Refer to Modicon S980 MAP 3.0 Network Interface User Guide that describes theregister contents for each operation.

Data Source (Middle Node)The middle node is the starting 4x register of the local data source (for a write request) orlocal data destination (for a read).

MAP 3

225


20

Length (Bottom Node)The bottom node defines the maximum size of the local data area (the quantity ofregisters) starting at 4x register of data source, in the range of 1 to 255 decimal. Thequantity of data to be actually transferred in the operation is determined by a ReferenceLength parameter in one of the control registers.

Top OutputThe top output passes power for one scan when a transaction completes successfully.

Middle OutputThe middle output passes power when a transaction is in progress. If the top input is ONand the middle input is OFF, then the middle output will go OFF on the same scan thatthe top output goes ON. If both top input and middle input are ON, then the middle outputwill remain ON.

Bottom OutputThe bottom output passes power for one scan when a transaction cannot be completed.An error code is returned to the Function Status Word (register 4x+3) in the function’scontrol block.

MBIT

20226

MBITModify Bit

1 Brief Description

The MBIT instruction modifies bit locations within a data matrix, i.e. it sets the bit(s) to 1or clears the bit(s) to 0. One bit location may be modified per scan.

WarningMBIT will override any disabled coils within a destination group without enablingthem. This can cause injury if a coil has been disabled for repair or maintenancebecause the coil’s state can change as a result of the MBIT instruction.

2 Representation

2.1 Symbol

bit

MBIT

length

data

location

matrix

STOP

MBIT

227


20



Data Type Meaning

Top input 0x, 1x None ON = implements bit modification

MIddle input 0x, 1x None OFF = clear bit locations to 0ON = set bit locations to 1

Bottom input 0x, 1x None Increment bit location by one after modificationbit location(top node)


Specific bit location to be set or clear in thedata matrix; entered explicitly as an integervalue or stored in a register (range 1 ... 9 600)

data matrix(middle node)


First word or register in the data matrix

length(bottom node)

INT, UINT Matrix length; range: 1 ... 600

Top output 0x None Echoes state of the top inputMiddle output 0x None Echoes state of the middle inputBottom output 0x None ON = error: bit location > matrix length


3.1 Parameter DescriptionBit Location (Top Node)

NoteIf the bit location is entered as an integer or in a 3x register, the instruction will ignore thestate of the bottom input.

Matrix Length (Bottom Node)The integer value entered in the bottom node specifies a matrix length, i.e, the number of16-bit words or registers in the data matrix. The length can range from 1 ... 600 in a24-bit CPU, e.g, a matrix length of 200 indicates 3200 bit locations.

MBUS

20228

MBUSMBUS Transaction


1 Brief Description

The S975 Modbus II Interface option modules use two loadable function blocks: MBUSand PEER (see Volume 2). MBUS is used to initiate a single transaction with anotherdevice on the Modbus II network. In an MBUS transaction, you are able to read or writediscrete or register data.

PLCs on a Modbus II network can handle up to 16 transactions simultaneously.Transactions include incoming (unsolicited) messages as well as outgoing messages.Thus, the number of message initiations a PLC can manage at any time is16 – # of incoming messages.

A transaction cannot be initiated unless the S975 has enough resources for the entiretransaction to be performed. Once a transaction has been initiated, it runs until a reply isreceived, an error is detected, or a timeout occurs. A second transaction cannot bestarted in the same scan that the previous transaction completes unless the middle inputis ON. A second transaction cannot be initiated by the same MBUS instruction until thefirst transaction has completed.

2 Representation

2.1 Symbol

control

MBUS

length

data

block

block

MBUS

229


20



Data Type Meaning

Top input 0x, 1x None Enable MBUS transaction

Middle input 0x, 1x None Repeat transaction in same scan

Bottom input 0x, 1x None Clears system statistics


4x INT, UINT,WORD

First of seven contiguous registers in theMBUS control block

data block(middle node)

4x INT, UINT,WORD

First 4x register in a data block to be transmit-ted or received in the MBUS transaction.

length(bottom node)

INT, UINT Number of words reserved for the data block isentered as a constant value

Top output 0x None Transaction completeMiddle output 0x None Transaction in progress or new transaction

startingBottom output 0x None Error detected in transaction

MBUS

20230


3.1 Parameter DescriptionControl Block (Top Node)The 4x register entered in the top node is the first of seven contiguous registers in theMBUS control block:

Register FunctionDisplayed Address of destination device (range: 0 ... 246)

4x + First implied

Second implied Function code for requested action: 01 Read discretes 02 Read registers 03 Write discrete outputs

04 Write register outputs255 Get system statistics

Third implied Discrete or register reference type: 0 Discrete output (0x) 1 Discrete input (1x) 3 Input register (3x)

4 Holding register (4x)

Fourth implied Reference number—e.g., if you placed a 4 in the third implied register andyou place a 23 in this register, the reference will be holding register 400023

Fifth implied Number of words of discrete or register references to be read or written; thelength limits are:Read register 251 registers

Write register 249 registersRead coils 7 848 discretesWrite coils 7 800 discretes

Sixth implied Time allowed for a transaction to be completed before an error is declared;expressed as a multiple of 10 ms—e.g., 100 indicates 1 000 ms; the defaulttimeout is 250 ms

MBUS

231


20

Length (Bottom Node)The number of words reserved for the data block is entered as a constant value in thebottom node. This number does not imply a data transaction length, but it can restrictthe maximum allowable number of register or discrete references to be read or written inthe transaction. The maximum number of words that may be used in the specifiedtransaction is:

� 251 for reading registers (one register/word)� 249 for writing registers (one register/word)� 490 for reading discretes using 24-bit CPUs (up to 16 discretes/word)� 487 for writing discretes using 24-bit CPUs (up to 16 discretes/word)

4 The MBUS Get Statistics Function

Issuing function code 255 in the second implied register of the MBUS control blockobtains a copy of the Modbus II local statistics—a series of 46 contiguous registerlocations where data describing error and system conditions is stored. To use MBUS fora get statistics operation, set the length in the bottom node to 46—a length < 46 returnsan error (the bottom output will go ON), and a length > 46 reserves extra registers thatcannot be used. For example:

400101Enable

Clear system

Complete

Error: length < 46MBUS

46

401000

statitics

Register 400101 is the first register in the MBUS control block, making register 400103the control register that defines the MBUS function code. By entering a value of 255 inregister 400103, you implement a get statistics function. Registers 401000 ... 401045are then filled with the following system statistics:

Statistic Register ContentToken bus controller (TBC) 401000 Number of tokens passed by this station

401001 Number of tokens sent by this station401002 Number of time the TBC has failed to pass

token and has not found a successor401003 Number of times the station has had to look

for a new successor

MBUS

20232

Statistic ContentRegisterSoftware-maintained 401004 TBC-detected error framesreceive statistics 401005 Invalid request with response frames

401006 Applications message too long401007 Media access control (MAC) address out of

range401008 Duplicate application frames401009 Unsupported logical link control (LLC) mes-

sage types401010 Unsupported LLC address

TBC-maintained 401011 Receive noise bursts (no start delimiter)error counters 401012 Frame check sequence errors

401013 E-bit error in end delimiter401014 Fragmented frames received (start delimiter

not followed by end delimiter)401015 Receive frames too long401016 Discarded frames because there is no re-

ceive buffer401017 Receive overruns401018 Token pass failures

Software-maintained 401019 Retries on request with response framestransmit errors 401020 All retries performed and no response re-

ceived from unit

Software-maintained 401021 Bad transmit requestreceive errors 401022 Negative transmit confirmation

User logic transaction errors 401023 Message sent but no application response401024 Invalid MBUS/PEER logic

Manufacturing message 401025 Command not executableformat standard 401026 Data not available

(MMFS) errors 401027 Device not available401028 Function not implemented401029 Request not recognized401030 Syntax error

401031 Unspecified error401032 Data request out of bounds401033 Request contains invalid controller address

401034 Request contains invalid data type401035 None of the above

Background statistics 401036 Invalid MBUS/PEER request401037 Number of unsupported MMFS message

types received

MBUS

233


20

Statistic ContentRegister401038 Unexpected response or response received

after timeout401039 Duplicate application responses received

401040 Response from unspecified device401041 Number of responses buffered to be pro-

cessed (in the least significant byte); num-ber of MBUS/PEER requests to be pro-cessed (in the most significant byte)

401042 Number of received requests to be pro-cessed (in the least significant byte); num-ber of transactions in process (in the mostsignificant byte)

401043 S975 scan time in 10 �s increments

Software revision 401044 Version level of fixed software (PROMs):major version number in most significantbyte; minor version number in least signifi-cant byte

401045 Version of loadable software(EEPROMs):major version number in most significantbyte; minor version number in least signifi-cant byte

MRTM

20234

MRTMMulti–Register Transfer Module


1 Brief Description

The MRTM instruction is used to transfer blocks of holding registers from the programtable to the command block, a group of output registers. To verify each block transfer, anecho of the data contained in the first holding register is returned to an input register. TheMRTM function block is shown in the following figure.

2 Representation

2.1 Symbol

program

MRTM

length

control

table

table

MRTM

235


20



Data Type Meaning

Top input 0x, 1x None ON = enables the operation

Middle input 0x, 1x None ON = one instruction block is transferred, tablepointer of control table is incremented by thevalue of ”length”

Bottom input 0x, 1x None ON =resetprogram table(top node)

0x, 1x, 3x, 4x INT, UINT,WORD

First register of the program table. The digit 4is assumed as the most significant digit

control table(middle node)


First register of the control table. The digit 4 isassumed as the most significant digit.

length(bottom node)

INT, UINT Number of registers moved from the programtable during each transfer, range: 1 to 127.

Top output 0x None Echoes state of the top inputMiddle output 0x None Instruction block is transferred to the command

block (stays on only for the remainder of thecurrent scan)

Bottom output 0x None ON = pointer value ≥ table end


3.1 Mode of FunctioningThe MRTM transfers contiguous blocks of up to 127 registers from a table of registerblocks to a block size holding register area. The MRTM function block controls theoperation of the module in the following manner:

� When power is applied to the top input, the function block is enabled for datatransfers.

NoteOn initial startup, power must be applied to the bottom input.

� When power is applied to the middle input, the function block attempts to transferone instruction block. Before a transfer can occur, the echo register is evaluated.The most significant bit (MSB) of the echo register is not evaluated just bits 0through 14. Echo mismatch is a condition that prohibits a transfer. If a transfer ispermitted, one instruction block is transferred form the table starting at the tablepointer.

� The table pointer in the control table is then advanced. If the pointer’s new value isequal to or greater than the table end, the bottom output is turned on. A tablepointer value less than the table end turns off the output.

� When power is applied to the bottom input, the function block resets. The tablepointer in the control table is reloaded with the start of commands value from theheader of the program table

MRTM

20236

3.2 Parameter DescriptionIncrement Step (MIddle Input)When power is applied, this input attempts to transfer one instruction block. Before atransfer can occur, the echo register is evaluated. The most significant bit (MSB) of theecho register is not evaluated, just bits 0 through 14. Echo mismatch is a condition thatprohibits a transfer. If a transfer is permitted, one instruction block is transferred from theprogram table starting at the table pointer. The table pointer in the control table is thenincremented by the value ”Length” (displayed in the Bottom node).

NoteThe MRTM function block is designed to accept fault indications from I/O modules, whichecho valid commands to the controller, but set a bit to indicate the occurrence of a fault.This method of fault indication is common for motion products and for most other I/Omodules. If using a module that reports a fault condition in any other way, especially ifthe echo involved is not an echo of a valid command, special care must be taken whenwriting the error handler for the ladder logic to ensure the fault is detected. Failure to doso may result in a lockup or some other undesirable performance of the MRTM.

Reset Pointer (Bottom Input)When power is applied to this input, the function block is reset. The table pointer in thecontrol table is reloaded with the start of commands value from the header of theprogram table.

MSTR

237


20

MSTRMaster

1 Brief Description

PLCs that support networking communications capabilities over Modbus Plus andEthernet have a special MSTR (master) instruction with which nodes on the network caninitiate message transactions.The MSTR instruction allows you to initiate one of 12possible network communications operations over the network.

� Read MSTR Operation� Write MSTR Operation� Get Local Statistics MSTR Operation� Clear Local Statistics MSTR Operation� Write Global Data MSTR Operation� Read Global Data MSTR Operation� Get Remote Statistics MSTR Operation� Clear Remote Statistics MSTR Operation� Peer Cop Health MSTR Operation� Reset Option Module MSTR Operation� Read CTE (Config Extension) MSTR Operation� Write CTE (Config Extension) MSTR Operation

2 Representation

2.1 Symbol

control

MSTR

length

data

block

area

MSTR

20238



Data Type Meaning

Top input 0x, 1x None ON = enables selected MSTR operation

Middle input 0x, 1x None ON = terminates active MSTR operationcontrol block(top node)

4x INT, UINT Control block (first of several (network–depen-dant) contiguous holding registers)

data area(middle node)

4x INT, UINT Data area (source or destination depending onselected operation)

length(bottom node)

INT Length of data area (maximum number of regi-sters), range: 1 ... 100

Top output 0x None ON while the instruction is active (echoes stateof the top input)

MIddle output 0x None ON if the MSTR operation is terminated priorto completion (echoes state of the middle in-put)

Bottom output 0x None ON = operation successful


3.1 Mode of FunctioningThe MSTR instruction allows you to initiate one of 12 possible network communicationsoperations over the network. Each operation is designated by a code. Certain MSTRoperations are supported on some networks and not on others:

MSTR Operation Code Modbus Plus TCP/IPEtherNet

SY/MAXEthernet

See Page

Write Data 1 x x x 248

Read Data 2 x x x 248

Get Local Statistics 3 x x not supported 250Clear Local Statistics 4 x x not supported 251Write Global Database 5 x not supported not supported 252Read Global Database 6 x not supported not supported 254Get Remote Statistics 7 x x not supported 255Clear Remote Statistics 8 x x not supported 256Peer Cop health 9 x not supported not supported 258Reset Option Module 10 not supported x x 258Read CTE (config extension) 11 not supported x x 258Write CTE (config extension) 12 not supported x x 258

Up to four MSTR instructions can be simultaneously active in a ladder logic program.More than four MSTRs may be programmed to be enabled by the logic flow; as oneactive MSTR block releases the resources it has been using and becomes deactivated,the next MSTR operation encountered in logic can be activated.

MSTR

239


20

3.2 Parameter DescriptionControl Block (Top Node)The 4x register entered in the top node is the first of several (network-dependant) holdingregisters that comprise the network control block. The control block structure differsaccording to the network in use:

� Modbus Plus (see Table 1)� TCP/IP EtherNet (see Table 2)� SY/MAX EtherNet (see Table 3)

Table 1 Control Block for Modbus Plus

Register ContentDisplayed Identifies one of the nine MSTR operations legal for Modbus

Plus (1 ... 9)First implied Displays error status (see chapter 4)Second implied Displays length (number of registers transferred)Third implied Displays MSTR operation-dependent informationFourth implied The Routing 1 register, used to designate the address of the

destination node for a network transaction. The register displayis implemented physically for the Quantum PLCs see Figure 1

Fifth implied The Routing 2 registerSixth implied The Routing 3 registerSeventh implied The Routing 4 registerEighth implied The Routing 5 registerNinth implied not applicableTenth implied not applicableEleventh implied not applicable

MSTR

20240

Routing 1 Register for Quantum Automation Series PLCs (Fourth Implied Register)To target a Modbus Plus Network Option module (NOM) in a Quantum PLC backplaneas the destination of an MSTR instruction, the value in the high byte represents thephysical slot location of the NOM, e.g. if the NOM resides in slot 7 in the backplane, thehigh byte of routing register 1 would look like this:

Figure 1 Control Block (Fourth Implied Register)

high byte

0 0 0 0 0 1 1 1

indicating physical location

destination address

0 x x x x x x x

binary value between 1 ... 64

ExpertIf you have created a logic program using an MSTR instruction for a 984 PLC and wantto port it to a Quantum Automation Series PLC without having to edit the routing 1register value, make sure that NOM #1 is installed in slot 1 of the Quantum backplane(and if a NOM #2 is used, that it is installed in slot 2 of the backplane). If you try to runthe ported application with the NOMs in other slots without modifying the register, anF001 status error will appear, indicating the wrong destination node.

Table 2 Control Block for TCP/IP EtherNet

Register ContentDisplayed Identifies one of the nine MSTR operations legal for TCP/IP

(1 ... 4, 7, 8, 10 ... 12)First implied Displays error status (see chapter 4)Second implied Displays length (number of registers transferred)Third implied Displays MSTR operation-dependent informationFourth implied Low byte: slot address of the NOE module

High byte: MBP-to-EtherNet Transporter (MET) Map indexFifth implied Byte 4 of the 32-bit destination IP AddressSixth implied Byte 3 of the 32-bit destination IP AddressSeventh implied Byte 2 of the 32-bit destination IP AddressEighth implied Byte 1 of the 32-bit destination IP Address

MSTR

241


20

Table 3 Control Block for SY/MAX EtherNet

Register ContentDisplayed Identifies one of the nine MSTR operations legal for SY/MAX

(1, 2, 10 ... 12)First implied Displays error status (see chapter 4)Second implied Displays Read/Write length (number of registers transferred)Third implied Displays Read/Write base addressFourth implied Low byte: slot address of the NOE module (e.g., slot 10 = 0A00,

slot 6 = 0600)High byte: MBP-to-EtherNet Transporter (MET) Map index

Fifth implied Destination drop number (or set to FF hex)Sixth implied Terminator (set to FF hex)

Data Area (Middle Node)The 4x register entered in the middle node is the first in a group of contiguous holdingregisters that comprise the data area. For operations that provide the communicationprocessor with data, such as a Write operation, the data area is the source of the data.For operations that acquire data from the communication processor ,such as a Readoperation, the data area is the destination for the data.

In the case of the EtherNet Read (see page 261) and Write (see page 262) CTEoperations, the middle node stores the contents of the EtherNet configuration extensiontable in a series of registers.

4 MSTR Function Error Codes

If an error occurs during a MSTR operation, a hexadecimal error code will be displayedin the first implied register in the control block (the top node). Function error codes arenetwork-specific:

� Modbus Plus and SY/MAX EtherNet Error Codes (see page 241)� SY/MAX–specific Error Codes (see page 243)� TCP/IP EtherNet Error Codes (see page 245)� CTE Error Codes for SY/MAX and TCP/IP EtherNet (see page 247)

4.1 Modbus Plus and SY/MAX EtherNet Error CodesThe form of the function error code for Modbus Plus and SY/MAX EtherNet transactionsis Mmss, where

� M represents the major code� m represents the minor code� ss represents a subcode

MSTR

20242

Table 4 HEX Error Code Modbus Plus and SY/MAX EtherNet

Hex Error Code Meaning1001 User has aborted the MSTR element2001 An unsupported operation type has been specified in the control block2002 One or more control block parameter has been changed while the MSTR

element is active (applies only to operations that take multiple scans tocomplete). Control block parameters may be changed only when theMSTR element is not active

2003 Invalid value in the length field of the control block2004 Invalid value in the offset field of the control block2005 Invalid values in the length and offset fields of the control block2006 Invalid slave device data area2007 Invalid slave device network area2008 Invalid slave device network routing2009 Route equal to your own address200A Attempting to obtain more global data words than available30ss Modbus slave exception response (see Table 5)4001 Inconsistent Modbus slave response5001 Inconsistent network response6mss Routing failure (see Table 6)

Note1The ss subfield in error code 30ss is:

Table 5 ss HEX Value in Error Code 30ss

ss Hex Value Meaning01 Slave device does not support the requested operation02 Nonexistent slave device registers requested03 Invalid data value requested04 Reserved05 Slave has accepted long-duration program command06 Function can’t be performed now: a long-duration command in effect07 Slave rejected long-duration program command08 ... 255 Reserved

MSTR

243


20

Note2The m subfield in error code 6mss is an index into the routing information indicatingwhere an error has been detected (a value of 0 indicates the local node, a 2 the seconddevice on the route, etc). The ss subfield in error code 6mss is:

Table 6 ss Hex Value in Error Code 6mss

ss Hex Value Meaning01 No response received02 Program access denied03 Node off-line and unable to communicate04 Exception response received05 Router node data paths busy06 Slave device down07 Bad destination address08 Invalid node type in routing path10 Slave has rejected the command20 Initiated transaction forgotten by slave device40 Unexpected master output path received80 Unexpected response receivedF001 Wrong destination node specified for the MSTR operation

4.2 SY/MAX–specific Error CodesThree additional types of errors may be reported in the MSTR instruction when SY/MAXEtherNet is being used. The error codes have the following designations:

� 71xx errors: Errors detected by the remote SY/MAX device� 72xx errors: Errors detected by the server� 73xx errors: Errors detected by the Quantum translator

Table 7 HEX Error Code SY/MAX–specific

Hex Error Code Meaning7101 Illegal opcode detected by the remote SY/MAX device7103 Illegal address detected by the remote SY/MAX device7109 Attempt to write a read–only register detected by the remote SY/MAX

device710F Receiver overflow detected by the remote SY/MAX device7110 Invalid length detected by the remote SY/MAX device7111 Remote device inactive, not communicating (occurs after retries and time–

out have been exhausted) detected by the remote SY/MAX device7113 Invalid parameter on a read operation detected by the remote SY/MAX

device711D Invalid route detected by the remote SY/MAX device7149 Invalid parameter on a write operation detected by the remote SY/MAX

device

MSTR

20244

Table 7 HEX Error Code SY/MAX–specific

Hex Error Code Meaning714B Illegal drop number detected by the remote SY/MAX device7201 Illegal opcode detected by the SY/MAX server7203 Illegal address detected by the SY/MAX server7209 Attempt to write to a read–only register detected by the SY/MAX server720F Receiver overflow detected by the SY/MAX server7210 Invalid length detected by the SY/MAX server7211 Remote device inactive, not communicating (occurs after retries and time–

out have been exhausted) detected by the SY/MAX server7213 Invalid parameter on a read operation detected by the SY/MAX server721D Invalid route detected by the SY/MAX server7249 Invalid parameter on a write operation detected by the SY/MAX server724B Illegal drop number detected by the SY/MAX server7301 Illegal opcode in an MSTR block request by the Quantum translator7303 Read/Write QSE module status (200 route address out of range)7309 Attempt to write to a read–only register when performing a status write

(200 route)731D Invalid rout detected by Quantum translator. Valid routes are:

– dest_drop, 0xFF– 200, dest_drop, 0xFF– 100+drop, dest_drop, 0xFFAll other routing values generate an error

734B One of the following errors has occurred:– No CTE (configuration extension) table was configured– No CTE table entry was created for the QSE Module slot number– No valid drop was specified– The QSE Module was not reset after the CTE was created (see note 3)– When using an MSTR instruction, no valid slot or drop was specified

Note3After writing and configuring the CTE and downloading it to the QSE Module, you mustreset the QSE Module to make the changes take effect.

MSTR

245


20

4.3 TCP/IP EtherNet Error CodesAn error in an MSTR routine over TCP/IP EtherNet may produce one of the followingerrors in the MSTR control block.

The form of the code is Mmss, where

� M represents the major code� m represents the minor code� ss represents a subcode

Table 8 HEX Error Code TCP/IP EtherNet

Hex Error Code Meaning1001 User has aborted the MSTR element2001 An unsupported operation type has been specified in the control block2002 One or more control block parameter has been changed while the MSTR

element is active (applies only to operations that take multiple scans tocomplete). Control block parameters may be changed only when theMSTR element is not active

2003 Invalid value in the length field of the control block2004 Invalid value in the offset field of the control block2005 Invalid values in the length and offset fields of the control block2006 Invalid slave device data area3000 Generic Modbus fail code30ss Modbus slave exception response (see Table 9)4001 Inconsistent Modbus slave response

Note4The ss subfield in error code 30ss is:

Table 9 ss HEX Value in Error Code 30ss

ss Hex Value Meaning01 Slave device does not support the requested operation02 Nonexistent slave device registers requested03 Invalid data value requested04 Reserved05 Slave has accepted long-duration program command06 Function can’t be performed now: a long-duration command in effect07 Slave rejected long-duration program command

MSTR

20246

An error on the TCP/IP EtherNet network itself may produce one of the following errors inthe MSTR control block:

Table 10 HEX Error Code TCP/IP EtherNet Network

Hex Error Code Meaning5004 Interrupted system call5005 I/O error5006 No such address5009 The socket descriptor is invalid500C Not enough memory500D Permission denied5011 Entry exists5016 An argument is invalid5017 An internal table has run out of space5020 The connection is broken5023 This operation would block and the socket is nonblocking5024 The socket is nonblocking and the connection cannot be completed5025 The socket is nonblocking and a previous connection attempt has not yet

completed5026 Socket operation on a nonsocket5027 The destination address is invalid5028 Message too long5029 Protocol wrong type for socket502A Protocol not available502B Protocol not supported502C Socket type not supported502D Operation not supported on socket502E Protocol family not supported502F Address family not supported5030 Address is already in use5031 Address not available5032 Network is down5033 Network is unreachable5034 Network dropped connection on reset5035 The connection has been aborted by the peer5036 The connection has been reset by the peer5037 An internal buffer is required, but cannot be allocated5038 The socket is already connected5039 The socket is not connected503A Can’t send after socket shutdown503B Too many references; can’t splice503C Connection timed out503D The attempt to connect was refused5040 Host is down5041 The destination host could not be reached from this node

MSTR

247


20

Table 10 HEX Error Code TCP/IP EtherNet Network

Hex Error Code Meaning5042 Directory not empty5046 NI_INIT returned –15047 The MTU is invalid5048 The hardware length is invalid5049 The route specified cannot be found504A Collision in select call; these conditions have already been selected by

another task504B The task id is invalidF001 In Reset mode

4.4 CTE Error Codes for SY/MAX and TCP/IP EtherNetThe following error codes are returned if there is a problem with the EtherNetconfiguration extension table (CTE) in your program configuration.

Table 11 CTE Error Codes for SY/MAX and TCP/IP EtherNet

Hex Error Code Meaning7001 The is no EtherNet configuration extension7002 The CTE is not available for access7003 The offset is invalid7004 The offset + length is invalid7005 Bad data field in the CTE

MSTR

20248

5 MSTR Operations

5.1 Read and Write MSTR OperationsBrief DescriptionAn MSTR Write operation transfers data from a master source device to a specifiedslave destination device on the network. An MSTR Read operation transfers data from aspecified slave source device to a master destination device on the network. Read andWrite use one data master transaction path and may be completed over multiple scans.

Network ImplementationThe MSTR Read and Write operations (type 2 or 1, respectively, in the displayed registerof the top node) can be implemented on the Modbus Plus, TCP/IP EtherNet, andSY/MAX EtherNet networks.

NoteYou need to understand the routing procedures used by the network you are using whenyou program an MSTR instruction. A full discussion of Modbus Plus routing pathstructures is given in Modbus Plus Network Planning and Installation Guide. IfTCP/IP or SY/MAX EtherNet routing is being implemented, it must be accomplished viastandard third-party Ethernet IP router products.

Control Block UtilizationIn a Read or Write operation, the registers in the MSTR control block (the top node)contain the information that differs depending on the type of network you are using:

� Modbus Plus (see Table 12)� TCP/IP EtherNet (see Table 13)� SY/MAX EtherNet (see Table 14)


Register Function ContentDisplayed Operation type 1 = Write; 2 = ReadFirst implied Error status Displays a hex value indicating an MSTR error,

when relevantSecond implied Length Write = number of registers to be sent to slave

Read = number of registers to be read from slaveThird implied Slave device data area Specifies starting 4x register in the slave to be

read from or written to (1 = 40001, 49 = 40049)Fourth ... Eighthimplied

Routing 1 ... 5 Designates the first ... fifth routing path address-es, respectively; the last nonzero byte in the rout-ing path is the destination device

MSTR

249


20

NoteIf you attempt to program the MSTR to Read or Write its own station address, an errorwill be generated in the first implied register of the MSTR control block. It is possible toattempt a Read/Write operation to a nonexistent register in the slave device. The slavewill detect this condition and report it, this may take several scans.


Register Function ContentDisplayed Operation type 1 = Write; 2 = ReadFirst implied Error status Displays a hex value indicating an MSTR error:

Exception code + 3000: Exception response,where response size is correct4001: Exception response, where response sizeis incorrect4001: Read/Write

Second implied Length Write = number of registers to be sent to slaveRead = number of registers to be read from slave

Third implied Slave device data area Specifies starting 4x register in the slave to beread from or written to (1 = 40001, 49 = 40049)

Fourth implied Low byte Slot address of the network adapter moduleFifth ... eighth im-plied

Destination Each register contains one byte of the 32-bit IPaddress


Register Function ContentDisplayed Operation type 1 = Write; 2 = ReadFirst implied Error status Displays a hex value indicating an MSTR error,

when relevantSecond implied Length Write = number of registers to be sent to slave

Read = number of registers to be read from slaveThird implied Slave device data area Specifies starting 4x register in the slave to be

read from or written to (1 = 40001, 49 = 40049)Fourth implied Slot ID Low byte: slot address of the network adapter

moduleHigh byte: Destination drop number

Fifth ... eighth im-plied

Terminator FF hex

MSTR

20250

5.2 Get Local Statistics MSTR OperationBrief DescriptionThe Get local statistics operation obtains information related to the local node, where theMSTR has been programmed. This operation takes one scan to complete and does notrequire a data master transaction path.

Network ImplementationThe Get Local Statistics operation (type 3 in the displayed register of the top node) canbe implemented for Modbus Plus and TCP/IP EtherNet networks. It is not used forSY/MAX EtherNet.

� Listing of available Modbus Plus network statistics see page 264� Listing of TCP/IP EtherNet network statistics see page 270

Control Block UtilizationIn a Get local statistics operation, the registers in the MSTR control block (the top node)contain the information that differs depending on the type of network you are using:

� Modbus Plus (see Table 15)� TCP/IP EtherNet (see Table 16)


Register Function ContentDisplayed Operation type 3First implied Error status Displays a hex value indicating an MSTR error,

when relevantSecond implied Length Starting from offset, the number of words of statis-

tics from the local processor’s statistics table (seepage 264); the length must be > 0 ≤ data area

Third implied Offset An offset value relative to the first available wordin the local processor’s statistics table; if the off-set is specified as 1, the function obtains statisticsstarting with the second word in the table

Fourth implied Routing 1 If this is the second of two local nodes, set thehigh byte to a value of 1

NoteIf you are using the MSTR instruction for Modbus Plus networking and your PLC doesnot support Modbus Plus option modules (S985s or NOMs), the fourth implied register isnot used.

MSTR

251


20




tics from the local processor’s statistics table; thelength must be > 0 ≤ data area

Third implied Offset An offset value relative to the first available wordin the local processor’s statistics table (see page270), if the offset is specified as 1, the functionobtains statistics starting with the second word inthe table

Fourth implied Slot ID Low byte: slot address of the network adaptermodule

Fifth ... Eighthimplied

Not applicable

5.3 Clear Local Statistics MSTR OperationBrief DescriptionThe Clear local statistics operation clears statistics relative to the local node (where theMSTR has been programmed). This operation takes one scan to complete and does notrequire a data master transaction path.

NoteWhen you issue the ”Clear local statistics” operation, only words 13 ... 22 in the statisticstable (see page 264) are cleared

Network ImplementationThe Clear Local Statistics operation (type 4 in the displayed register of the top node) canbe implemented for Modbus Plus and TCP/IP EtherNet networks. It is not used forSY/MAX EtherNet.


Control Block UtilizationIn a Clear local statistics operation, the registers in the MSTR control block (the topnode) differ according to the type of network in use:


MSTR

20252



when relevantSecond implied ReservedThird implied ReservedFourth implied Routing 1 If this is the second of two local nodes, set the

high byte to a value of 1

NoteIf you are using the MSTR instruction for Modbus Plus networking and your PLC doesnot support Modbus Plus option modules (S985s or NOMs), the fourth implied register isnot used.



when relevantSecond implied ReservedThird implied ReservedFourth implied Slot ID Low byte: slot address of the network adapter

moduleFifth ... Eighth im-plied

Reserved

5.4 Write Global Data MSTR OperationBrief DescriptionThe Write global data operation transfers data to the communications processor in thecurrent node so that it can be sent over the network when the node gets the token. Allnodes on the local network link can receive this data. This operation takes one scan tocomplete and does not require a data master transaction path.

Network ImplementationThe Write global data operation (type 5 in the displayed register of the top node) can beimplemented only for Modbus Plus networks.

Control Block UtilizationThe registers in the MSTR control block (the top node) are used in a Write global dataoperation:

MSTR

253


20


when relevantSecond implied Length Specifies the number of registers from the data

area to be sent to the comm processor; the valueof the length must be ≤ 32 and must not exceedthe size of the data area

Third implied ReservedFourth implied Routing 1 If this is the second of two local nodes, set the

high byte to a value of 1

NoteIf your PLC does not support Modbus Plus option modules (S985s or NOMs), the fourthimplied register is not used.

MSTR

20254

5.5 Read Global Data MSTR OperationBrief DescriptionThe Read global data operation gets data from the communications processor in anynode on the local network link that is providing global data. This operation may requiremultiple scans to complete if global data is not currently available from the requestednode. If global data is available, the operation completes in a single scan. No mastertransaction path is required.

Network ImplementationThe Read global data operation (type 6 in the displayed register of the top node) can beimplemented only for Modbus Plus networks.

Control Block UtilizationThe registers in the MSTR control block (the top node) are used in a Read global dataoperation:


when relevantSecond implied Length Specifies the number of words of global data to

be requested from the comm processor desig-nated by the routing 1 parameter; the value of thelength must be > 0 ≤ 32 and must not exceed thesize of the data area

Third implied Available words Contains the number of words available from therequested node; the value is automatically up-dated by internal software

Fourth implied Routing 1 The low byte specifies the address of the nodewhose global data are to be returned (a value be-tween 1 ... 64); if this is the second of two localnodes, set the high byte to a value of 1

NoteIf your PLC does not support Modbus Plus option modules (S985s or NOMs), the highbyte of the fourth implied register is not used and the high-byte bits must all be set to 0.

MSTR

255


20

5.6 Get Remote Statistics MSTR OperationBrief DescriptionThe Get remote statistics operation obtains information relative to remote nodes on thenetwork. This operation may require multiple scans to complete and does not require amaster data transaction path.

Network ImplementationThe Get Remote Statistics operation (type 7 in the displayed register of the top node)can be implemented for Modbus Plus and TCP/IP EtherNet networks. It is not used forSY/MAX EtherNet.

NoteYou need to understand the routing procedures used by the network you are using whenyou program an MSTR instruction. A full discussion of Modbus Plus routing pathstructures is given in Modbus Plus Network Planning and Installation Guide. IfTCP/IP routing is being implemented, it must be accomplished via standard third-partEthernet IP router products.

Control Block UtilizationIn a Get remote statistics operation, the registers in the MSTR control block (the topnode) contain information that differs according to the network in use:




when relevantSecond implied Length Starting from an offset, the number of words of

statistics to be obtained from a remote node; thelength must be > 0 ≤ total number of statisticsavailable (54) and must not exceed the size of thedata area

Third implied Offset Specifies an offset value relative to the first avail-able word in the statistics table (see page 264),the value must not exceed the number of statisticwords available

Fourth ... eighthimplied


The remote comm processor always returns its complete statistics table when a requestis made, even if the request is for less than the full table. The MSTR instruction thencopies only the amount of words you have requested to the designated 4x registers.

MSTR

20256




tics from the local processor’s statistics table; thelength must be > 0 ≤ data area

Third implied Offset An offset value relative to the first available wordin the local processor’s statistics table (see page270), if the offset is specified as 1, the functionobtains statistics starting with the second word inthe table

Fourth implied Low byte Slot address of the network adapter moduleFifth ... Eighth im-plied


5.7 Clear Remote Statistics MSTR OperationBrief DescriptionThe Clear remote statistics operation clears statistics related to a remote network nodefrom the data area in the local node. This operation may require multiple scans tocomplete and uses a single data master transaction path.

NoteWhen you issue the ”Clear remote statistics” operation, only words 13 ... 22 in thestatistics table (see page 264) are cleared

Network ImplementationThe Clear remote statistics operation (type 8 in the displayed register of the top node)can be implemented for Modbus Plus and TCP/IP EtherNet networks. It is not used forSY/MAX EtherNet.


Control Block UtilizationIn a Clear remote statistics operation, the registers in the MSTR control block (the topnode) contain information that differs according to the network in use:


MSTR

257


20



when relevantSecond implied ReservedThird implied ReservedFourth ... eighthimplied


NoteYou need to understand Modbus Plus routing path procedures before programming anMSTR block. A full discussion of routing path structures is given in Modbus PlusNetwork Planning and Installation Guide.



when relevantSecond implied Not applicableThird implied

Fourth implied Low byte Slot address of the network adapter moduleFifth ... Eighth im-plied


MSTR

20258

5.8 Peer Cop Health MSTR OperationBrief DescriptionThe peer cop health operation reads selected data from the peer cop communicationshealth table and loads that data to specified 4x registers in state RAM. The peer copcommunications health table is 12 words long, and the words are indexed via this MSTRoperation as words 0 ... 11.

Network ImplementationThe Clear remote statistics operation (type 8 in the displayed register of the top node)can be implemented only for Modbus Plus networks.

Control Block UtilizationThe registers in the MSTR control block (the top node) contain the following informationin a Peer cop health operation:


when relevantSecond implied Data Size Number of words requested from peer cop table

(range 1 ... 12)Third implied Index First word from the table to be read (range 0 ...

11, where 0 = the first word in the peer cop tableand 11 = the last word in the table)

Fourth implied Routing 1 If this is the second of two local nodes, set thehigh byte to a value of 1

NoteIf your PLC does not support Modbus Plus option modules (S985s or NOMs), the fourthimplied register is not used.

Peer Cop Communications Health Status InformationThe peer cop communications health table comprises 12 contiguous registers that canbe indexed in an MSTR operation as words 0 ... 11. Each bit in each of the table words isused to represent an aspect of communications health relative to a specific node on theModbus Plus network.

The bits in words 0 ... 3 represent the health of the global input communication expectedfrom nodes 1 ... 64. The bits in words 4 ... 7 represent the health of the output from aspecific node. The bits in words 8 ... 11 represent the health of the input to a specificnode:

MSTR

259


20

Type of Status

WordIndex

33343536373839404142434445464748

49505152535455565758596061626364

Bit–to–Network Node Relationship

GlobalInput 0

1

2

3

12345678910111213141516

17181920212223242526272829303132

33343536373839404142434445464748

49505152535455565758596061626364

SpecificOutput 4

5

6

7

12345678910111213141516

17181920212223242526272829303132

33343536373839404142434445464748

49505152535455565758596061626364

SpecificInput 8

9

10

11

12345678910111213141516

17181920212223242526272829303132

The state of a peer cop health bit reflects the current communication status of itsassociated node. A health bit is set when its associated node accepts inputs for its peercopped input data group or hears that another node has accepted specific output datafrom the its peer copped output data group. A health bit is cleared when nocommunication has occurred for its associated data group within the configured peer cophealth time-out period.

All health bits are cleared when the Put Peer Cop interface command is executed at PLCstart-up time. Table values are not valid until at least one full token rotation cycle hasbeen completed after execution of the Put Peer Cop interface command. The health bitfor a given node is always zero when its associated peer cop entry is null.

MSTR

20260

5.9 Reset Option Module MSTR OperationBrief DescriptionThe Reset option module operation causes a Quantum NOE option module to enter areset cycle to reset its operational environment.

Network ImplementationThe Reset option module operation (type 10 in the displayed register of the top node)can be implemented for TCP/IP and SY/MAX Ethernet networks, accessed via theappropriate network adapter. Modbus Plus networks do not use this operation.

Control Block UtilizationIn a Reset option module operation, the registers in the MSTR control block (the topnode) differ according to the network in use:

� TCP/IP EtherNet (see Table 23� SY/MAX EtherNet (see Table 24)



when relevantSecond implied Not applicableThird impliedFourth implied Slot ID Number displayed in the low byte, in the range

1 ... 16 indicating the slot in the local backplanewhere the option module resides

Fifth ... Eighth im-plied

Not applicable



when relevantSecond implied Not applicableThird impliedFourth implied Slot ID Low byte: slot address of the network adapter

moduleFifth ... eighth im-plied

Not applicable

MSTR

261


20

5.10 Read CTE (Config Extension Table) MSTR OperationBrief DescriptionThe Read CTE operation reads a given number of bytes from the Ethernet configurationextension table to the indicated buffer in PLC memory. The bytes to be read begin at abyte offset from the beginning of the CTE. The content of the EtherNet CTE table isdisplayed in the middle node of the MSTR block.

Network ImplementationThe Read CTE operation (type 11 in the displayed register of the top node) can beimplemented for TCP/IP and SY/MAX Ethernet networks, accessed via the appropriatenetwork adapter. Modbus Plus networks do not use this operation.

Control Block UtilizationIn a Read CTE operation,, the registers in the MSTR control block (the top node) differaccording to the network in use:




when relevantSecond implied Not applicable

Third impliedFourth implied Map index Either a value displayed in the high byte of the

register or not usedSlot ID Number displayed in the low byte, in the range



Not applicable



when relevantSecond implied Data Size Number of words transferredThird implied Base Address Byte offset in PLC register structure indicating

where the CTE bytes will be writtenFourth implied Low byte Slot address of the NOE module

High byte Terminator (FF hex)Fifth ... eighth im-plied

Not applicable

MSTR

20262

CTE Display Implementation (Middle Node)The values in the EtherNet configuration extension table (CTE) are displayed in a seriesof registers in the middle node of the MSTR instruction when a Read CTE operation isimplemented. The middle node contains the first of 11 contiguous 4x registers. Theregisters display the following CTE data:

Parameter Register ContentFrame type Displayed 1 = 802.3y y

2 = EtherNet

IP address First implied First byte of the IP addressSecond implied Second byte of the IP addressThird implied Third byte of the IP address

Fourth implied Fourth byte of the IP addressSubnetwork Fifth implied Hi wordmask Sixth implied Low word

Gateway Seventh implied First byte of the gatewayyEighth implied Second byte of the gatewayNinth implied Third byte of the gatewayTenth implied Fourth byte of the gateway

5.11 Write CTE (Config Extension Table) MSTR OperationBrief DescriptionThe Write CTE operation writes the configuration CTE table from the data specified inthe middle node to an indicated Ethernet configuration extension table or a specified slot.

Network ImplementationThe Write CTE operation (type 12 in the displayed register of the top node) can beimplemented for TCP/IP and SY/MAX Ethernet networks, via the appropriate networkadapter. Modbus Plus networks do not use this operation.

Control Block UtilizationIn a Write CTE operation, the registers in the MSTR control block (the top node) differaccording to the network in use:


MSTR

263


20



when relevantSecond implied Not applicable

Third impliedFourth implied Map index Either a value displayed in the high byte of the

register or not usedSlot ID Number displayed in the low byte, in the range



Not applicable



when relevantSecond implied Data Size Number of words transferredThird implied Base Address Byte offset in PLC register structure indicating

where the CTE bytes will be writtenFourth implied Low byte Slot address of the NOE module

High byte Destination drop numberFifth implied Terminator FF hexSixth ... eighthimplied

Not applicable

MSTR

20264

CTE Display Implementation (Middle Node)The values in the EtherNet configuration extension table (CTE) are displayed in a seriesof registers in the middle node of the MSTR instruction when a Write CTE operation isimplemented. The middle node contains the first of 11 contiguous 4x registers. Theregisters are used to transfer the following CTE data:

Parameter Register ContentFrame type Displayed 1 = 802.3y y

2 = EtherNet

IP address First implied First byte of the IP addressSecond implied Second byte of the IP addressThird implied Third byte of the IP address

Fourth implied Fourth byte of the IP addressSubnetwork Fifth implied Hi wordmask Sixth implied Low word

Gateway Seventh implied First byte of the gatewayyEighth implied Second byte of the gatewayNinth implied Third byte of the gatewayTenth implied Fourth byte of the gateway

6 Network Statistic Tables

The network statistic tables differ according to the network in use:

� Modbus Plus (see page 264)� TCP/IP EtherNet (see page 270)

6.1 Modbus Plus Network StatisticsThe following table shows the statistics available on the Modbus Plus network. You mayacquire this information by using the appropriate MSTR operation or by using Modbusfunction code 8.

NoteWhen you issue the Clear local or Clear remote statistics operations, only words 13 ... 22are cleared.

MSTR

265


20

Word Bits Meaning 00 Node type ID

0 Unknown node type

1 PLC node 2 Modbus bridge node 3 Host computer node

4 Bridge Plus node 5 Peer I/O node

01 0 ... 11 Software version number in hex (to read, strip bits 12–15 from word) 12 ... 14 Reserved 15 Defines Word 15 error counters (see Word 15)

Most significant bit defines use of error counters in Word 15. Least signifi-cant half of upper byte, plus lower byte, contain software version, seeFigure 2.

Figure 2 Software Version / Error Counter

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Word 15 error counter (see Word 15)

Software version number (in hex)

Word Bits Meaning 02 Network address for this station

03 MAC state variable:

0 Power up state 1 Monitor offline state

2 Duplicate offline state 3 Idle state 4 Use token state

5 Work response state 6 Pass token state 7 Solicit response state

8 Check pass state 9 Claim token state 10 Claim response state

04 Peer status (LED code); provides status of this unit relative to the net-work:

0 Monitor link operation 32 Normal link operation

MSTR

20266

Word MeaningBits 64 Never getting token

96 Sole station128 Duplicate station

05 Token pass counter; increments each time this station gets the token

06 Token rotation time in ms

07 LO Data master failed during token ownership bit map HI Program master failed during token ownership bit map

08 LO Data master token owner work bit map HI Program master token owner work bit map

09 LO Data slave token owner work bit map HI Program slave token owner work bit map

10 HI Data slave/get slave command transfer request bit map

11 LO Program master/get master rsp transfer request bit map HI Program slave/get slave command transfer request bit map

12 LO Program master connect status bit map HI Program slave automatic logout request bit map

13 LO Pretransmit deferral error counter HI Receive buffer DMA overrun error counter

14 LO Repeated command received counter HI Frame size error counter

15 If Word 1 bit 15 is not set, Word 15 has the following meaning:

LO Receiver collision–abort error counter HI Receiver alignment error counter

If Word 1 bit 15 is set, Word 15 has the following meaning: LO Cable A framing error

HI Cable B framing error

16 LO Receiver CRC error counter HI Bad packet–length error counter

17 LO Bad link–address error counter HI Transmit buffer DMA–underrun error counter

MSTR

267


20

Word MeaningBits

18 LO Bad internal packet length error counter HI Bad MAC function code error counter

19 LO Communication retry counter HI Communication failed error counter

20 LO Good receive packet success counter HI No response received error counter

21 LO Exception response received error counter HI Unexpected path error counter

22 LO Unexpected response error counter HI Forgotten transaction error counter

23 LO Active station table bit map, nodes 1 ... 8 HI Active station table bit map, nodes 9 ...16

24 LO Active station table bit map, nodes 17 ... 24 HI Active station table bit map, nodes 25 ... 32



27 LO Token station table bit map, nodes 1 ... 8 HI Token station table bit map, nodes 9 ... 16




31 LO Global data present table bit map, nodes 1 ... 8 HI Global data present table bit map, nodes 9 ... 16

MSTR

20268

Word MeaningBits 32 LO Global data present table bit map, nodes 17 ... 24

HI Global data present table bit map, nodes 25 ... 32

33 LO Global data present table bit map, nodes 33 ... 40 HI Global data present table bit map, nodes 41 ... 48

34 LO Global data present table map, nodes 49 ... 56 HI Global data present table bit map, nodes 57 ... 64

35 LO Receive buffer in use bit map, buffer 1–8 HI Receive buffer in use bit map, buffer 9 ... 16

36 LO Receive buffer in use bit map, buffer 17 ... 24 HI Receive buffer in use bit map, buffer 25 ... 32

37 LO Receive buffer in use bit map, buffer 33 ... 40 HI Station management command processed initiation counter

38 LO Data master output path 1 command initiation counter HI Data master output path 2 command initiation counter




42 LO Data slave input path 41 command processed counter HI Data slave input path 42 command processed counter




46 LO Program master output path 81 command initiation counter HI Program master output path 82 command initiation counter

MSTR

269


20

Word MeaningBits


48 LO Program master command initiation counter HI Program master output path 86 command initiation counter


50 LO Program slave input path C1 command processed counter HI Program slave input path C2 command processed counter




MSTR

20270

6.2 TCP/IP Ethernet StatisticsA TCP/IP EtherNet board responds to Get Local Statistics and Set Local Statisticscommands with the following information:

Word Meaning00 ... 02 MAC address—e.g., if the MAC address is 00 00 54 00 12 34, it is displayed as

follows:Word Content 00 00 00 01 00 54 02 34 12

03 Board status: 0x0001 = Running0x4000 = APPI LED (1=ON, 0 = OFF)0x8000 = Link LED

04 and 05 Number of receiver interrupts06 and 07 Number of transmitter interrupts08 and 09 Transmit–timeout error count10 and 11 Collision–detect error count12 and 13 Missed packets14 and 15 Memory error count16 and 17 Number of times driver has restarted lance18 and 19 Receive framing error count20 and 21 Receiver overflow error count22 and 23 Receive CRC error count24 and 25 Receive buffer error count26 and 27 Transmit buffer error count28 and 29 Transmit silo underflow count30 and 31 Late collision count32 and 33 Lost carrier count34 and 35 Number of retries36 and 37 IP address—e.g., if the IP address is 198.202.137.113 (or c6 CA 89 71), it is

displayed as follows:Word Content 36 89 71 37 C6 CA

MU16

271


20

MU16Multiply 16 Bit

1 Brief Description

The MU16 instruction performs signed or unsigned multiplication on the 16-bit values inthe top and middle nodes, then posts the product in two contiguous holding registers inthe bottom node.

2 Representation

2.1 Symbol

value 1

MU16

product

value 2



Data Type Meaning

Top input 0x, 1x None ON = enables value 1 x value 2


value 1(top node)

3x, 4x INT, UINT Multiplicand, can be displayed explicitly as aninteger (range 1 ... 65 535, enter e.g. #65535)or stored in a register


3x, 4x INT, UINT Multiplier, can be displayed explicitly as an in-teger (range 1 ... 65 535) or stored in a register

product(bottom node)

4x INT, UINT First of two contiguous holding registers:displayed register contains half of the productand the implied register contains the other half


MUL

20272

MULMultiply

1 Brief Description

The MUL instruction multiplies unsigned value 1 (its top node) by unsigned value 2 (itsmiddle node) and stores the product in two contiguous holding registers in the bottomnode.

2 Representation

2.1 Symbol

value 1

MUL

result

value 2



Data Type Meaning

Top input 0x, 1x None ON = value 1 multiplied by value 2

value 1(top node)

3x, 4x UINT Multiplicand, can be displayed explicitly as aninteger (range 1 ... 9 999) or stored in a regi-ster


3x, 4x UINT Multiplier, can be displayed explicitly as an in-teger (range 1 ... 9 999) or stored in a register

result (bottom node)

4x UINT Product (first of two contiguous holding regi-sters; displayed: high-order digits; implied: low-order digits)


MUL

273


20

Product of Instruction MUL

For example, if value 1 = 8 000 and value 2 = 2, the product is 16 000. The displayedregister contains the value 0001 (the high-order half of the product), and implied registercontains the value 6 000 (the low-order half of the product).

Example

PLC Modicon 840USE48600_1

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