Pipelined Mul
of 3
Transcript of Pipelined Mul
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library IEEE;use IEEE.std_logic_1164.all;
entity register_64 isport(clk : in std_logic;
clear : in std_logic;input : in std_logic_vector (63 downto 0);output : out std_logic_vector (63 downto 0) );
end entity register_64;
architecture behavior of register_64 isbegin -- behaviorreg_64: process(clk, clear)
beginif clear='1' then -- only onceoutput '0');
elsif clk'event and clk='1' thenoutput
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ab
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gmaddi: for i in 0 to NS-1 generategmaddj: for j in 0 to N-1 generatemaddj1: entity WORK.madd port map
(pout(i)(j+4*i), tcout(i)(j), bout(i)(4*i), aout(i)(j),s(4*i)(j), c(4*i)(j));
maddj2: entity WORK.madd port map(s(4*i)(j+1), c(4*i)(j), bout(i)(4*i+1), aout(i)(j),s(4*i+1)(j), c(4*i+1)(j));
maddj3: entity WORK.madd port map(s(4*i+1)(j+1), c(4*i+1)(j), bout(i)(4*i+2), aout(i)(j),s(4*i+2)(j), c(4*i+2)(j));
maddj4: entity WORK.madd port map(s(4*i+2)(j+1), c(4*i+2)(j), bout(i)(4*i+3), aout(i)(j),s(4*i+3)(j), tcin(i+1)(j));
end generate gmaddj;gmaddjn: for j in N to N generate -- special left sidemaddj1n: entity WORK.madd port map
(pout(i)(j+4*i), tcout(i)(j), bout(i)(4*i), aout(i)(j),s(4*i)(j), c(4*i)(j));
maddj2n: entity WORK.madd port map('0', c(4*i)(j), bout(i)(4*i+1), aout(i)(j),s(4*i+1)(j), c(4*i+1)(j));
maddj3n: entity WORK.madd port map('0', c(4*i+1)(j), bout(i)(4*i+2), aout(i)(j),
s(4*i+2)(j), c(4*i+2)(j));maddj4n: entity WORK.madd port map('0', c(4*i+2)(j), bout(i)(4*i+3), aout(i)(j),s(4*i+3)(j), tcin(i+1)(j));
end generate gmaddjn;pin(i+1)(4*i-1 downto 0)
