PicoBlaze Hello World project using the PicoBlaze 2014/Class_9.pdfPicoBlaze Function Blocks (cont.)...
Transcript of PicoBlaze Hello World project using the PicoBlaze 2014/Class_9.pdfPicoBlaze Function Blocks (cont.)...
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• PicoBlaze • Hello World project using the PicoBlaze
Agenda
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•Why? • Firmware is easier to maintain/modify/deploy • If the constraints of you system can be met by a processor, no reason build dedicated hardware. • Customization – e.g. connectivity to FPGA on-chip functions • Obsolescence Mitigation – soft processor RTL can be purchased to fulfill product lifespan requirements. • Multiple components can be combined for cost and count reduction.
• Multiple processers on same FPGA to control particular functions. • Hardware Acceleration – Slow SW algorithm can be moved to custom HW co-processor and interfaced to processor.
• Why Not? • Design tools more complex as integration of HW/SW.
• What? • ARM, Tensilica, Xilinx, etc. market embedded processors
• How? •Distributed as hard macro or soft core
Embedded Processor
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Xilinx’s Embedded Processors • PicoBlaze
• 8-bit RISC • Distributed as a soft core • Can use the EDK or a free DOS based EDK • Supplied in VHDL
• MicroBlaze • 32-bit RISC Harvard • Distributed as a soft core • Requires Xilinx Embedded Developer Kit (EDK) • DO-254 Compliant version available from Logicircuit
• PowerPC • 32-bit RISC • Instantiated in some higher end FPGAs • Requires Xilinx Embedded Developer Kit (EDK) • PLC Interface
• ARM • Dual core Cortex-A9 MPCore processors • Each run up to 800MHz • AMBA-AXI Interface
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The PicoBlaze Embedded Processor • Downloadable from the 4211 web site or http://www.xilinx.com/products/ipcenter/picoblaze • Core is kcpsm3.v (VHDL version also available) • Uses block ram configured as a PROM for program memory. • Occupies 96 slices or about 2% of the FPGA on our boards • Program memory space occupies 5% of block RAM • 57 Instructions • Up to 200MHz or 100MIPS on a Virtex-II Pro FPGA • Free assembler
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PicoBlaze Block Diagram
1K x 18
Block
Ram
PCaddress 10 31x10
Stack
10
10
Instruction
Decoder
18
interrupt
64x8
Scratchpad
RAM
16x8
General
Purpose
Registers
8in_port 8
8
ALU
IE
C
z
out_port8
port_id8
clk
reset
instruction
read_strobe
write_strobe
interrupt_ack
PicoBlaze Function Blocks
• General Purpose Registers – 16 Byte wide registers (s0 – sF) – Can be renamed for better program clarity – No registers are reserved or have priority – Each result is computed in specified register
• 1024 Instruction PROM – Instructions are 18 bits wide – Instructions are compiled within the FPGA design and automatically loaded
during FPGA config. – Can update code w/o FPGA design recompile.
• ALU – 8 bits wide – Addition and Subtraction – Bitwise AND, OR, and XOR – Arithmetic compare and bitwise test operations – Shift and Rotate operations
Source: Xilinx PicoBlaze User Guide 6
PicoBlaze Function Blocks (cont.)
• Flags – ZERO: indicates results of last op. resulted in zero. – CARRY: depending on last instruction, indicates various conditions
• Scratchpad RAM – 64 Byte – Accessed via the STORE or FETCH commands. – Directly or Indirectly accessable
• I/O – Up to 256 input or output or combination of
• PC – Points to the next instruction – Automatically increments to next instruction – JUMP, CALL, RETURN, and RETURNI instructions and Interrupt and
Reset Events modify auto increment behavior.
Source: Xilinx PicoBlaze User Guide 7
PicoBlaze Function Blocks (cont.)
• CAL/RETURN Stack
– Stores up to 31 instruction addresses
• Allows up to 31 nested CALL sequences
• Interrupt
– Optional asynchronous (w.r.t. instruction cycle) input.
• Reset
– Automatically reset after FPGA configuarion
Source: Xilinx PicoBlaze User Guide 8
PicoBlaze Ports
Source: Xilinx PicoBlaze User Guide 9
User Level
Subfunctions
Can also use dist. ROM if all block ROM used
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port_id and in_port
PicoBlaze
in_port8 read_strobe
port_id 8
...
clk
instruction INPUT s0, (s7)
port_id contents of register s7
mux_out
mux_out_q
Valid Data
Valid Data
read_strobe
Register s0 Valid Data
mux_out
FPGA Logic
Indirect Addressing
0 1 2 3
Should register
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port_id and out_port
PicoBlazeout_port
write_strobe
port_id 8
clk
instruction OUTPUT s0, 65
port_id 65
out_port Contents of Register s0
write_strobe
Q
8D Q
EN
8 Q
Contents of Register s0
address of register R1, (constant)
R1
Performance
• The PicoBlaze on a Spartan-3 FPGA has a maximum clock of 125.3MHz
– Fully static, i.e. operates down to DC.
• All instructions execute in two clock cycles.
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Interrupts
• Single INTERRUPT input – Use FPGA logic to create single interrupt from multiple
sources.
• INTERRUPT disabled upon reset – Enable via the ENABLE INTERRUPT instruction.
• Interrupt signal must be applied for at least two clock cycles. Interrupts must be disabled during ISR.
• Interrupt causes: – processor to execute CALL 3FF (which typically has jump
to ISR) – Preserves ZERO and CARRY flags – Pushes the PC value onto the CALL/RETURN stack.
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Design Flow
Assembler/KCPSM3.exe
my_code.psm ROM_form.coeROM_form.vhd
my_code.v
ROM_form.v
ISE
kcpsm3.v
my_design.v
my_design.ucf
my_design.bit
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Design Flow
Note: kcpsm3 doesn’t run on 64 (and 32?) bit machines. One solution is to download Intel x86 PC emulator that runs DOS from: http://www.dosbox.com According to the Xilinx forums, kcpsm6 won’t work with Spartan-3E.
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The Hello World Project • Displays “hello world” on line 2 starting at character 44
lcd_master.v
LCDDAT[3:0]
LCDELCDRSLCDRW
LCDdebounce.vBTN0
DCM
CCLK
slow_clk
LCDDAT[3:0]
LCDELCDRSLCDRW
LCDCCLK
hello_world.v
kcpsm3.v
Block
Ram
control.v
New
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The program – control.psm CONSTANT LCD_output_port, 40 ; output data and control CONSTANT LCD_E, 01 ; active High Enable CONSTANT LCD_RW, 02 ; Read=1 Write=0 CONSTANT LCD_RS, 04 ; Instruction=0 Data=1 CONSTANT LCD_DB4, 10 ; Data[0] CONSTANT LCD_DB5, 20 ; Data[1] CONSTANT LCD_DB6, 40 ; Data[2] CONSTANT LCD_DB7, 80 ; Data[3] ;ASCII table CONSTANT character_a, 61 CONSTANT character_b, 62 CONSTANT character_c, 63 CONSTANT character_d, 64 ....... syntax: CONSTANT name, value; ; is a comment delimiter
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control.psm - Main
CALL LCD_reset ; Initialize LCD display LOAD s5, 24 ; Line 2 position 4 CALL LCD_cursor ; Set the cursor position CALL disp_hello_world ; Display 'hello world‘ wait: JUMP wait
PC
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control.psm - LCD_reset LCD_reset: CALL delay_20ms ; wait>15ms for display to be ready
LOAD s4, 30 CALL LCD_write_inst4 ; send '3' CALL delay_20ms ; wait > 4.1ms CALL LCD_write_inst4 ; send '3‘ CALL delay_1ms ; wait > 100us CALL LCD_write_inst4 ; send '3' CALL delay_40us ; wait > 40us LOAD s4, 20 CALL LCD_write_inst4 ; send '2' CALL delay_40us ; wait >40us LOAD s5, 28 ; Function set CALL LCD_write_inst8 LOAD s5, 06 ; Entry mode CALL LCD_write_inst8 LOAD s5, 0C ; Display control CALL LCD_write_inst8
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control.psm - LCD_clear
LCD_clear: LOAD s5, 01 ; Display clear CALL LCD_write_inst8 CALL delay_1ms ; wait >1.64ms for display to clear CALL delay_1ms RETURN
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LCD_write_inst4 subroutine
;RS=0 (Instruction), RW=0 (Write), E=0 LCD_write_inst4: AND s4, F0 ;set up RS and RW >40ns before enable pulse OUTPUT s4, LCD_output_port CALL LCD_pulse_E RETURN LCD_pulse_E: XOR s4, LCD_E ;E=1 OUTPUT s4, LCD_output_port CALL delay_1us XOR s4, LCD_E ;E=0 OUTPUT s4, LCD_output_port RETURN
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LCD_write_inst8 subroutine LCD_write_inst8: LOAD s4, s5 AND s4, F0 ; RS=0, RW=0, E=0 CALL LCD_write_inst4 ;write upper nibble CALL delay_1us ;wait >1us LOAD s4, s5 ;select lower nibble with SL0 s4 ;don’t care SL0 s4 ;RS=0 Instruction SL0 s4 ;RW=0 Write SL0 s4 ;E=0 CALL LCD_write_inst4 ;write lower nibble CALL delay_40us ;wait >40us RETURN
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The delay subroutines
CALL delay_1us delay_1us: LOAD s0, delay_1us_constant wait_1us: SUB s0, 01 JUMP NZ, wait_1us RETURN
2 cycles 4 cycles
2 cycles
2 cycles
xB011constant delay_1us_cycles 4
6cycles - 50cycles constant delay_1us_
cycles 50 constant delay_1us_4cycles cycles 6
sec 6-1E sec
cycles 50E6 2cyclesconstantdelay_1us_4cycles2cycles2cycles
CONSTANT delay_1us_constant, 0B
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control.psm - Main
CALL LCD_reset ; Initialize LCD display LOAD s5, 24 ; Line 2 position 4 CALL LCD_cursor ; Set the cursor position CALL disp_hello_world ; Display 'hello world‘ wait: JUMP wait
PC PC
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control.psm - LCD_cursor
LCD_cursor: TEST s5, 10 ; Test for line 1 JUMP Z, set_line2 ;make address in range 80 to 8F for line 1 AND s5, 0F OR s5, 80 CALL LCD_write_inst8 ;set cursor command RETURN ;make address in range C0 to CF for line 2 set_line2: AND s5, 0F OR s5, C0 CALL LCD_write_inst8 ; set cursor command RETURN
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control.psm - Main
CALL LCD_reset ; Initialize LCD display LOAD s5, 24 ; Line 2 position 4 CALL LCD_cursor ; Set the cursor position CALL disp_hello_world ; Display 'hello world‘ wait: JUMP wait
PC
PC
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control.psm - disp_hello_world disp_hello_world: LOAD s5, character_h CALL LCD_write_data LOAD s5, character_e CALL LCD_write_data LOAD s5, character_l CALL LCD_write_data LOAD s5, character_l CALL LCD_write_data LOAD s5, character_o CALL LCD_write_data CALL disp_space LOAD s5, character_w CALL LCD_write_data
............ RETURN
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control.psm - LCD_write_data LCD_write_data: LOAD s4, s5 AND s4, F0 ;RS=0 Instruction, RW=0 Write, E=0 OUTPUT s4, LCD_output_port CALL LCD_pulse_E ;write upper nibble CALL delay_1us ;wait >1us LOAD s4, s5 ;select lower nibble SL0 s4 ;Don't care SL1 s4 ;RS=1 Data SL0 s4 ;RW=0 Write SL0 s4 ;E=0 OUTPUT s4, LCD_output_port CALL LCD_pulse_E ;write lower nibble CALL delay_40us ;wait >40us RETURN
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control.psm - Main
CALL LCD_reset ;initialise LCD display LOAD s5, 24 ;Line 2 position 4 CALL LCD_cursor ; Set the cursor position CALL disp_hello_world ;Display 'hello world‘ wait: JUMP wait
PC PC
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The Hello World Project
LCDDAT[3:0]
LCDELCDRSLCDRW
LCDCCLK
hello_world.v
kcpsm3.v
Block
Ram
control.v
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hello_world.v
module hello_world ( input wire BTN_NORTH, // reset input wire clk, output reg [7:4] lcd_d, output reg lcd_rs, output reg lcd_rw, output reg lcd_e);
wire [9:0] address;
wire [17:0] instruction; wire [7:0] port_id; wire [7:0] out_port; wire write_strobe;
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hello_world.v (cont.) kcpsm3 processor(.address(address), .instruction(instruction), .port_id(port_id), .write_strobe(write_strobe), .out_port(out_port), .read_strobe(), .in_port(8'b0), .interrupt(1'b0), .interrupt_ack(), .reset(BTN_NORTH), .clk(clk));
control program_rom(.address(address), .instruction(instruction), .clk(clk));
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hello_world.v (cont) always @(posedge clk or posedge BTN_NORTH) begin if (BTN_NORTH) {lcd_d, lcd_rs, lcd_rw, lcd_e} <= 0; else if (write_strobe && port_id == 8’h40) begin lcd_d <= out_port[7:4]; lcd_rs <= out_port[2]; lcd_rw <= out_port[1]; lcd_e <= out_port[0]; end // if (write_strobe) end // always @ (posedge clk) endmodule
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The Hello World Project
LCDDAT[3:0]
LCDELCDRSLCDRW
LCDCCLK
hello_world.v
kcpsm3.v
Block
Ram
control.v
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control.v module control (address, instruction, clk); input [9:0] address; input clk; output [17:0] instruction; RAMB16_S18 ram_1024_x_18( .DI(16'h0000),
.DIP (2'b00), .EN (1'b1), .WE (1'b0), .SSR (1'b0), .CLK (clk), .ADDR (address), .DO (instruction[15:0]), .DOP (instruction[17:16]))
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control.v (cont) /*synthesis init_00 = "001B004C056F004C056C004C056C004C0565004C05684004000500700524005A" init_01 = "C001000BA000004C0520A000004C0564004C056C004C0572004C056F004C0577" ... init_3F = "0000000000000000000000000000000000000000000000000000000000000000" initp_00 = "000B0B0DBF3333CFFF3BEAA3E0BEA8F0B8A38B72DCB72DCB4B2CCCCCF33333F3" ... initp_07= "0000000000000000000000000000000000000000000000000000000000000000" */; endmodule
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To run the Hello World Project 1. Go to www.uccs.edu/~gtumbush/4211/PicoBlaze.html and
download/unzip: 1. Xilinx PicoBlaze zip archive 2. Hello World Project archive
2. Open project Hello_World_final
3. If you want to recompile the program do: <Picoblaze Path>/Picoblaze/Assembler/KCPSM3.exe control.psm from a DOS window