ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler...

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ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives

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Page 1: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

ECE 448 – FPGA and ASIC Design with VHDL

Lecture 16

PicoBlaze Instruction Set& Assembler Directives

Page 2: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

2ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• P. Chu, FPGA Prototyping by VHDL Examples

Chapter 15 PicoBlaze Assembly Code Development

Recommended reading

• K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and

7-Series (KCPSM6)

Page 3: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

3

PicoBlaze-6 Programming Model

ECE 448 – FPGA and ASIC Design with VHDL

FFC

FFD

FFE

FFF

Bank ABank B

Page 4: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Syntax and Terminology

Syntax Example Definition

sX

KK

PORT(KK)

PORT((sX))

RAM(KK)

s7

0xAB

PORT(2)

PORT((sa))

RAM(4)

Value at register 7

Constant AB (in hex)

Input value from port 2

Input value from the port specified by register a

Value from RAM location 4

Page 5: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Addressing modes

Direct mode

ADD sa, sf

IN s5, 0x2a

sa <= sa + sf

s5 <= PORT(0x2a)

Indirect mode

STORE s3, (sa)

IN s9, (s2)

RAM((sa)) <= s3

s9 <= PORT((s2))

s7 <= s7 – 0x07

s2 <= s2 + 0x08 + C

Immediate mode

SUB s7, 0x07

ADDC s2, 0x08

Page 6: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

PicoBlaze Development Environments

Xilinx KCPSM3/ 6 OpenPIC IDE

Platform support Windows Windows XP, Windows 7 and 8

Assembler Command-line in DOS window Graphical

Instruction Syntax KCPSM3/ 6 OpenPIC

Instruction Set SimulatorFacilities provided for VHDL simulation Graphical/ Interactive

Simulator Breakpoints N/A Yes

Register Viewer N/A Yes

Memory Viewer N/A Yes

Page 7: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

KCPSM6 Assembler Files

ECE 448 – FPGA and ASIC Design with VHDL

KCPSM6.EXE

Page 8: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Directives of Assembly Language

Function KCPSM3/ 6 Directive OpenPIC DirectiveLocating Code ADDRESS 3FF ORG 0x3FFAliasing Register Names NAMEREG s5, myregname myregname EQU s5Declaring Constants CONSTANT myconstant, 80 myconstant EQU 0x80

Naming the program ROM file

Name using the same base filename as the assembler source file

Specify the VHDL template file in the project settings under processor tab and compiler options

Equating symbolic name for an I/O port ID N/A

sw_port EQU 0x01 ; 8-bit switchessw_in EQU sf IN sw_in, sw_port ; read switch input

data EQU s0 ; reg for tmp dataled_port EQU 0x05OUT data, led_port

Page 9: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Differences between Mnemonics of Instructions

KCPSM3/ 6 Mnemonic OpenPIC Mnemonic

RETURNRET

RETURN CRET C

RETURN NCRET NC

RETURN ZRET Z

RETURN NZ RET NZ

RETURNI ENABLERETI ENABLE

RETURNI DISABLERETI DISABLE

ENABLE INTERRUPTEINT

DISABLE INTERRUPTDINT

Page 10: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Differences between Mnemonics of Instructions

ADDCY sX, sY ADDC sX, sY

SUBCY sX, sY SUBC sX, sY

INPUT sX, (sY) IN sX, (sY)

INPUT sX, kk IN sX, kk

OUTPUT sX, (sY) OUT sX, (sY)

OUTPUT sX, (sY) OUT sX, (sY)

COMPARE sX, sY COMP sX, sY

STORE sX, (sY) STORE sX, (sY)

FETCH sX, (sY) FETCH sX, (sY)

Page 11: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Differences between Programs

Page 12: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Basic Data Movement

Instructions

Page 13: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Data Movement Instructions

LOAD

LOAD sX, sY

sX <= sY

LOAD sX, KK

sX <= KK

IMM, DIR

C Z

- -

Page 14: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Logic Instructions

& Bit Manipulation

Page 15: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Logic instructions

1. AND AND sX, sY

sX <= sX and sY AND sX, KK

sX <= sX and KK

2. OR OR sX, sY sX <= sX or sY OR sX, KK sX <= sX or KK

3. XOR XOR sX, sY

sX <= sX xor sY XOR sX, KK

sX <= sX xor KK

IMM, DIR

C Z

IMM, DIR

IMM, DIR

0

0

0

Page 16: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

QuestionsPerform the following operations

in the assembly language of PicoBlaze

1. Set the most significant bit of the register s0 to 1

2. Clear two middle bits of the register s1

3. Toggle the least significant bit of the register s2

Page 17: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Answers

1. Set the most significant bit of the register s0 to 1BIT7 EQU 0x80

OR s0, BIT7

2. Clear two middle bits of the register s1BITS43C EQU 0xE7

AND s1, BITS43C

3. Toggle the least significant bit of the register s2BIT0 EQU 0x01

XOR s2, BIT0

Page 18: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Arithmetic Instructions

& Multiple-Byte Manipulation

Page 19: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Arithmetic Instructions (1)

IMM, DIR

C Z

Addition

ADD sX, sY

sX <= sX + sY

ADD sX, KK

sX <= sX + KK

ADDC sX, sY

sX <= sX + sY + CARRY

ADDC sX, KK

sX <= sX + KK + CARRY

Page 20: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

QuestionsPerform the following operation

in the assembly language of PicoBlaze

Add two 3-byte numbers X=(x2, x1, x0) and Y=(y2, y1, y0),stored originally in registers (s2, s1, s0) and (s5, s4, s3),accordingly.

Page 21: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Answer

x0 EQU s0x1 EQU s1x2 EQU s2y0 EQU s3y1 EQU s4y2 EQU s5

ADD x0, y0ADDC x1, y1ADDC x2, y2

Page 22: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Arithmetic Instructions (2)

Subtraction

SUB sX, sY

sX <= sX – sY

SUB sX, KK

sX <= sX – KK

SUBC sX, sY

sX <= sX – sY – CARRY

SUBC sX, KK

sX <= sX – KK – CARRY

IMM, DIR

C Z

Page 23: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

QuestionsPerform the following operation

in the assembly language of PicoBlaze

Perform the subtraction X=X-Y, where X=(x2, x1, x0) and Y=(y2, y1, y0), and these variablesare originally stored in registers (s2, s1, s0) and (s5, s4, s3),accordingly.

Page 24: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Answer

x0 EQU s0x1 EQU s1x2 EQU s2y0 EQU s3y1 EQU s4y2 EQU s5

SUB x0, y0SUBC x1, y1SUBC x2, y2

Page 25: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Shifts & Rotations

Page 26: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Edit instructions - Shifts

*All shift instructions affect Zero and Carry flags

Page 27: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Edit instructions - Rotations

*All rotate instructions affect Zero and Carry flags

Page 28: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

QuestionsPerform the following operation

in the assembly language of PicoBlaze

Perform the left shift (C, X) <= X << 1, where X = (x2, x1, x0) is stored in registers (s2, s1, s0),and the most significant bit of X is shifted into the carry flag.

Page 29: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Answer

x0 EQU s0x1 EQU s1x2 EQU s2

SL0 x0SLA x1SLA x2

Page 30: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Test, Compare, and Program Flow Instructions

Page 31: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Test and Compare Instructions

TEST

TEST sX, sY

sX and sY => none

TEST sX, KK

sX and KK => none

COMPARE

COMP sX, sY

sX – sY => none

COMP sX, KK

sX – KK => none

C Z

IMM, DIR

IMM, DIR

C = odd parity of

the result

Page 32: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Program Flow Control Instructions (1)

JUMP AAA

PC <= AAA

JUMP C, AAA

if C=1 then PC <= AAA else PC <= PC + 1

JUMP NC, AAA

if C=0 then PC <= AAA else PC <= PC + 1

JUMP Z, AAA

if Z=1 then PC <= AAA else PC <= PC + 1

JUMP NZ, AAA

if Z=0 then PC <= AAA else PC <= PC + 1

Page 33: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

If-else statementC Assembly language

if (s0 == s1) { ……….}else { ………..}

Page 34: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

If-else statementC Assembly language

if (s0 == s1) { ……….}else { ………..}

COMP s0, s1JUMP NZ, else_branch ……….. JUMP if_doneelse_branch: ………..if_done:

Page 35: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Switch statementC Assembly language

switch (s0) {case value_1: ………. break;case value_2: ………. break;case value_3: ………. break;default: ………. break;}

Page 36: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Switch statementC Assembly language

switch (s0) {case value_1: ………. break;case value_2: ………. break;case value_3: ………. break;default: ………. break;}

COMP s0, value_1JUMP NZ, case_2……….JUMP case_done

case_2: COMP s0, value_2

JUMP NZ, case_3……….JUMP case_done

case_3:COMP s0, value_3JUMP NZ, default……….JUMP case_done

default: ……….case_done:

Page 37: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

For loop

C Assembly language

for(i=MAX, i>=0, i--) { …………… }

Page 38: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

For loop

C Assembly language

for(i=MAX; i>0; i--) { …………… }

LOAD s0, MAXfor_loop:

……….SUB s0, 1JUMP NZ, for_loop

for(i=MAX; i>=0; i--) { …………… }

LOAD s0, MAXfor_loop:

……….SUB s0, 1JUMP NC, for_loop

Page 39: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Subroutines

Page 40: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Subroutine-Related Instructions

CALL AAA

TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA

CALL C | Z , AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1

CALL NC | NZ , AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1

Page 41: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

RET

PC <= STACK[TOS] + 1; TOS <= TOS - 1

RET C | Z if C | Z =1 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1

RET NC | NZ if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1

Subroutine-Related Instructions

Page 42: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Subroutine Call Flow

Page 43: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Instructions Involving

Data Memory

Page 44: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

FETCH

FETCH sX, KK

sX <= RAM(KK)

FETCH sX, (sY)

sX <= RAM((sY)

Data Movement Instructions Involving Data Memory

DIR, IND

C Z

- -STORE

STORE sX, KK

RAM(KK) <= sX

STORE sX, sY

RAM((sY)) <= sX

DIR, IND

- -

Page 45: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Example 1: Clear Data RAM of the size of 64 bytes

;=========================================================

; routine: clr_data_mem

; function: clear data ram

; temp register: data, s2

;=========================================================

RAM_SIZE EQU 0x40 ; size of RAM = 64

clr_data_mem:

load s2, RAM_SIZE ; unitize loop index to 64

load s0, 0x00

clr_mem_loop:

sub s2, 0x01 ;dec loop index

store s0, (s2)

jump nz, clr_mem_loop ;repeat until s2=0

ret

Page 46: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Input/Output

Instructions

Page 47: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Input/Output Instructions

IN

IN sX, KK

sX <= PORT(KK)

IN sX, (sY)

sX <= PORT((sY))

OUT

OUT sX, KK

PORT(KK) <= sX

OUT sX, (sY)

PORT((sY)) <= sX

DIR, IND

DIR, IND

C Z- -

- -

Page 48: ECE 448 – FPGA and ASIC Design with VHDL Lecture 16 PicoBlaze Instruction Set & Assembler Directives.

Example 2: Clear External RAM of the size of 64 bytes

;=========================================================

; routine: clr_ext_mem

; function: clear data ram

; temp register: data, s2

;=========================================================

RAM_SIZE EQU 0x40 ; size of RAM = 64

clr_ext_mem:

load s2, RAM_SIZE ; unitize loop index to 64

load s0, 0x00

clr_mem_loop:

sub s2, 0x01 ;dec loop index

out s0, (s2)

jump nz, clr_mem_loop ;repeat until s2=0

return


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