Phase Locked Loop Basics

7/25/2019 Phase Locked Loop Basics

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Frequency Synthesizers forCommunication Systems

Part of this material came from courtesy of Ari Valero

An a l o g a n d M i x e d -S ig n a l C e n t e r

A M S C

ELEN 665 (Edgar Snchez-Sinencio)


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Outline Introduction

Linear model Charge Pump PLL

Performance Metrics

Design Methodology


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What is a PLL?

From a communications point of view, a phase-lockedloop is an optimum phase estimator

For an input r(t)=Asin(t+ ), the PLL provides anestimate Asin(t+ ML)

How does it work?- Inject sinusoidal signal into the reference input

- The internal oscillator locks to the reference

- Frequency and phase differences between the referenceand internal sinusoid = kor 0

- Internal sinusoid then represents a filtered version of thereference sinusoid


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Where is it used? Frequency Synthesis

Reference frequency for modulation and

demodulation

Clock reference

Radio, Television

Clock Recovery

Serial interfaces (Computers, optical networks)

FM demodulation

Radio


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What does it look like?Phase

Detector

fin

foutLoop

FilterVCO

Phase Detector (PD). Nonlinear block that provides the phase

difference between the input and oscillating signal

Loop Filter (LPF). Eliminates high order harmonics of PD output

and helps to stabilize the loop

Voltage Controlled Oscillator (VCO). Nonlinear device that

generates a sinusoidal signal whose frequency is controlled by its

DC input.

Feedback interconnection. The output of the VCO is fed to the

Phase Detector to generate a phase error signal. This phase error

signal controls the oscillation frequency of the VCO.


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How can we implement a

Frequency Synthesizer with a PLL?

Phase

Detector

Frequency

Divider

fin foutLoop

FilterVCO

If a frequency divider is introduced in the feedback

interconnection, the frequency of the reference input

is multiplied by the feedback factor at the output ofthe PLL

inout fNf =

N Integer -> Integer-N Frequency Synthesizer

N Fractional -> Fractional-N Frequency Synthesizer

From a fixed reference frequency (fin) alarge set of output frequencies (fout)

can be generated


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Linear Model

The following phase domain model

provides a way to study the

characteristics of operation of the loop

A PLL depends on nonlinearoperations to work properly

To analyze its behavior we need tolimit the analysis to the locked state

= PDPFD KV

divin =

)()( tVKtfctrlVCOVCO

=

= t

ctrlVCOVCO dttVKt0

)()(

s

K

sV

ssG VCO

ctrl

VCOVCO =

=

)(

)()(

The output of the phase detector is:

Where the phase difference is:

The output of the VCO is:

Integrating both sides

In s-domain the VCO transfer

function becomes:

Kpd

1N

in

out

G(s)KVCO

s

div

Kpd(in-div)

The Loop Filter transfer function:

)(sG

The loop is considered locked when

the phase and frequency of the

feedback (divided VCO output) isexactly equal to the average phase

and frequency of the input


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)(

)(

)(

)()(

sGKKNs

sGKKN

s

ssH

VCOPD

VCOPD

in

outout +

=

=

)(

)(

)(

)()(

sGKKNs

sGKN

s

ssH

VCOPD

VCOout

+=

=

The order of a PLL is defined by

the number of poles in the open

and closed loop transfer functions

and the type of a PLL indicates the

number of perfect (lossless)integrators in the loop

The closed loop transfer function:

The transfer function from phase error to

output:

PLL Transfer Function

Hold Range: the frequency range over which the PLL is able to statically maintain phase

tracking: H= KPDKVCOG(0).

Lock Range: the frequency range within which the PLL locks within one single-beat note

between the reference frequency and output frequency: L KPDKVCOG().

The Pull-In and Pull-Out Range: The pull-in range, P, is defined as the frequency range

in which the PLL will always become locked. The pull-out range, PO, is defined as the

limit of dynamic stability for the PLL. No simple relationships for these.


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Type I PLL

NKKss

KKsH

VCOPD

VCOPDout

//

/)(

22 ++=

VCOPD

VCOPD

in

outout

KKNs

KKN

s

ssH

+=

=)(

)()(1

VCOPD

VCOPDn

KK

N

N

KK

2

1=

=

1

1)()( 2 +

==s

sGsG

1)(

1)()(

21

23

++

+==

s

ssGsG

22

2

3 2

2

)( nn

nn

out ss

s

sH

++

+

=

+++

=

+=

VCOPD

VCOPD

VCOPDn

KK

N

N

KK

N

KK

2

21

21

)(2

1

)(

1)()( 1 == sGsG

For a Type-I PLL with different Loop Filters G(s) we have the following responses

C1

R2

R1

Vin

Vout

1=R1C12=R2C1


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Type I PLL

10-2

10-1

100

-40

-30

-20

-10

0

10

Mag

nitude(dB)

10-2 10 -1 100-200

-150

-100

-50

0

Frequency [Hz]

Phase(Degree)

|Hout1

(s)|

|Hout2

(s)|

|Hout3

(s)|

Hout1

(s)

Hout2

(s)

Hout3(s)

A drawback of type-I phase-

locked loops is that it is not

possible to set

independently the loop

bandwidth n, the dampingfactor and the loop gain

KPD

KVCO

Comparison of the closed loop transfer function of

the PLL for the three previous loop filters


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Charge Pump PLL (Type-II)Advantages:

Increased locking range

Speed up in capture process

Phase Frequency Detector (PFD) Charge Pump (CP) combinationcreates extra pole at zerofrequency

This pole provides infinite gain atDC, which results in zero phase

error in ideal locked state

PFD

fin fout

VCO

1

N

C1

R1

C2

Charge Pump

Loop Filter

fdiv

VDD

UP

DWN

Iin Vvco

A type-II PLL is the most commonly used

for frequency synthesizer applications, it is

also known as charge-pump PLL

Disadvantages:

Sampled operation introducesspurious tones at the VCO output

Loop bandwidth limited by stabilityconsiderations

Note: This PLL is also known as Digital PLL since the phase comparison and

frequency division are performed digitally


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Phase-Frequency Detector Compares edges of reference

and divided clocks.

If reference clock leads thedivided clock, the UP signal is

asserted. If the divided clock leads thereference clock , the DWNsignal is asserted.

In an ideal PFD no pulses arepresent at the output in thelocked state.

Duty cycle of inputs is notrelevant to the circuitoperation.

The width of the UP/DWNpulses is proportional to thephase difference between theclock inputs.

VDD

UP

DWN

D Q

CLR

D Q

CLR

" 1"

" 1"

Div

In

Out

fREF

UP

DWN

fDIV Typical PFD implementation

Conceptual PFD-CP


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up=0dn=1

up=0dn=0

up=1dn=0

refref

div div

div ref

-0.1 -0.05 0 0.05 0.1

-1

0

1

Phase error (2rad)

Averag

eChargePumpCurrent

(A)

State machine of PFD

Phase response of PFD with dead zone

In practical PFD the delay of the gates creates non-idealities in thephase input/output characteristic.

The PFD can no longer resolve very small phase errors, and adead zone is created.

To solve this problem, extra delay is introduced in the feedbackpath of reset signal.


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ton

tref

t

UP

DWN

In locked state, narrow pulses are generated in

both UP/DWN outputs.

The width of these pulses determines the amount ofnoise introduced to the VCO output by the charge-pump.

Timing mismatch between the UP/DWN pulses is asource of spurious tones.

Output of PFD for locked state


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Charge Pump

The Charge-Pump convertsthe phase error informationprovided by the PFD into a

voltage that controls theVCO frequency.

If the UP input is asserted,S1 is closed and charge isinjected into capacitor C1,increasing voltage Vout

If the DWN input is asserted,S2 is closed and charge isextracted from capacitorC1,decreasing voltage Vout

C1

VDD

UP

DWN

D Q

CLR

D Q

CLR

"1"

"1"

Div

In

VoutS1

S2

Icp

Icp

t

UP

DWN

Vout

Total

CPcurrent

Icp


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Charge PumpCalculating the Detector Gain:

2

Ttup

=

==2

cpup

cppd

I

T

tII

2

cp

pd

IK =

Capacitor C1 is the main

integrating capacitor; it generates

the pole at zero frequency.Resistor R1 introduces a stabilizing

zero. Capacitor C2is added to the

loop filter to reduce the glitches on

the VCO control voltage

The time the UP/DWN signals are

asserted is:

Where T is the reference period and

is the phase difference

measured by the PFD.

The average current provided by the

charge pump for a given is:

Which gives an overall phase

detector gain Kpd of:


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Current mismatch Mismatch between source and sink

currents in the charge pump introducesa finite phase error.

Current leakage When the source/sink currents are off,

leakage currents can flow and modifythe VCO control voltage of the VCO bycharging/discharging the loop filter.Spurs are introduced.

Charge sharing Parasitic capacitances from the switches

share charge with the loop filter whenthe nodes they are connected to have alarge change in their voltage.

Charge injection Occurs when switches are turned off

and the charge in their channels isinjected/extracted to the loop filter.Spurs are introduced

Non-ideal effects of charge pumps

ton

icp

ileak


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Loop Filter Characteristics The PFD-CP and C1 combination introduces a pole atzero frequency.

This pole, along with the zero generated by the VCO

generates -40dB/decade loop gain at low frequency.

If the loop gain crosses 0dB with a slope of-40dB, then the circuit is unstable.

In order to stabilize the circuit, resistor R1 is introduced inseries with C1 to create a zero.

The zero at z reduces the slope of the loop gain to-20dB/decade and stabilizes the circuit.

Capacitor C2 is added to reduce ripples in the VCO controlvoltage. Adds a second pole p2 to the loop filter.

An extra (third) pole can be added to further eliminateVCO ripple, at the expense of phase margin degradation

(stability)

21

21

21

1

2

11

CR

CC

CCR

p

+

=

C1

R1

C2

Iin

Vvco

11

1

CRz=


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Loop Filter

[ ])(1

)(2112111

111

CCRsCRCRs

CsRR

I

VsZ

in

VCO

+++

==

102

103

104

105

106

107

50

60

70

80

90

100

110

120

130

140

Frequency [Hz]

|Z(s)|[dBohm]

[ ])(1

2

)()(

2112111

111

CCRsCRCRs

CsRR

N

IK

N

sZKKsH

cpVCO

VCOPD

in

divol

+++

=

==

=

2

11 tantan

p

c

z

cm

1

2

12 +==

C

Czpzc

Transimpedance of loop filter

The phase margin

The transimpedance of loop filter is:

And the open loop transfer function of the

PLL

The crossover frequency (0dB gain in the Hol(s))


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+

+=

=

1

1tan1tan

tantan

2

1

1

2

11

2

121

C

CC

Cm

p

z

z

p

m

2

12

2

1

1

1

C

C

C

C

cp

cz

+=

+

=

N

RKI

CC

CR

N

KI vcocpvcocpc

1

21

11 +

=

The phase margin, zero and pole frequency

can be written as a function of the capacitor

ratio C1/C2

With these values, the crossover frequencyas a function of PLL parameters can be

obtained.

This form of the equation assumes the

crossover frequency is aligned with the

maximum of the phase margin

This equation shows that the loop bandwidthis not a function of C1, but a function of R1,

Kvco, Icp and N.

In general, the crossover frequency Wc is

equal to the loop bandwidth of the PLL.


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Plotting the open loop response of the PLL

helps to determine graphically the crossover

frequency and phase margin

102

103

104

105

106

107

-100

-50

0

50

100

PLL Open Loop Response

Magnitude

[dB]

10

2

10

3

10

4

10

5

10

6

10

7-180

-160

-140

-120

-100

Phase

f

(Hz)

Degree

PM

c

z

p2

The ratios between c/z andp2/c determine the phase

margin and damping factor of the

PLL.

Thus, the transient characteristics

of the loop are set by them.


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Performance MetricsThe design of frequency synthesizers for RF

systems involves complying to a large set of

specifications, such as:

Tuning Range and Frequency Resolution

Phase Noise

Spurious Signals

Settling Time

Communication standards usually do not include particular block

specifications. It is up to the system/circuit designer to obtain the

proper circuit specifications for each building block


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Frequency Resolution and

AccuracyThe frequency resolution of the

synthesizer is set by the required

channel spacing of the intended

application

5 kHz200 kHz1.710 1.7851.805 1.880

DCS1800

60 kHz20 MHz2.400 2.479IEEE 802.11g

60 kHz5 MHz2.400 2.479IEEE 802.11b

60 kHz20 MHz5.150 5.3505.750 5.850

IEEE 802.11a

75 kHz1 MHz2.400 2.479Bluetooth

Frequency AccuracyFrequency ResolutionTuning range

(GHz)

Standard

The frequency accuracy is related with

the maximum offset that the synthesized

frequency can have, with respect to the

desired center frequency

The frequency resolution affects

the selection of synthesizer

architecture (Integer / Fractional)

The frequency accuracy defines a

boundary for settling time calculation


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Phase Noise

()

dBc/Hz

0

spur

[dBc]

carrier

f

Power

0

0

m

0+

m

Phase noise is a measure of the spectral purity of a signal and is one of the

most important parameters for characterization of the synthesizer

Phase noise degrades the quality of the data in a communication system

( ) ( ))(sin)(1)( 0 tttatv ++=

Assume the PLL output is a sinusoidal tone at 0

with amplitude and phase variation a(t) and (t)respectively

(t) has a random part and a deterministic part

(t)= r(t)+ dsin(dt)

The random part, r(t), accounts for phase

noise and the deterministic part, dsin(dt),for spurious tones


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Phase Noise (continued..)

Assuming the phase variations are a single tone in the phase, (t)=

msin(mt), and the root mean square (rms) value of (t) is much smaller than

1 radian, the output of the oscillator becomes:

( ) ( )[ ]ttAtAtv mmm

osc )(sin)(sin2

)sin()( 000

+++

the output spectrum of the oscillator contains a narrowband FM signal

with a modulation index m and a strong component at thefundamental frequency 0

The oscillator output voltage power spectral density (PSD) is related to the

phase noise PSD

++= )(

2

1)(

2

1)(

2)( 000

2

SSA

SV

)(

2

)(2

mmS

=

The phase noise skirt is directly

translated to noise side lobes

at both sides of the carrier

frequency


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{ }Phase noise is defined as the ratio of the noise power, in abandwidth of 1 Hz at a certain offset frequency from 0, to the

carrier power Pcarrier

{ } ( )

carrier

noise

P

P

=

atbandHz1log10

The actual phase noise at an offset m is:

{ } ][2

)(log10

2

)(log10

2

0 dBcS

A

S mmV

=

+=

The units dBc/Hz refer to the ratio between the noise and the carrier

in dB in a bandwidth of 1 Hz.


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The phase noise at the output of the VCO comes from

Reference clock

Phase-Frequency Detector

Charge PumpLoop Filter

Frequency Divider

VCO Active Devices Noise

Due to this noise, the output of the VCO is no longer a

single frequency tone, but a smeared version

Sometimes the energy is concentrated at frequencies other than

the desired frequency, appearing as a spike above the skirt.This energy is due to a spurious tone.


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Effect of Phase Noise in Received

Signal Unwanted ChannelsDesired

Channel

Received

Signal

Syn

.Output

ReceiverOutput

Noise

Desired signal

Phase Noise

Spurious tone

Desired Tone

fRF

fLO

fIF= fRF- fLO

Phase Noise and Spurious Tones

are mixed with adjacent channels

and degrade the desireddownconverted signal.

The unwanted channels may bemuch larger than the desired

channel (as much as 40dB for

Bluetooth), setting stringent

requirements for phase noise and

spurious signals.


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Phase Noise Specification

The total noise, Pnoise, in a channel with

bandwidth fBW, blocker power Pblkat an

offset frequency from the desiredchannel and a phase noise {} is

{ } )dBc/Hz()dBHz()dBm()dBm( ++= BWblknoise fPP

The equation assumes that the phase

noise is constant (white) in the

channel bandwidth

The signal-to-noise ratio (SNR) of the downconverted signal is:

)dBm()dBm(SNR(dB) noiseIF PP =

{ }[ ])dBHz()dBc/Hz()dBm()dBm(SNR(dB) BWblksig fPP ++=

For a minimum received signal Psig_min, maximum blocker signal Pblk_maxandminimum required SNR, the phase noise specification can be determined as:

{ } )dB(SNR)dBHz()dBm()dBm()dBc/Hz( max_min_


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Phase Noise Numerical Example

For Bluetooth the carrier-to-interferer ratio at a 3MHz offset

is 40dB, the SNR is 16dB, the channel bandwidth is 1MHz.

With these values the phase noise can be calculated

{ }{ } HzdBcMHz

dBHzedBMHz

/1163

16)61log(1040)dBc/Hz(3

Phase Locked Loop Basics

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