Performed byGreenberg Oleg

Kichin Dima

Winter 2010

Supervised by Moshe Mishali

Inna Rivkin

General Algorithm Scheme

1. Expand block: Recieves 4 channels from A/D and expands

them to 12 channels 2. CTF block: Discovers supports out of 12 channels

3. DSP & Detector block**: Reconstructs the Initial Signal

** Implemented in the same FPGA

General Connectivity

Expander BlocksIncluding on Board Memories

•A2D : FIFO on board memory•Coeff. : FIFO on board memory•Main Bus Debug : FIFO on board memory•CTFDebug : FIFO on board memory

•A2D Reader : Reads data from A2D, simulates A2D input•Main Debug Writer : Writes data from main bus to on board FIFO•CTF Debug Writer : Writes data from Expander to debug memory

•Main Bus Interface : Receives data from Expander & sends with high rate •CTF Bus Interface : Receives data from Expander & sends with high rate

•Main Controller : Controls the system operation

•Registers : Contain control data received from PCI

•Pll : On board Pll , similar to all

Block Description

Expander Block Diagram

1. Loading data on board FIFOs from PSI

2. Loading control registers from PSI

3. Transferring data to internal RAMs from external memory

4. Sending Start Loading signal to CTF/DSP/Exp. Units

5. Receiving Ready signal from the CTF/DSP/Exp. Units

6. Sending Ready signal to the main controller. All units ready

7. Main controller Starts the A2D and the system runs

Process FlowSimilar to all Units

Expander State Machine

CTF BlocksIncluding on Board Memories

•Iteration Debug : FIFO on board memory•Matrix : FIFO on board memory•Memory Debug : FIFO on board memory•Matrix internal : RAM memory

•Main Reader : Reads data from memory, simulates input from Exp. main•Exp.Debug Reader: Reads data from memory, simulates input from Exp. L/R•Matrix Writer : Reads ‘A’ matrix from memory, writes to internal memory•Memory Debug Writer: Writes Debug data to memory

•Main Bus Interface : Receives data from main bus & sends with low rate •CTF Bus Interface : Receives data from L/R bus & sends with low rate

•Exp. DebugMod. : Simulates Expander in debug mode•Dsp DebugMod : Simulates DSP in debug mode

•Main Controller : Controls the system operation

•Registers : Contain control data received from PCI

Block Description

CTF Block Diagram

CTF State Machine

DSP BlocksIncluding on Board Memories

•MainBus : FIFO on board memory•Matrix : FIFO on board memory•Delay : FIFO on board memory•Output : FIFO on board memory•Matrix internal : RAM memory

•Main Reader : Reads data from memory, simulates input from Exp. Main•Matrix Writer : Reads ‘A’ matrix from memory, writes to internal memory•Output Writer : Writes outputdata to memory•Fifo Reader : Reads inputdata from delay fifo

•Main Bus Interface : Receives data from main bus & sends with low rate •Ctf DebugMod. : Simulates CTF in debug mode

•Main Controller : Controls the system operation

•Registers : Contain control data received from PCI

Block Description

DSP Block Diagram

DSP State Machine

Expander EntityInputs:Clk_60 – 60MHz input data clockClk_20 – 20MHz main output data clockClk_2 – 2MHz iteration output data clockClk_240 – 240MHz processing clock

From main controller :rst – resetstart_load – memory ready for readnum_of_itr – number of wanted slicepause – pause the system

From CTF :req_pulse – request of new slice

Memory (20[MHz]) :memory_data – data from memorymemory_ack – requested data is ready

From A/D (60[MHz]) :Data_from_AD – input data for the systemData_in_valid – the input is valid

Outputs:ready_to_arch – finished initilizationdata_to_main – main output to CTF/DSP (20[MHz])data_to_main_valid – main output is validdata_to_CTF – iteration output (2[MHz])data_to_CTF_valid – iteration output is validmemory_read_request – request data from memory

CTF EntityOutputs:

To Controller :ready – ready to begin

To Expander :req_pulse – requests next iteration To DSP :support – numbers of supportnum_of_supports – total number of supportssupport_valid – support data is valid

To Matrix RAM :A_addr – Address for data from RAMA_rd_req – read enable

Inputs:Clk_20 – 20MHz main input data clockClk_240 – 240MHz processing clockCLk 160 - 160MHz processing clock or as needed

From controller :reset – resetstart_load– memory ready for readpause – pause the systemN_Frame – FrameThreshhold - OMP stopping cond.Num_Of_Ite r- Number of iterations

From Expander :data_from_exp – iterational datadata_exp_valid - iterational data valid

From DSP : initiate – there has been support change

From Matrix RAM:A_data – data from RAM

From Main interface:data_main– input data for the expanderdata_main_valid– the data is valid

DSP EntityOutputs:column_number– number of columndigital_signals – data outputsamples_valid_out– the output data is validsupport_changed– support change was detected

Inputs:Clk_20 – 20MHz main input data clockClk_240 – 240MHz processing clock

From controller :reset – resetstart– memory ready for readpause – pause the system

From CTF :support – numbers of supportsupport_num – how many support passedsupport_valid – support number is valid

Internal FIFO:samples_from_fifo– data from fifosamples_fifo_valid– the data is valid

From Main interface:samples_from_expander– input data for the expandersamples_expander_valid– the data is valid

From Matrix memory:memory_get – matrix row

What’s Next?17.01 – 31.1

1.2 – 15.216.2 – 28.21.3 – 15.316.3 – 31.31.4 – 15.4

Studying Tools

Blocks Implamintation

Each FPGA integration

Each FPGA simulation

System integration

System simulation

Writing C code

Project Book Writing

Questions

Thank You For Listening.