PCI Local BusSpecification

Revision 2.2

December 18, 1998

Revision 2.2

ii

REVISION REVISION HISTORY DATE

1.0 Original issue 6/22/92

2.0 Incorporated connector and expansion board specification 4/30/93

2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95

2.2 Incorporated ECNs and improved readability 12/18/98

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Copyright © 1992, 1993, 1995, 1998 PCI Special Interest Group

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ContentsChapter 1 Introduction

1.1. Specification Contents............................................................................................................ 1

1.2. Motivation .............................................................................................................................. 1

1.3. PCI Local Bus Applications ................................................................................................... 2

1.4. PCI Local Bus Overview........................................................................................................ 3

1.5. PCI Local Bus Features and Benefits ..................................................................................... 4

1.6. Administration ........................................................................................................................ 6

Chapter 2 Signal Definition

2.1. Signal Type Definition ........................................................................................................... 8

2.2. Pin Functional Groups ............................................................................................................ 8

2.2.1. System Pins ..................................................................................................................... 8

2.2.2. Address and Data Pins..................................................................................................... 9

2.2.3. Interface Control Pins.................................................................................................... 10

2.2.4. Arbitration Pins (Bus Masters Only) ............................................................................. 11

2.2.5. Error Reporting Pins...................................................................................................... 12

2.2.6. Interrupt Pins (Optional) ............................................................................................... 13

2.2.7. Additional Signals ......................................................................................................... 15

2.2.8. 64-Bit Bus Extension Pins (Optional) ........................................................................... 17

2.2.9. JTAG/Boundary Scan Pins (Optional) .......................................................................... 18

2.3. Sideband Signals .................................................................................................................. 19

2.4. Central Resource Functions.................................................................................................. 19

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Chapter 3 Bus Operation

3.1. Bus Commands..................................................................................................................... 21

3.1.1. Command Definition ..................................................................................................... 21

3.1.2. Command Usage Rules ................................................................................................. 23

3.2. PCI Protocol Fundamentals .................................................................................................. 26

3.2.1. Basic Transfer Control .................................................................................................. 26

3.2.2. Addressing ..................................................................................................................... 273.2.2.1. I/O Space Decoding................................................................................................ 283.2.2.2. Memory Space Decoding ....................................................................................... 283.2.2.3. Configuration Space Decoding............................................................................... 30

3.2.3. Byte Lane and Byte Enable Usage ................................................................................ 38

3.2.4. Bus Driving and Turnaround......................................................................................... 39

3.2.5. Transaction Ordering and Posting ................................................................................. 403.2.5.1. Transaction Ordering and Posting for Simple Devices .......................................... 413.2.5.2. Transaction Ordering and Posting for Bridges ....................................................... 42

3.2.6. Combining, Merging, and Collapsing ........................................................................... 44

3.3. Bus Transactions .................................................................................................................. 46

3.3.1. Read Transaction ........................................................................................................... 47

3.3.2. Write Transaction .......................................................................................................... 48

3.3.3. Transaction Termination ............................................................................................... 493.3.3.1. Master Initiated Termination .................................................................................. 493.3.3.2. Target Initiated Termination .................................................................................. 523.3.3.3. Delayed Transactions ............................................................................................. 61

3.4. Arbitration ............................................................................................................................ 68

3.4.1. Arbitration Signaling Protocol ...................................................................................... 70

3.4.2. Fast Back-to-Back Transactions.................................................................................... 72

3.4.3. Arbitration Parking ........................................................................................................ 74

3.5. Latency ................................................................................................................................. 75

3.5.1. Target Latency............................................................................................................... 753.5.1.1. Target Initial Latency ............................................................................................. 753.5.1.2. Target Subsequent Latency .................................................................................... 77

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3.5.2. Master Data Latency...................................................................................................... 78

3.5.3. Memory Write Maximum Completion Time Limit ...................................................... 78

3.5.4. Arbitration Latency ....................................................................................................... 793.5.4.1. Bandwidth and Latency Considerations ................................................................. 803.5.4.2. Determining Arbitration Latency ........................................................................... 823.5.4.3. Determining Buffer Requirements ......................................................................... 87

3.6. Other Bus Operations ........................................................................................................... 88

3.6.1. Device Selection ............................................................................................................ 88

3.6.2. Special Cycle ................................................................................................................. 90

3.6.3. Address/Data Stepping .................................................................................................. 91

3.6.4. Interrupt Acknowledge .................................................................................................. 93

3.7. Error Functions ..................................................................................................................... 93

3.7.1. Parity Generation........................................................................................................... 94

3.7.2. Parity Checking ............................................................................................................. 95

3.7.3. Address Parity Errors .................................................................................................... 95

3.7.4. Error Reporting.............................................................................................................. 953.7.4.1. Data Parity Error Signaling on PERR# .................................................................. 963.7.4.2. Other Error Signaling on SERR# ........................................................................... 973.7.4.3. Master Data Parity Error Status Bit ........................................................................ 983.7.4.4. Detected Parity Error Status Bit ............................................................................. 98

3.7.5. Delayed Transactions and Data Parity Errors ............................................................... 98

3.7.6. Error Recovery .............................................................................................................. 99

3.8. 64-Bit Bus Extension.......................................................................................................... 100

3.8.1. Determining Bus Width During System Initialization ................................................ 104

3.9. 64-bit Addressing ............................................................................................................... 105

3.10. Special Design Considerations ......................................................................................... 108

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Chapter 4 Electrical Specification

4.1. Overview ............................................................................................................................ 113

4.1.1. 5V to 3.3V Transition Road Map ................................................................................ 113

4.1.2. Dynamic vs. Static Drive Specification ...................................................................... 115

4.2. Component Specification ................................................................................................... 115

4.2.1. 5V Signaling Environment .......................................................................................... 1174.2.1.1. DC Specifications ................................................................................................. 1174.2.1.2. AC Specifications ................................................................................................. 1184.2.1.3. Maximum AC Ratings and Device Protection ..................................................... 120

4.2.2. 3.3V Signaling Environment ....................................................................................... 1224.2.2.1. DC Specifications ................................................................................................. 1224.2.2.2. AC Specifications ................................................................................................. 1234.2.2.3. Maximum AC Ratings and Device Protection ..................................................... 125

4.2.3. Timing Specification ................................................................................................... 1264.2.3.1. Clock Specification .............................................................................................. 1264.2.3.2. Timing Parameters................................................................................................ 1284.2.3.3. Measurement and Test Conditions ....................................................................... 129

4.2.4. Indeterminate Inputs and Metastability ....................................................................... 130

4.2.5. Vendor Provided Specification.................................................................................... 131

4.2.6. Pinout Recommendation ............................................................................................. 131

4.3. System (Motherboard) Specification.................................................................................. 132

4.3.1. Clock Skew.................................................................................................................. 132

4.3.2. Reset ............................................................................................................................ 133

4.3.3. Pull-ups........................................................................................................................ 136

4.3.4. Power ........................................................................................................................... 1374.3.4.1. Power Requirements............................................................................................. 1374.3.4.2. Sequencing............................................................................................................ 1374.3.4.3. Decoupling............................................................................................................ 138

4.3.5. System Timing Budget ................................................................................................ 138

4.3.6. Physical Requirements ................................................................................................ 1414.3.6.1. Routing and Layout Recommendations for Four-Layer Motherboards ............... 1414.3.6.2. Motherboard Impedance....................................................................................... 141

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4.3.7. Connector Pin Assignments ........................................................................................ 142

4.4. Expansion Board Specification .......................................................................................... 146

4.4.1. Board Pin Assignment ................................................................................................. 146

4.4.2. Power Requirements.................................................................................................... 1504.4.2.1. Decoupling............................................................................................................ 1504.4.2.2. Power Consumption ............................................................................................. 150

4.4.3. Physical Requirements ................................................................................................ 1514.4.3.1. Trace Length Limits ............................................................................................. 1514.4.3.2. Routing Recommendations for Four-Layer Expansion Boards ........................... 1524.4.3.3. Impedance............................................................................................................. 1524.4.3.4. Signal Loading...................................................................................................... 152

Chapter 5 Mechanical Specification

5.1. Overview ............................................................................................................................ 153

5.2. Expansion Card Physical Dimensions and Tolerances ...................................................... 154

5.2.1. Connector Physical Description .................................................................................. 1685.2.1.1. Connector Physical Requirements........................................................................ 1765.2.1.2. Connector Performance Specification .................................................................. 177

5.2.2. Planar Implementation ................................................................................................ 178

Chapter 6 Configuration Space

6.1. Configuration Space Organization ..................................................................................... 190

6.2. Configuration Space Functions .......................................................................................... 192

6.2.1. Device Identification ................................................................................................... 192

6.2.2. Device Control............................................................................................................. 193

6.2.3. Device Status ............................................................................................................... 196

6.2.4. Miscellaneous Registers .............................................................................................. 198

6.2.5. Base Addresses ............................................................................................................ 2016.2.5.1. Address Maps ....................................................................................................... 2016.2.5.2. Expansion ROM Base Address Register .............................................................. 204

6.3. PCI Expansion ROMs ........................................................................................................ 205

6.3.1. PCI Expansion ROM Contents.................................................................................... 206

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6.3.1.1. PCI Expansion ROM Header Format ................................................................... 2066.3.1.2. PCI Data Structure Format ................................................................................... 207

6.3.2. Power-on Self Test (POST) Code ............................................................................... 209

6.3.3. PC-compatible Expansion ROMs................................................................................ 2096.3.3.1. ROM Header Extensions ...................................................................................... 209

6.4. Vital Product Data ............................................................................................................... 212

6.5. Device Drivers.................................................................................................................... 212

6.6. System Reset ...................................................................................................................... 213

6.7. Capabilities List .................................................................................................................. 213

6.8. Message Signaled Interrupts .............................................................................................. 214

6.8.1. Message Capability Structure....................................................................................... 2146.8.1.1. Capability ID ........................................................................................................ 2156.8.1.2. Next Pointer .......................................................................................................... 2156.8.1.3. Message Control ................................................................................................... 2156.8.1.4. Message Address .................................................................................................. 2176.8.1.5. Message Upper Address (Optional) ..................................................................... 2176.8.1.6. Message Data........................................................................................................ 218

6.8.2. MSI Operation .............................................................................................................. 2186.8.2.1. MSI Transaction Termination .............................................................................. 2206.8.2.2. MSI Transaction Reception and Ordering Requirements .................................... 220

Chapter 7 66 Mhz PCI Specification

7.1. Introduction ........................................................................................................................ 221

7.2. Scope .................................................................................................................................. 221

7.3. Device Implementation Considerations ............................................................................. 222

7.3.1. Configuration Space .................................................................................................... 222

7.4. Agent Architecture ............................................................................................................. 222

7.5. Protocol............................................................................................................................... 222

7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition .............................................................. 222

7.5.2. Latency ........................................................................................................................ 223

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7.6. Electrical Specification....................................................................................................... 223

7.6.1. Overview ..................................................................................................................... 223

7.6.2. Transition Roadmap to 66 MHz PCI........................................................................... 224

7.6.3. Signaling Environment ................................................................................................ 2247.6.3.1. DC Specifications ................................................................................................. 2257.6.3.2. AC Specifications ................................................................................................. 2257.6.3.3. Maximum AC Ratings and Device Protection ..................................................... 226

7.6.4. Timing Specification ................................................................................................... 2267.6.4.1. Clock Specification .............................................................................................. 2267.6.4.2. Timing Parameters................................................................................................ 2287.6.4.3. Measurement and Test Conditions ....................................................................... 229

7.6.5. Vendor Provided Specification ................................................................................... 231

7.6.6. Recommendations ....................................................................................................... 2317.6.6.1. Pinout Recommendations ..................................................................................... 2317.6.6.2. Clocking Recommendations................................................................................. 231

7.7. System (Planar) Specification ............................................................................................ 232

7.7.1. Clock Uncertainty........................................................................................................ 232

7.7.2. Reset ............................................................................................................................ 233

7.7.3. Pullups ......................................................................................................................... 233

7.7.4. Power ........................................................................................................................... 2337.7.4.1. Power Requirements............................................................................................. 2337.7.4.2. Sequencing............................................................................................................ 2337.7.4.3. Decoupling............................................................................................................ 233

7.7.5. System Timing Budget ................................................................................................ 233

7.7.6. Physical Requirements ................................................................................................ 2367.7.6.1. Routing and Layout Recommendations for Four-Layer Boards .......................... 2367.7.6.2. Planar Impedance ................................................................................................. 236

7.7.7. Connector Pin Assignments ........................................................................................ 236

7.8. Expansion Board Specifications......................................................................................... 237

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Appendix A Special Cycle Messages .......................................239

Appendix B State Machines ......................................................241

Appendix C Operating Rules.....................................................251

Appendix D Class Codes...........................................................257

Appendix E System Transaction Ordering...............................267

Appendix F Exclusive Accesses...............................................279

Appendix G I/O Space Address Decoding for Legacy Devices ....................................................285

Appendix H Capability IDs..........................................................287

Appendix I Vital Product Data ...................................................289

Glossary .......................................................................................297

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FiguresFigure 1-1: PCI Local Bus Applications .................................................................................... 2

Figure 1-2: PCI System Block Diagram..................................................................................... 3

Figure 2-1: PCI Pin List ............................................................................................................. 7

Figure 3-1: Address Phase Formats of Configuration Transactions ........................................ 31

Figure 3-2: Layout of CONFIG_ADDRESS Register ............................................................. 32

Figure 3-3: Host Bridge Translation for Type 0 Configuration Transactions Address Phase....................................................................................................... 33

Figure 3-4: Configuration Read ............................................................................................... 38

Figure 3-5: Basic Read Operation ............................................................................................ 47

Figure 3-6: Basic Write Operation ........................................................................................... 48

Figure 3-7: Master Initiated Termination ................................................................................. 50

Figure 3-8: Master-Abort Termination .................................................................................... 51

Figure 3-9: Retry ...................................................................................................................... 55

Figure 3-10: Disconnect With Data.......................................................................................... 56

Figure 3-11: Master Completion Termination ......................................................................... 57

Figure 3-12: Disconnect-1 Without Data Termination ............................................................ 58

Figure 3-13: Disconnect-2 Without Data Termination ............................................................ 58

Figure 3-14: Target-Abort ........................................................................................................ 59

Figure 3-15: Basic Arbitration ................................................................................................. 70

Figure 3-16: Arbitration for Back-to-Back Access .................................................................. 74

Figure 3-17: DEVSEL# Assertion........................................................................................... 89

Figure 3-18: Address Stepping ................................................................................................. 92

Figure 3-19: Interrupt Acknowledge Cycle.............................................................................. 93

Figure 3-20: Parity Operation................................................................................................... 94

Figure 3-21: 64-bit Read Request With 64-bit Transfer ........................................................ 103

Figure 3-22: 64-bit Write Request With 32-bit Transfer ....................................................... 104

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Figure 3-23. 64-Bit Dual Address Read Cycle....................................................................... 107

Figure 4-1: PCI Board Connectors ......................................................................................... 114

Figure 4-2: V/I Curves for 5V Signaling................................................................................ 120

Figure 4-3: Maximum AC Waveforms for 5V Signaling ...................................................... 121

Figure 4-4: V/I Curves for 3.3V Signaling............................................................................. 124

Figure 4-5: Maximum AC Waveforms for 3.3V Signaling ................................................... 125

Figure 4-6: Clock Waveforms ................................................................................................ 126

Figure 4-7: Output Timing Measurement Conditions ............................................................ 129

Figure 4-8: Input Timing Measurement Conditions .............................................................. 129

Figure 4-9: Suggested Pinout for PQFP PCI Component ...................................................... 132

Figure 4-10: Clock Skew Diagram......................................................................................... 133

Figure 4-11: Reset Timing...................................................................................................... 135

Figure 4-12: Measurement of Tprop, 5 Volt Signaling.......................................................... 140

Figure 5-1: PCI Raw Card (5V) ............................................................................................. 155

Figure 5-2: PCI Raw Card (3.3V and Universal) ................................................................... 155

Figure 5-3: PCI Raw Variable Height Short Card (5V, 32-bit) ............................................. 156

Figure 5-4: PCI Raw Variable Height Short Card (3.3V, 32-bit) .......................................... 156

Figure 5-5: PCI Raw Variable Height Short Card (5V, 64-bit) ............................................. 157

Figure 5-6: PCI Raw Variable Height Short Card (3.3V, 64-bit) .......................................... 158

Figure 5-7: PCI Card Edge Connector Bevel ......................................................................... 159

Figure 5-8: ISA Assembly (5V) ............................................................................................. 160

Figure 5-9: ISA Assembly (3.3V and Universal) ................................................................... 160

Figure 5-10: MC Assembly (5V) ........................................................................................... 161

Figure 5-11: MC Assembly (3.3V) ........................................................................................ 161

Figure 5-12: ISA Bracket ....................................................................................................... 162

Figure 5-13: ISA Retainer ...................................................................................................... 163

Figure 5-14: I/O Window Height ........................................................................................... 164

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Figure 5-15: Adapter Installation With Large I/O Connector ................................................ 165

Figure 5-16: MC Bracket Brace ............................................................................................. 166

Figure 5-17: MC Bracket........................................................................................................ 167

Figure 5-18: MC Bracket Details ........................................................................................... 168

Figure 5-19: 32-bit Connector ................................................................................................ 169

Figure 5-20: 5V/32-bit Connector Layout Recommendation ................................................ 169

Figure 5-21: 3.3V/32-bit Connector Layout Recommendation ............................................. 170

Figure 5-22: 5V/64-bit Connector .......................................................................................... 170

Figure 5-23: 5V/64-bit Connector Layout Recommendation ................................................ 170

Figure 5-24: 3.3V/64-bit Connector ....................................................................................... 171

Figure 5-25: 3.3V/64-bit Connector Layout Recommendation ............................................. 171

Figure 5-26: 5V/32-bit Card Edge Connector Dimensions and Tolerances .......................... 172

Figure 5-27: 5V/64-bit Card Edge Connector Dimensions and Tolerances .......................... 172

Figure 5-28: 3.3V/32-bit Card Edge Connector Dimensions and Tolerances ....................... 173

Figure 5-29: 3.3V/64-bit Card Edge Connector Dimensions and Tolerances ....................... 173

Figure 5-30: Universal 32-bit Card Edge Connector Dimensions and Tolerances ................ 174

Figure 5-31: Universal 64-bit Card Edge Connector Dimensions and Tolerances ................ 175

Figure 5-32: PCI Card Edge Connector Contacts .................................................................. 176

Figure 5-33: PCI Connector Location on Planar Relative to Datum on the ISA Connector ....................................................................................... 179

Figure 5-34: PCI Connector Location on Planar Relative to Datum on the EISA Connector..................................................................................... 179

Figure 5-35: PCI Connector Location on Planar Relative to Datum on the MC Connector ....................................................................................... 180

Figure 5-36: 32-bit PCI Riser Connector ............................................................................... 181

Figure 5-37: 32-bit/5V Riser Connector Footprint ................................................................ 182

Figure 5-38: 32-bit/3.3V Riser Connector Footprint ............................................................. 183

Figure 5-39: 64-bit/5V Riser Connector ............................................................................... 184

Figure 5-40: 64-bit/5V Riser Connector Footprint ................................................................ 185

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Figure 5-41: 64-bit/3.3V Riser Connector ............................................................................ 186

Figure 5-42: 64-bit/3.3V Riser Connector Footprint.............................................................. 187

Figure 6-1: Type 00h Configuration Space Header ............................................................... 191

Figure 6-2: Command Register Layout .................................................................................. 193

Figure 6-3: Status Register Layout......................................................................................... 196

Figure 6-4: BIST Register Layout .......................................................................................... 199

Figure 6-5: Base Address Register for Memory .................................................................... 202

Figure 6-6: Base Address Register for I/O ............................................................................. 202

Figure 6-7: Expansion ROM Base Address Register Layout................................................. 205

Figure 6-8: PCI Expansion ROM Structure ........................................................................... 206

Figure 6-9: Typical Image Layout.......................................................................................... 211

Figure 6-10: Example Capabilities List.................................................................................. 213

Figure 6-11: Message Signaled Interrupt Capability Structure .............................................. 214

Figure 7-1: 33 MHz PCI vs. 66 MHz PCI Timing ................................................................. 224

Figure 7-2: 3.3V Clock Waveform......................................................................................... 226

Figure 7-3: Output Timing Measurement Conditions ............................................................ 229

Figure 7-4: Input Timing Measurement Conditions .............................................................. 229

Figure 7-5: Tval(max) Rising Edge........................................................................................ 230

Figure 7-6: Tval(max) Falling Edge....................................................................................... 230

Figure 7-7: Tval (min) and Slew Rate.................................................................................... 231

Figure 7-8: Recommended Clock Routing............................................................................. 232

Figure 7-9: Clock Skew Diagram........................................................................................... 233

Figure 7-10: Measurement of Tprop ...................................................................................... 235

Figure D-1: Programming Interface Byte Layout for IDE Controller Class Code ................ 258

Figure E-1: Example Producer - Consumer Model ................................................................ 269

Figure E-2: Example System with PCI-to-PCI Bridges ......................................................... 276

Figure F-1: Starting an Exclusive Access .............................................................................. 282

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Figure F-2: Continuing an Exclusive Access ......................................................................... 283

Figure F-3: Accessing a Locked Agent .................................................................................. 284

Figure I-1: VPD Capability Structure .................................................................................... 289

Figure I-2: Small Resource Data Type Tag Bit Definitions................................................... 290

Figure I-3: Large Resource Data Type Tag Bit Definitions................................................... 291

Figure I-4: Resource Data Type Flags for a Typical VPD..................................................... 291

Figure I-5: VPD Format ......................................................................................................... 292

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Preface

Specification Supersedes Earlier Documents7KLVGRFXPHQWFRQWDLQVWKHIRUPDOVSHFLILFDWLRQVRIWKHSURWRFROHOHFWULFDODQGPHFKDQLFDOIHDWXUHVRIWKH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQDVWKHSURGXFWLRQYHUVLRQHIIHFWLYH'HFHPEHU7KH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQLVVXHG-XQHLVVXSHUVHGHGE\WKLVVSHFLILFDWLRQ

)ROORZLQJSXEOLFDWLRQRIWKH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQWKHUHPD\EHIXWXUHDSSURYHGHUUDWDDQGRUDSSURYHGFKDQJHVWRWKHVSHFLILFDWLRQSULRUWRWKHLVVXDQFHRIDQRWKHUIRUPDOUHYLVLRQ7RDVVXUHGHVLJQVPHHWWKHODWHVWOHYHOUHTXLUHPHQWVGHVLJQHUVRI3&,GHYLFHVPXVWUHIHUWRWKH3&,6,*KRPHSDJHDWKWWSZZZSFLVLJFRPLQWKHPHPEHUVRQO\VHFWLRQIRUDQ\DSSURYHGFKDQJHV

Incorporation of Engineering Change Requests (ECRs)7KHIROORZLQJ(&5VKDYHEHHQLQFRUSRUDWHGLQWRWKLVSURGXFWLRQYHUVLRQRIWKHVSHFLILFDWLRQ

ECR Description

New Capabilities Changes to configuration structure to define additionalcapabilities of a PCI function

Sub ID Subsystem vendor configuration space changed from optional torequired for most classes of devices

PME# Describes wake-up function and assigns (previously reserved) pinon PCI bus

MECH ECN# 1 Bracket mounting for EMI reduction

MECH ECN# 2 Increase size of I/O window to enable new connectors

MECH ECN# 3 I/O connector volume to enable add-in card insertion

MECH ECN# 4 Riser connector-add-in card interface

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ECR Description

MECH ECN# 5 Tighten critical tolerance to improve add-in card seating

MECH ECN# 6 Mechanical errata (wrong datum ref), components free areas

Posted MemoryWrites

Clarified requirements for posted memory writes to preventsituations which may lead to a deadlock

Tprop Clarifies measurement and determination of Tprop times for33/66 MHz

RST# TIMING New timing requirements between RST# and the first transactionon the bus and the first access to a device

VPD (Revised) Provides alternate access method to vital product data

3.3 V Aux Specifies a standard source of power for power managementwake event logic

Max Retry Time Devices cannot Retry a memory write request for longer than10 µs

Msg Interrupt Method by which an I/O controller can deliver message basedinterrupt

Spread SpectrumClocking

Adds spread spectrum clocking (SSC) to the specification

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Document Conventions7KHIROORZLQJQDPHDQGXVDJHFRQYHQWLRQVDUHXVHGLQWKLVGRFXPHQW

asserted, deasserted The terms asserted and deasserted refer to theglobally visible state of the signal on the clock edge,not to signal transitions.

edge, clock edge The terms edge and clock edge refer to the rising edgeof the clock. On the rising edge of the clock is theonly time signals have any significance on the PCIbus.

# A # symbol at the end of a signal name indicates thatthe signal’s asserted state occurs when it is at a lowvoltage. The absence of a # symbol indicates that thesignal is asserted at a high voltage.

reserved The contents or undefined states or information arenot defined at this time. Using any reserved area inthe PCI specification is not permitted. All areas ofthe PCI specification can only be changed accordingto the by-laws of the PCI Special Interest Group. Anyuse of the reserved areas of the PCI specification willresult in a product that is not PCI-compliant. Thefunctionality of any such product cannot beguaranteed in this or any future revision of the PCIspecification.

signal names Signal names are indicated with this bold font.

signal range A signal name followed by a range enclosed inbrackets, for example AD[31::00], represents a rangeof logically related signals. The first number in therange indicates the most significant bit (msb) and thelast number indicates the least significant bit (lsb).

implementation notes Implementation notes are enclosed in a box. They arenot part of the PCI specification and are included forclarification and illustration only.

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Chapter 1Introduction

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1.2. Motivation:KHQWKH3&,/RFDO%XV6SHFLILFDWLRQZDVRULJLQDOO\GHYHORSHGLQJUDSKLFVRULHQWHGRSHUDWLQJV\VWHPVVXFKDV:LQGRZVDQG26KDGFUHDWHGDGDWDERWWOHQHFNEHWZHHQWKHSURFHVVRUDQGLWVGLVSOD\SHULSKHUDOVLQVWDQGDUG3&,2DUFKLWHFWXUHV0RYLQJSHULSKHUDOIXQFWLRQVZLWKKLJKEDQGZLGWKUHTXLUHPHQWVFORVHUWRWKHV\VWHPVSURFHVVRUEXVFDQHOLPLQDWHWKLVERWWOHQHFN6XEVWDQWLDOSHUIRUPDQFHJDLQVDUHVHHQZLWKJUDSKLFDOXVHULQWHUIDFHV*8,VDQGRWKHUKLJKEDQGZLGWKIXQFWLRQVLHIXOOPRWLRQYLGHR6&6,/$1VHWFZKHQDORFDOEXVGHVLJQLVXVHG

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1.5. PCI Local Bus Features and Benefits7KH3&,/RFDO%XVZDVVSHFLILHGWRHVWDEOLVKDKLJKSHUIRUPDQFHORFDOEXVVWDQGDUGIRUVHYHUDOJHQHUDWLRQVRISURGXFWV7KH3&,VSHFLILFDWLRQSURYLGHVDVHOHFWLRQRIIHDWXUHVWKDWFDQDFKLHYHPXOWLSOHSULFHSHUIRUPDQFHSRLQWVDQGFDQHQDEOHIXQFWLRQVWKDWDOORZGLIIHUHQWLDWLRQDWWKHV\VWHPDQGFRPSRQHQWOHYHO)HDWXUHVDUHFDWHJRUL]HGE\EHQHILWDVIROORZV

High Performance • Transparent upgrade from 32-bit data path at 33 MHz(132 MB/s peak) to 64-bit data path at 33 MHz(264 MB/s peak) and from 32-bit data path at 66 MHz(264 MB/s peak) to 64-bit data path at 66 MHz(528 MB/s peak).

• Variable length linear and cacheline wrap mode burstingfor both read and writes improves write dependentgraphics performance.

• Low latency random accesses (60-ns write access latencyfor 33 MHz PCI or 30-ns for 66 MHz PCI to slaveregisters from master parked on bus).

• Capable of full concurrency with processor/memorysubsystem.

• Synchronous bus with operation up to 33 MHz or 66 MHz.

• Hidden (overlapped) central arbitration.

Low Cost • Optimized for direct silicon (component) interconnection;i.e., no glue logic. Electrical/driver (i.e., total load) andfrequency specifications are met with standard ASICtechnologies and other typical processes.

• Multiplexed architecture reduces pin count (47 signals fortarget; 49 for master) and package size of PCI componentsor provides for additional functions to be built into aparticular package size.

• Single PCI add-in card works in ISA-, EISA-, orMC-based systems (with minimal change to existingchassis designs), reducing inventory cost and end userconfusion.

Ease of Use • Enables full auto configuration support of PCI Local Busadd-in boards and components. PCI devices containregisters with the device information required forconfiguration.

Longevity • Processor independent. Supports multiple families ofprocessors as well as future generations of processors (bybridges or by direct integration).

• Support for 64-bit addressing.

• Both 5-volt and 3.3-volt signaling environments arespecified. Voltage migration path enables smooth industrytransition from 5 volts to 3.3 volts.

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Interoperability/Reliability

• Small form factor add-in boards.

• Present signals allow power supplies to be optimized forthe expected system usage by monitoring add-in boardsthat could surpass the maximum power budgeted by thesystem.

• Over 2000 hours of electrical SPICE simulation withhardware model validation.

• Forward and backward compatibility of 32-bit and 64-bitadd-in boards and components.

• Forward and backward compatibility with 33 MHz and66 MHz add-in boards and components.

• Increased reliability and interoperability of add-in cards bycomprehending the loading and frequency requirements ofthe local bus at the component level, eliminating buffersand glue logic.

• MC-style expansion connectors.

Flexibility • Full multi-master capability allowing any PCI master peer-to-peer access to any PCI master/target.

• A shared slot accommodates either a standard ISA, EISA,or MC board or a PCI add-in board (refer to Chapter 5,"Mechanical Specification" for connector layout details).

Data Integrity • Provides parity on both data and address and allowsimplementation of robust client platforms.

SoftwareCompatibility

• PCI components can be fully compatible with existingdriver and applications software. Device drivers can beportable across various classes of platforms.

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Chapter 2Signal Definition

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InterfaceControl

System

Address& Data

Arbitration(masters only)

PCICOMPLIANT

DEVICE

AD[31::00]

C/BE[3::0]#

FRAME#TRDY#IRDY# LOCK#

REQ#GNT#

IDSELDEVSEL#

CLKRST#

PAR PAR64

SERR#

TDOTDI

TCKTMS

TRST#

JTAG(IEEE 1149.1)

REQ64#ACK64#

AD[63::32]

C/BE[7::4]#

ErrorReporting

64-BitExtension

STOP#

Required Pins Optional Pins

PERR#

InterfaceControl

InterruptsINTB#INTC#INTD#

INTA#

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1 The minimum number of pins for a planar-only device is 45 for a target-only and 47 for a master (PERR#and SERR# are optional for planar-only applications). Systems must support all signals defined for theconnector. This includes individual REQ# and GNT# signals for each connector. The PRSNT[1::2]#pins are not device signals and, therefore, are not included in Figure 2-1, but are required to be connected onadd-in cards.

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2.1. Signal Type Definition7KHIROORZLQJVLJQDOW\SHGHILQLWLRQVDUHIURPWKHYLHZSRLQWRIDOOGHYLFHVRWKHUWKDQWKHDUELWHURUFHQWUDOUHVRXUFH)RUWKHDUELWHUREQ#LVDQLQSXWGNT#LVDQRXWSXWDQGRWKHU3&,VLJQDOVIRUWKHDUELWHUKDYHWKHVDPHGLUHFWLRQDVDPDVWHURUWDUJHW7KHFHQWUDOUHVRXUFHLVD³ORJLFDO´GHYLFHZKHUHDOOV\VWHPW\SHIXQFWLRQVDUHORFDWHGUHIHUWR6HFWLRQIRUPRUHGHWDLOV

in Input is a standard input-only signal.

out Totem Pole Output is a standard active driver.

t/s Tri-State is a bi-directional, tri-state input/output pin.

s/t/s Sustained Tri-State is an active low tri-state signal owned and drivenby one and only one agent at a time. The agent that drives an s/t/s pinlow must drive it high for at least one clock before letting it float. Anew agent cannot start driving a s/t/s signal any sooner than one clockafter the previous owner tri-states it. A pullup is required to sustainthe inactive state until another agent drives it and must be provided bythe central resource.

o/d Open Drain allows multiple devices to share as a wire-OR. A pull-upis required to sustain the inactive state until another agent drives it andmust be provided by the central resource.

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2.2.1. System Pins

CLK in Clock provides timing for all transactions on PCI and is aninput to every PCI device. All other PCI signals, exceptRST#, INTA#, INTB#, INTC#, and INTD#, are sampled onthe rising edge of CLK and all other timing parameters aredefined with respect to this edge. PCI operates up to 33 MHz(refer to Chapter 4) or 66 MHz (refer to Chapter 7) and, ingeneral, the minimum frequency is DC (0 Hz); however,component-specific permissions are described in Chapter 4(refer to Section 4.2.3.1.).

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RST# in Reset is used to bring PCI-specific registers, sequencers, andsignals to a consistent state. What effect RST# has on adevice beyond the PCI sequencer is beyond the scope of thisspecification, except for reset states of required PCIconfiguration registers. A device that can wake the systemwhile in a powered down bus state has additionalrequirements related to RST#. Refer to the PCI PowerManagement Interface Specification for details. AnytimeRST# is asserted, all PCI output signals must be driven totheir benign state. In general, this means they must beasynchronously tri-stated. REQ# and GNT# must both be tri-stated (they cannot be driven low or high during reset). Toprevent AD, C/BE#, and PAR signals from floating duringreset, the central resource may drive these lines during reset(bus parking) but only to a logic low level; they may not bedriven high. Refer to Section 3.8.1. for special requirementsfor AD[63::32], C/BE[7::4]#, and PAR64 when they arenot connected (as in a 64-bit card installed in a 32-bitconnector).

RST# may be asynchronous to CLK when asserted ordeasserted. Although asynchronous, deassertion is guaranteedto be a clean, bounce-free edge. Except for configurationaccesses, only devices that are required to boot the systemwill respond after reset.

2.2.2. Address and Data Pins

AD[31::00] t/s Address and Data are multiplexed on the same PCI pins. Abus transaction consists of an address2 phase followed by oneor more data phases. PCI supports both read and write bursts.

The address phase is the first clock cycle in which FRAME#is asserted. During the address phase, AD[31::00] contain aphysical address (32 bits). For I/O, this is a byte address; forconfiguration and memory, it is a DWORD address. Duringdata phases, AD[07::00] contain the least significant byte(lsb) and AD[31::24] contain the most significant byte (msb).Write data is stable and valid when IRDY# is asserted; readdata is stable and valid when TRDY# is asserted. Data istransferred during those clocks where both IRDY# andTRDY# are asserted.

2 The DAC uses two address phases to transfer a 64-bit address.

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C/BE[3::0]# t/s Bus Command and Byte Enables are multiplexed on the samePCI pins. During the address phase of a transaction,C/BE[3::0]# define the bus command (refer to Section 3.1.for bus command definitions). During the data phase,C/BE[3::0]# are used as Byte Enables. The Byte Enables arevalid for the entire data phase and determine which byte lanescarry meaningful data. C/BE[0]# applies to byte 0 (lsb) andC/BE[3]# applies to byte 3 (msb).

PAR t/s Parity is even3 parity across AD[31::00] and C/BE[3::0]#.Parity generation is required by all PCI agents. PAR is stableand valid one clock after each address phase. For data phases,PAR is stable and valid one clock after either IRDY# isasserted on a write transaction or TRDY# is asserted on a readtransaction. Once PAR is valid, it remains valid until oneclock after the completion of the current data phase. (PARhas the same timing as AD[31::00], but it is delayed by oneclock.) The master drives PAR for address and write dataphases; the target drives PAR for read data phases.

2.2.3. Interface Control Pins

FRAME# s/t/s Cycle Frame is driven by the current master to indicate thebeginning and duration of an access. FRAME# is asserted toindicate a bus transaction is beginning. While FRAME# isasserted, data transfers continue. When FRAME# isdeasserted, the transaction is in the final data phase or hascompleted.

IRDY# s/t/s Initiator Ready indicates the initiating agent’s (bus master’s)ability to complete the current data phase of the transaction.IRDY# is used in conjunction with TRDY#. A data phase iscompleted on any clock both IRDY# and TRDY# areasserted. During a write, IRDY# indicates that valid data ispresent on AD[31::00]. During a read, it indicates the masteris prepared to accept data. Wait cycles are inserted until bothIRDY# and TRDY# are asserted together.

TRDY# s/t/s Target Ready indicates the target agent’s (selected device’s)ability to complete the current data phase of the transaction.TRDY# is used in conjunction with IRDY#. A data phase iscompleted on any clock both TRDY# and IRDY# areasserted. During a read, TRDY# indicates that valid data ispresent on AD[31::00]. During a write, it indicates the targetis prepared to accept data. Wait cycles are inserted until bothIRDY# and TRDY# are asserted together.

STOP# s/t/s Stop indicates the current target is requesting the master tostop the current transaction.

3 The number of "1"s on AD[31::00], C/BE[3::0]#, and PAR equals an even number.

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LOCK# s/t/s Lock indicates an atomic operation to a bridge that mayrequire multiple transactions to complete. When LOCK# isasserted, non-exclusive transactions may proceed to a bridgethat is not currently locked. A grant to start a transaction onPCI does not guarantee control of LOCK#. Control ofLOCK# is obtained under its own protocol in conjunctionwith GNT#. It is possible for different agents to use PCIwhile a single master retains ownership of LOCK#. Lockedtransactions may be initiated only by host bridges, PCI-to-PCIbridges, and expansion bus bridges. Refer to Appendix F fordetails on the requirements of LOCK#.

IDSEL in Initialization Device Select is used as a chip select duringconfiguration read and write transactions.

DEVSEL# s/t/s Device Select, when actively driven, indicates the drivingdevice has decoded its address as the target of the currentaccess. As an input, DEVSEL# indicates whether any deviceon the bus has been selected.

2.2.4. Arbitration Pins (Bus Masters Only)

REQ# t/s Request indicates to the arbiter that this agent desires use ofthe bus. This is a point-to-point signal. Every master has itsown REQ# which must be tri-stated while RST# is asserted.

GNT# t/s Grant indicates to the agent that access to the bus has beengranted. This is a point-to-point signal. Every master has itsown GNT# which must be ignored while RST# is asserted.

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4 REQ# is an input to the arbiter, and GNT# is an output.

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2.2.5. Error Reporting Pins

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PERR# s/t/s Parity Error is only for the reporting of data parity errorsduring all PCI transactions except a Special Cycle. ThePERR# pin is sustained tri-state and must be driven activeby the agent receiving data (when enabled) two clocksfollowing the data when a data parity error is detected. Theminimum duration of PERR# is one clock for each dataphase that a data parity error is detected. (If sequential dataphases each have a data parity error, the PERR# signal willbe asserted for more than a single clock.) PERR# must bedriven high for one clock before being tri-stated as with allsustained tri-state signals. Refer to Section 3.7.4.1. for moredetails.

SERR# o/d System Error is for reporting address parity errors, data parityerrors on the Special Cycle command, or any other systemerror where the result will be catastrophic. If an agent doesnot want a non-maskable interrupt (NMI) to be generated, adifferent reporting mechanism is required. SERR# is pureopen drain and is actively driven for a single PCI clock by theagent reporting the error. The assertion of SERR# issynchronous to the clock and meets the setup and hold timesof all bused signals. However, the restoring of SERR# to thedeasserted state is accomplished by a weak pullup (samevalue as used for s/t/s) which is provided by the centralresource not by the signaling agent. This pullup may take twoto three clock periods to fully restore SERR#. The agent thatreports SERR# to the operating system does so anytimeSERR# is asserted.

5 Some planar devices are granted exceptions (refer to Section 3.7.2. for details).

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2.2.6. Interrupt Pins (Optional)

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INTA# o/d Interrupt A is used to request an interrupt.

INTB# o/d Interrupt B is used to request an interrupt and only hasmeaning on a multi-function device.

INTC# o/d Interrupt C is used to request an interrupt and only hasmeaning on a multi-function device.

INTD# o/d Interrupt D is used to request an interrupt and only hasmeaning on a multi-function device.

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6 When several independent functions are integrated into a single device, it will be referred to as a multi-function device. Each function on a multi-function device has its own configuration space.

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Implementation Note: Interrupt Routing

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Device Number Interrupt Pin on Interrupt Pin onon Motherboard Device Motherboard

0, 4, 8, 12, INTA# IRQW16, 20, 24, 28 INTB# IRQX

INTC# IRQYINTD# IRQZ

1, 5, 9, 13, INTA# IRQX17, 21, 25, 29 INTB# IRQY

INTC# IRQZINTD# IRQW

2, 6, 10, 14, INTA# IRQY18, 22, 26, 30 INTB# IRQZ

INTC# IRQWINTD# IRQX

3, 7, 11, 15, INTA# IRQZ19, 23, 27, 31 INTB# IRQW

INTC# IRQXINTD# IRQY

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2.2.7. Additional Signals

PRSNT[1:2]# in The Present signals are not signals for a device, but areprovided by an add-in board. The Present signals indicate tothe motherboard whether an add-in board is physicallypresent in the slot and, if one is present, the total powerrequirements of the board. These signals are required foradd-in boards but are optional for motherboards. Refer toSection 4.4.1. for more details.

Implementation Note: PRSNT# Pins

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CLKRUN# in, o/d,s/t/s

Clock running is an optional signal used as an input for adevice to determine the status of CLK and an open drainoutput used by the device to request starting or speeding upCLK.

CLKRUN# is a sustained tri-state signal used by thecentral resource to request permission to stop or slow CLK.The central resource is responsible for maintainingCLKRUN# in the asserted state when CLK is running anddeasserts CLKRUN# to request permission to stop or slowCLK. The central resource must provide the pullup forCLKRUN#.

Implementation Note: CLKRUN#

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M66EN in The 66MHZ_ENABLE pin indicates to a device whether thebus segment is operating at 66 or 33 MHz. Refer toSection 7.5.1. for details of this signal’s operation.

PME# o/d The Power Management Event signal is an optional signalthat can be used by a device to request a change in thedevice or system power state. The assertion anddeassertion of PME# is asynchronous to CLK. This signalhas additional electrical requirements over and abovestandard open drain signals that allow it to be sharedbetween devices which are powered off and those whichare powered on. In general, this signal is bused between allPCI connectors in a system, although certainimplementations may choose to pass separate bufferedcopies of the signal to the system logic.

Devices must be enabled by software before asserting thissignal. Once asserted, the device must continue to drivethe signal low until software explicitly clears the conditionin the device.

The use of this pin is specified in the PCI Bus PowerManagement Interface Specification. The system vendormust provide a pull-up on this signal, if it allows the signalto be used. System vendors that do not use this signal arenot required to bus it between connectors or provide pull-ups on those pins.

3.3Vaux in An optional 3.3 volt auxiliary power source delivers powerto the PCI add-in card for generation of power managementevents when the main power to the card has been turned offby software.

The use of this pin is specified in the PCI Bus PowerManagement Interface Specification.

A system or add-in card that does not support PCI buspower management must treat the 3.3Vaux pin as reserved.

Implementation Note: PME# and 3.3Vaux

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2.2.8. 64-Bit Bus Extension Pins (Optional)

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AD[63::32] t/s Address and Data are multiplexed on the same pins andprovide 32 additional bits. During an address phase (whenusing the DAC command and when REQ64# is asserted), theupper 32-bits of a 64-bit address are transferred; otherwise,these bits are reserved7 but are stable and indeterminate.During a data phase, an additional 32-bits of data aretransferred when a 64-bit transaction has been negotiated bythe assertion of REQ64# and ACK64#.

C/BE[7::4]# t/s Bus Command and Byte Enables are multiplexed on the samepins. During an address phase (when using the DACcommand and when REQ64# is asserted), the actual buscommand is transferred on C/BE[7::4]#; otherwise, these bitsare reserved and indeterminate. During a data phase,C/BE[7::4]# are Byte Enables indicating which byte lanescarry meaningful data when a 64-bit transaction has beennegotiated by the assertion of REQ64# and ACK64#.C/BE[4]# applies to byte 4 and C/BE[7]# applies to byte 7.

REQ64# s/t/s Request 64-bit Transfer, when asserted by the current busmaster, indicates it desires to transfer data using 64 bits.REQ64# also has the same timing as FRAME#. REQ64#also has meaning at the end of reset as described in Section3.8.1.

ACK64# s/t/s Acknowledge 64-bit Transfer, when actively driven by thedevice that has positively decoded its address as the target ofthe current access, indicates the target is willing to transferdata using 64 bits. ACK64# has the same timing asDEVSEL#.

PAR64 t/s Parity Upper DWORD is the even8 parity bit that protectsAD[63::32] and C/BE[7::4]#. PAR64 must be valid oneclock after each address phase on any transaction in whichREQ64# is asserted.

PAR64 is stable and valid for 64-bit data phases one clockafter either IRDY# is asserted on a write transaction orTRDY# is asserted on a read transaction. (PAR64 has thesame timing as AD[63::32] but delayed by one clock.) Themaster drives PAR64 for address and write data phases; thetarget drives PAR64 for read data phases.

7 Reserved means reserved for future use by the PCI SIG Steering Committee. Reserved bits must not beused by any device.

8 The number of “1”s on AD[63::32], C/BE[7::4]#, and PAR64 equals an even number.

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2.2.9. JTAG/Boundary Scan Pins (Optional)

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TCK in Test Clock is used to clock state information and test data intoand out of the device during operation of the TAP.

TDI in Test Data Input is used to serially shift test data and testinstructions into the device during TAP operation.

TDO out Test Output is used to serially shift test data and testinstructions out of the device during TAP operation.

TMS in Test Mode Select is used to control the state of the TAPcontroller in the device.

TRST# in Test Reset provides an asynchronous initialization of the TAPcontroller. This signal is optional in IEEE Standard 1149.1.

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2.3. Sideband Signals3&,SURYLGHVDOOEDVLFWUDQVIHUPHFKDQLVPVH[SHFWHGRIDJHQHUDOSXUSRVHPXOWLPDVWHU,2EXV+RZHYHULWGRHVQRWSUHFOXGHWKHRSSRUWXQLW\IRUSURGXFWVSHFLILFIXQFWLRQSHUIRUPDQFHHQKDQFHPHQWVYLDVLGHEDQGVLJQDOV$VLGHEDQGVLJQDOLVORRVHO\GHILQHGDVDQ\VLJQDOQRWSDUWRIWKH3&,VSHFLILFDWLRQWKDWFRQQHFWVWZRRUPRUH3&,FRPSOLDQWDJHQWVDQGKDVPHDQLQJRQO\WRWKHVHDJHQWV6LGHEDQGVLJQDOVDUHSHUPLWWHGIRUWZRRUPRUHGHYLFHVWRFRPPXQLFDWHVRPHDVSHFWRIWKHLUGHYLFHVSHFLILFVWDWHLQRUGHUWRLPSURYHWKHRYHUDOOHIIHFWLYHQHVVRI3&,XWLOL]DWLRQRUV\VWHPRSHUDWLRQ

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Chapter 3Bus Operation

3.1. Bus Commands%XVFRPPDQGVLQGLFDWHWRWKHWDUJHWWKHW\SHRIWUDQVDFWLRQWKHPDVWHULVUHTXHVWLQJ%XVFRPPDQGVDUHHQFRGHGRQWKHC/BE[3::0]#OLQHVGXULQJWKHDGGUHVVSKDVH

3.1.1. Command Definition

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C/BE[3::0]# Command Type

0000000100100011010001010110011110001001101010111100110111101111

Interrupt AcknowledgeSpecial CycleI/O ReadI/O WriteReservedReservedMemory ReadMemory WriteReservedReservedConfiguration ReadConfiguration WriteMemory Read MultipleDual Address CycleMemory Read LineMemory Write and Invalidate

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3.1.2. Command Usage Rules

$OO3&,GHYLFHVH[FHSWKRVWEXVEULGJHVDUHUHTXLUHGWRUHVSRQGDVDWDUJHWWRFRQILJXUDWLRQUHDGDQGZULWHFRPPDQGV$OORWKHUFRPPDQGVDUHRSWLRQDO

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)RUEORFNGDWDWUDQVIHUVWRIURPV\VWHPPHPRU\0HPRU\:ULWHDQG,QYDOLGDWH0HPRU\5HDG/LQHDQG0HPRU\5HDG0XOWLSOHDUHWKHUHFRPPHQGHGFRPPDQGVIRUPDVWHUVFDSDEOHRIVXSSRUWLQJWKHP7KH0HPRU\5HDGRU0HPRU\:ULWHFRPPDQGVFDQEHXVHGLIIRUVRPHUHDVRQWKHPDVWHULVQRWFDSDEOHRIXVLQJWKHSHUIRUPDQFHRSWLPL]LQJFRPPDQGV)RUPDVWHUVXVLQJWKHPHPRU\UHDGFRPPDQGVDQ\OHQJWKDFFHVVZLOOZRUNIRUDOOFRPPDQGVKRZHYHUWKHSUHIHUUHGXVHLVVKRZQEHORZ

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• :KHQUHDGWKHGHYLFHLVUHTXLUHGWRUHWXUQDOOE\WHVUHJDUGOHVVRIWKHE\WHHQDEOHVIRXURUHLJKWGHSHQGLQJXSRQWKHZLGWKRIWKHGDWDWUDQVIHUUHIHUWR6HFWLRQ

• %ULGJHVDUHSHUPLWWHGWRPHUJHZULWHVLQWRWKLVUDQJHUHIHUWR6HFWLRQ

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0HPRU\5HDG :KHQUHDGLQJGDWDLQDQDGGUHVVUDQJHWKDWKDVVLGHHIIHFWVQRWSUHIHWFKDEOHRUUHDGLQJDVLQJOH':25'

0HPRU\5HDG/LQH 5HDGLQJPRUHWKDQD':25'XSWRWKHQH[WFDFKHOLQHERXQGDU\LQDSUHIHWFKDEOHDGGUHVVVSDFH

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7KHWDUJHWVKRXOGWUHDWWKHUHDGFRPPDQGVWKHVDPHHYHQWKRXJKWKH\GRQRWDGGUHVVWKHILUVW':25'RIWKHFDFKHOLQH)RUH[DPSOHDWDUJHWWKDWLVDGGUHVVHGDW':25'LQVWHDGRI':25'VKRXOGRQO\SUHIHWFKWRWKHHQGRIWKHFXUUHQWFDFKHOLQH,IWKH&DFKHOLQH6L]HUHJLVWHULVQRWLPSOHPHQWHGWKHQWKHPDVWHUVKRXOGDVVXPHDFDFKHOLQHVL]HRIHLWKHURUE\WHVDQGXVHWKHUHDGFRPPDQGVUHFRPPHQGHGDERYH7KLVDVVXPHVOLQHDUEXUVWRUGHULQJ

Implementation Note: Using Read Commands

'LIIHUHQWUHDGFRPPDQGVZLOOKDYHGLIIHUHQWDIIHFWVRQV\VWHPSHUIRUPDQFHEHFDXVHKRVWEULGJHVDQG3&,WR3&,EULGJHVPXVWWUHDWWKHFRPPDQGVGLIIHUHQWO\:KHQWKH0HPRU\5HDGFRPPDQGLVXVHGDEULGJHZLOOJHQHUDOO\REWDLQRQO\WKHGDWDWKHPDVWHUUHTXHVWHGDQGQRPRUHVLQFHDVLGHHIIHFWPD\H[LVW7KHEULGJHFDQQRWUHDGPRUHEHFDXVHLWGRHVQRWNQRZZKLFKE\WHVDUHUHTXLUHGIRUWKHQH[WGDWDSKDVH7KDWLQIRUPDWLRQLVQRWDYDLODEOHXQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV+RZHYHUIRU0HPRU\5HDG/LQHDQG0HPRU\5HDG0XOWLSOHWKHPDVWHUJXDUDQWHHVWKDWWKHDGGUHVVUDQJHLVSUHIHWFKDEOHDQGWKHUHIRUHWKHEULGJHFDQREWDLQPRUHGDWDWKDQWKHPDVWHUDFWXDOO\UHTXHVWHG7KLVSURFHVVLQFUHDVHVV\VWHPSHUIRUPDQFHZKHQWKHEULGJHFDQSUHIHWFKDQGWKHPDVWHUUHTXLUHVPRUHWKDQDVLQJOH':25'5HIHUWRWKH3&,3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQIRUDGGLWLRQDOGHWDLOVDQGVSHFLDOFDVHV

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Revision 2.2

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Implementation Note: Stale-Data Problems Caused By NotDiscarding Prefetch Data

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3.2. PCI Protocol Fundamentals7KHEDVLFEXVWUDQVIHUPHFKDQLVPRQ3&,LVDEXUVW$EXUVWLVFRPSRVHGRIDQDGGUHVVSKDVHDQGRQHRUPRUHGDWDSKDVHV3&,VXSSRUWVEXUVWVLQERWK0HPRU\DQG,2$GGUHVV6SDFHV

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3.2.1. Basic Transfer Control

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FRAME# is driven by the master to indicate the beginning and end of atransaction.

IRDY# is driven by the master to indicate that it is ready to transfer data.

TRDY# is driven by the target to indicate that it is ready to transfer data.

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9 The only exceptions are 567,17$,17%,17& and ,17'which are discussed inSections 2.2.1. and 2.2.6.

10 3$5 and 3$5 are treated like an $' line delayed by one clock.

11 The notion of qualifying $' and ,'6(/ signals is fully defined in Section 3.6.3.

12 Note: The address phase consists of two clocks when the command is the Dual Address Cycle (DAC).

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2QFHDPDVWHUKDVDVVHUWHGIRDY#LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHVUHJDUGOHVVRIWKHVWDWHRITRDY#2QFHDWDUJHWKDVDVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL#TRDY#RUSTOP#XQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV1HLWKHUWKHPDVWHUQRUWKHWDUJHWFDQFKDQJHLWVPLQGRQFHLWKDVFRPPLWWHGWRWKHFXUUHQWGDWDWUDQVIHUXQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV$GDWDSKDVHFRPSOHWHVZKHQIRDY#DQG>TRDY#RUSTOP#@DUHDVVHUWHG'DWDPD\RUPD\QRWWUDQVIHUGHSHQGLQJRQWKHVWDWHRITRDY#

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3.2.2. Addressing

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3&,WDUJHWVH[FHSWKRVWEXVEULGJHVDUHUHTXLUHGWRLPSOHPHQW%DVH$GGUHVVUHJLVWHUVWRUHTXHVWDUDQJHRIDGGUHVVHVZKLFKFDQEHXVHGWRSURYLGHDFFHVVWRLQWHUQDOUHJLVWHUVRUIXQFWLRQVUHIHUWR&KDSWHUIRUPRUHGHWDLOV7KHFRQILJXUDWLRQVRIWZDUHXVHVWKH%DVH$GGUHVVUHJLVWHUWRGHWHUPLQHKRZPXFKVSDFHDGHYLFHUHTXLUHVLQDJLYHQDGGUHVVVSDFHDQGWKHQDVVLJQVLISRVVLEOHZKHUHLQWKDWVSDFHWKHGHYLFHZLOOUHVLGH

Implementation Note: Device Address Space

,WLVKLJKO\UHFRPPHQGHGWKDWDGHYLFHUHTXHVWYLD%DVH$GGUHVVUHJLVWHUVWKDWLWVLQWHUQDOUHJLVWHUVEHPDSSHGLQWR0HPRU\6SDFHDQGQRW,26SDFH$OWKRXJKWKHXVHRI,26SDFHLVDOORZHG,26SDFHLVOLPLWHGDQGKLJKO\IUDJPHQWHGLQ3&V\VWHPVDQGZLOOEHFRPHPRUHGLIILFXOWWRDOORFDWHLQWKHIXWXUH5HTXHVWLQJ0HPRU\6SDFHLQVWHDGRI,26SDFHDOORZVDGHYLFHWREHXVHGLQDV\VWHPWKDWGRHVQRWVXSSRUW,26SDFH$GHYLFHPD\PDSLWVLQWHUQDOUHJLVWHULQWRERWK0HPRU\6SDFHDQGRSWLRQDOO\,26SDFHE\XVLQJWZR%DVH$GGUHVVUHJLVWHUVRQHIRU,2DQGWKHRWKHUIRU0HPRU\7KHV\VWHPFRQILJXUDWLRQVRIWZDUHZLOODOORFDWHLISRVVLEOHVSDFHWRHDFK%DVH$GGUHVVUHJLVWHU:KHQWKHDJHQW¶VGHYLFHGULYHULVFDOOHGLWGHWHUPLQHVZKLFKDGGUHVVVSDFHLVWREHXVHGWRDFFHVVWKHGHYLFH,IWKHSUHIHUUHGDFFHVVPHFKDQLVPLV,26SDFHDQGWKH,2%DVH$GGUHVVUHJLVWHUZDVLQLWLDOL]HGWKHQWKHGULYHUZRXOGDFFHVVWKHGHYLFHXVLQJ,2EXVWUDQVDFWLRQVWRWKH,2$GGUHVV6SDFHDVVLJQHG2WKHUZLVHWKHGHYLFHGULYHUZRXOGEHUHTXLUHGWRXVHPHPRU\DFFHVVHVWRWKHDGGUHVVVSDFHGHILQHGE\WKH0HPRU\%DVH$GGUHVVUHJLVWHU1RWH%RWK%DVH$GGUHVVUHJLVWHUVSURYLGHDFFHVVWRWKHVDPHUHJLVWHUVLQWHUQDOO\

:KHQDWUDQVDFWLRQLVLQLWLDWHGRQWKHLQWHUIDFHHDFKSRWHQWLDOWDUJHWFRPSDUHVWKHDGGUHVVZLWKLWV%DVH$GGUHVVUHJLVWHUVWRGHWHUPLQHLILWLVWKHWDUJHWRIWKHFXUUHQWWUDQVDFWLRQ,ILWLVWKHWDUJHWWKHGHYLFHDVVHUWVDEVSEL#WRFODLPWKHDFFHVV)RUPRUHGHWDLOVDERXWDEVSEL#JHQHUDWLRQUHIHUWR6HFWLRQ+RZDWDUJHWFRPSOHWHVDGGUHVVGHFRGHLQHDFKDGGUHVVVSDFHLVGLVFXVVHGLQWKHIROORZLQJVHFWLRQV

Revision 2.2

28

3.2.2.1. I/O Space Decoding

,QWKH,2$GGUHVV6SDFHDOOADOLQHVDUHXVHGWRSURYLGHDIXOOE\WHDGGUHVV7KHPDVWHUWKDWLQLWLDWHVDQ,2WUDQVDFWLRQLVUHTXLUHGWRHQVXUHWKDWAD[1::0]LQGLFDWHWKHOHDVWVLJQLILFDQWYDOLGE\WHIRUWKHWUDQVDFWLRQ

7KHE\WHHQDEOHVLQGLFDWHWKHVL]HRIWKHWUDQVIHUDQGWKHDIIHFWHGE\WHVZLWKLQWKH':25'DQGPXVWEHFRQVLVWHQWZLWKAD[1::0] 7DEOHLOOXVWUDWHVWKHYDOLGFRPELQDWLRQVIRUAD[1::0]DQGWKHE\WHHQDEOHVIRUWKHLQLWLDOGDWDSKDVH

7DEOH%\WH(QDEOHVDQGAD[1::0](QFRGLQJV

AD[1::0] 6WDUWLQJ%\WH 9DOLGBE#[3:0]&RPELQDWLRQV

%\WH [[[RU %\WH [[RU %\WH [RU %\WH RU

1RWHLIBE#[3::0] AD[1::0]FDQKDYHDQ\YDOXH

$IXQFWLRQPD\UHVWULFWZKDWW\SHRIDFFHVVHVLWVXSSRUWVLQ,26SDFH)RUH[DPSOHDGHYLFHPD\UHVWULFWLWVGULYHUWRRQO\DFFHVVWKHIXQFWLRQXVLQJE\WHZRUGRU':25'RSHUDWLRQVDQGLVIUHHWRWHUPLQDWHDOORWKHUDFFHVVHVZLWK7DUJHW$ERUW+RZDGHYLFHXVHVAD[1::0]DQGBE#[3::0]WRGHWHUPLQHZKLFKDFFHVVHVYLRODWHLWVDGGUHVVLQJUHVWULFWLRQVLVLPSOHPHQWDWLRQVSHFLILF

$GHYLFHRWKHUWKDQDQH[SDQVLRQEXVEULGJHWKDWFODLPVOHJDF\,2DGGUHVVHVZKHQHYHULWV,26SDFHHQDEOHELWLVVHWLHZLWKRXWWKHXVHRI%DVH$GGUHVV5HJLVWHUVLVUHIHUUHGWRDVDOHJDF\,2GHYLFH/HJDF\,2GHYLFHVDUHGLVFXVVHGLQ$SSHQGL[*

3.2.2.2. Memory Space Decoding

,QWKH0HPRU\$GGUHVV6SDFHWKHAD[31::02]EXVSURYLGHVD':25'DOLJQHGDGGUHVVAD[1::0]DUHQRWSDUWRIWKHDGGUHVVGHFRGH+RZHYHUAD[1::0]LQGLFDWHWKHRUGHULQZKLFKWKHPDVWHULVUHTXHVWLQJWKHGDWDWREHWUDQVIHUUHG

Revision 2.2

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7DEOHOLVWVWKHEXUVWRUGHULQJUHTXHVWHGE\WKHPDVWHUGXULQJ0HPRU\FRPPDQGVDVLQGLFDWHGRQAD[1::0]

7DEOH%XUVW2UGHULQJ(QFRGLQJ

AD1 AD0 Burst Order0 0 Linear Incrementing0 1 Reserved (disconnect after first data phase)13

1 0 Cacheline Wrap mode1 1 Reserved (disconnect after first data phase)

$OOWDUJHWVDUHUHTXLUHGWRFKHFNAD[1::0]GXULQJDPHPRU\FRPPDQGWUDQVDFWLRQDQGHLWKHUSURYLGHWKHUHTXHVWHGEXUVWRUGHURUWHUPLQDWHWKHWUDQVDFWLRQZLWK'LVFRQQHFWLQRQHRIWZRZD\V7KHWDUJHWFDQXVH'LVFRQQHFW:LWK'DWDGXULQJWKHLQLWLDOGDWDSKDVHRU'LVFRQQHFW:LWKRXW'DWDIRUWKHVHFRQGGDWDSKDVH:LWKHLWKHUWHUPLQDWLRQRQO\DVLQJOHGDWDSKDVHWUDQVIHUVGDWD7KHWDUJHWLVQRWDOORZHGWRWHUPLQDWHWKHWUDQVDFWLRQZLWK5HWU\VROHO\EHFDXVHLWGRHVQRWVXSSRUWDVSHFLILFEXUVWRUGHU,IWKHWDUJHWGRHVQRWVXSSRUWWKHEXUVWRUGHUUHTXHVWHGE\WKHPDVWHUWKHWDUJHWPXVWFRPSOHWHRQHGDWDSKDVHDQGWKHQWHUPLQDWHWKHUHTXHVWZLWK'LVFRQQHFW7KLVHQVXUHVWKDWWKHWUDQVDFWLRQZLOOFRPSOHWHDOEHLWVORZO\VLQFHHDFKUHTXHVWZLOOFRPSOHWHDVDVLQJOHGDWDSKDVHWUDQVDFWLRQ,IDWDUJHWVXSSRUWVEXUVWLQJRQWKHEXVWKHWDUJHWPXVWVXSSRUWWKHOLQHDUEXUVWRUGHULQJ6XSSRUWIRUFDFKHOLQHZUDSLVRSWLRQDO

,QOLQHDUEXUVWRUGHUPRGHWKHDGGUHVVLVDVVXPHGWRLQFUHPHQWE\RQH':25'IRXUE\WHVIRUELWWUDQVDFWLRQVDQGWZR':25'VHLJKWE\WHVIRUELWWUDQVDFWLRQVDIWHUHDFKGDWDSKDVHXQWLOWKHWUDQVDFWLRQLVWHUPLQDWHGDQH[FHSWLRQLVGHVFULEHGLQ6HFWLRQ7UDQVDFWLRQVXVLQJWKH0HPRU\:ULWHDQG,QYDOLGDWHFRPPDQGFDQRQO\XVHWKHOLQHDULQFUHPHQWLQJEXUVWPRGH

$FDFKHOLQHZUDSEXUVWPD\EHJLQDWDQ\DGGUHVVRIIVHWZLWKLQWKHFDFKHOLQH7KHOHQJWKRIDFDFKHOLQHLVGHILQHGE\WKH&DFKHOLQH6L]HUHJLVWHUUHIHUWR6HFWLRQLQ&RQILJXUDWLRQ6SDFHZKLFKLVLQLWLDOL]HGE\FRQILJXUDWLRQVRIWZDUH7KHDFFHVVSURFHHGVE\LQFUHPHQWLQJRQH':25'DGGUHVVWZR':25'6IRUDELWGDWDWUDQVDFWLRQXQWLOWKHHQGRIWKHFDFKHOLQHKDVEHHQUHDFKHGDQGWKHQZUDSVWRWKHEHJLQQLQJRIWKHVDPHFDFKHOLQH,WFRQWLQXHVXQWLOWKHUHVWRIWKHOLQHKDVEHHQWUDQVIHUUHG)RUH[DPSOHDQDFFHVVZKHUHWKHFDFKHOLQHVL]HLVE\WHVIRXU':25'VDQGWKHWUDQVDFWLRQDGGUHVVHV':25'KWKHVHTXHQFHIRUDELWWUDQVDFWLRQZRXOGEH

)LUVWGDWDSKDVHLVWR':25'K

6HFRQGGDWDSKDVHLVWR':25'&KZKLFKLVWKHHQGRIWKHFXUUHQWFDFKHOLQH

7KLUGGDWDSKDVHLVWR':25'KZKLFKLVWKHEHJLQQLQJRIWKHDGGUHVVHGFDFKHOLQH

/DVWGDWDSKDVHLVWR':25'KZKLFKFRPSOHWHVDFFHVVWRWKHHQWLUHFDFKHOLQH

13 This encoded value is reserved and cannot be assigned any “new” meaning for new designs. Newdesigns (master or targets) cannot use this encoding. Note that in an earlier version of this specification, thisencoding had meaning and there are masters that generate it and some targets may allow the transaction tocontinue past the initial data phase.

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,IWKHEXUVWFRQWLQXHVRQFHDFRPSOHWHFDFKHOLQHKDVEHHQDFFHVVHGWKHEXUVWFRQWLQXHVDWWKHVDPH':25'RIIVHWRIWKHQH[WFDFKHOLQH&RQWLQXLQJWKHEXUVWRIWKHSUHYLRXVH[DPSOHZRXOGEH

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6L[WKGDWDSKDVHLVWR':25'&KZKLFKLVWKHHQGRIWKHVHFRQGFDFKHOLQH

6HYHQWKGDWDSKDVHLVWR':25'KZKLFKLVWKHEHJLQQLQJRIWKHVHFRQGFDFKHOLQH

/DVWGDWDSKDVHLVWR':25'KZKLFKFRPSOHWHVDFFHVVWRWKHVHFRQGFDFKHOLQH

,IDWDUJHWGRHVQRWLPSOHPHQWWKH&DFKHOLQH6L]HUHJLVWHUWKHWDUJHWPXVWVLJQDO'LVFRQQHFWZLWKRUDIWHUWKHFRPSOHWLRQRIWKHILUVWGDWDSKDVHLI&DFKHOLQH:UDSRUDUHVHUYHGPRGHLVXVHG

,IDPDVWHUVWDUWVZLWKRQHEXUVWRUGHULQJLWFDQQRWFKDQJHWKHEXUVWRUGHULQJXQWLOWKHFXUUHQWWUDQVDFWLRQHQGVVLQFHWKHEXUVWRUGHULQJLQIRUPDWLRQLVSURYLGHGRQAD[1::0]GXULQJWKHDGGUHVVSKDVH

$GHYLFHPD\UHVWULFWZKDWDFFHVVJUDQXODULW\LWVXSSRUWVLQ0HPRU\6SDFH)RUH[DPSOHDGHYLFHPD\UHVWULFWLWVGULYHUWRRQO\DFFHVVWKHGHYLFHXVLQJE\WHZRUGRU':25'RSHUDWLRQVDQGLVIUHHWRWHUPLQDWHDOORWKHUDFFHVVHVZLWK7DUJHW$ERUW

3.2.2.3. Configuration Space Decoding

(YHU\GHYLFHRWKHUWKDQKRVWEXVEULGJHVPXVWLPSOHPHQW&RQILJXUDWLRQ$GGUHVV6SDFH+RVWEXVEULGJHVPD\RSWLRQDOO\LPSOHPHQW&RQILJXUDWLRQ$GGUHVV6SDFH,QWKH&RQILJXUDWLRQ$GGUHVV6SDFHHDFKIXQFWLRQLVDVVLJQHGDXQLTXHE\WHVSDFHWKDWLVDFFHVVHGGLIIHUHQWO\WKDQ,2RU0HPRU\$GGUHVV6SDFHV&RQILJXUDWLRQUHJLVWHUVDUHGHVFULEHGLQ&KDSWHU7KHIROORZLQJVHFWLRQVGHVFULEH

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3.2.2.3.1. Configuration Commands (Type 0 and Type 1)

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3.2.2.3.2. Software Generation of Configuration Transactions

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14 In versions 2.0 and 2.1 of this specification, two mechanisms were defined. However, only onemechanism (Configuration Mechanism #1) was allowed for new designs and the other (ConfigurationMechanism #2) was included for reference.

Revision 2.2

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:KHQDKRVWEULGJHVHHVDQ,2DFFHVVWKDWIDOOVLQVLGHWKH':25'EHJLQQLQJDW&21),*B'$7$DGGUHVVLWFKHFNVWKH(QDEOHELWDQGWKH%XV1XPEHULQWKH&21),*B$''5(66UHJLVWHU,I(QDEOHELWLVVHWDQGWKH%XV1XPEHUPDWFKHVWKHEULGJHV%XV1XPEHURUDQ\%XV1XPEHUEHKLQGWKHEULGJHDFRQILJXUDWLRQF\FOHWUDQVODWLRQPXVWEHGRQH

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0 0RegisterNumber

DeviceNumber

BusNumber

Reserved

Only One "1" 0 0

CONFIG_ADDRESS

PCI AD BUS

FunctionNumber

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15 If the Device Number field selects an IDSEL line that the bridge does not implement, the bridge mustcomplete the processor access normally, dropping the data on writes and returning all ones on reads. Thebridge may optionally implement this requirement by performing a Type 0 configuration access with noIDSEL asserted. This will terminate with Master-Abort which drops write data and returns all ones onreads.

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34

Implementation Note: Bus Numbers Registers and Peer HostBridges

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3.2.2.3.3. Software Generation of Special Cycles

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Revision 2.2

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3.2.2.3.4. Selection of a Device’s Configuration Space

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3.2.2.3.5. System Generation of IDSEL

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Implementation Note: System Generation of IDSEL

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16 The number of clocks the address bus should be pre-driven is determined from the RC time constant onIDSEL.

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FRAME#

CLK

TRDY#

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C/BE#

ADDRESS

BE#'s

DATA

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IDSEL

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3.2.3. Byte Lane and Byte Enable Usage

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3.2.4. Bus Driving and Turnaround

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17 For a 32-bit data transfer, this means 4 bytes per data phase; for a 64-bit data transfer, this means 8 bytesper data phase.

Revision 2.2

40

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3.2.5. Transaction Ordering and Posting

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Revision 2.2

41

3.2.5.1. Transaction Ordering and Posting for Simple Devices

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Implementation Note: Deadlock When Target and Master NotIndependent

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Revision 2.2

42

Implementation Note: Deadlock When Posted Write Data is NotAccepted

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3.2.5.2. Transaction Ordering and Posting for Bridges

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Revision 2.2

43

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Revision 2.2

44

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3.2.6. Combining, Merging, and Collapsing

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A Memory Write and Invalidate transaction is not governed by theLatency Timer except at cacheline boundaries. A master that initiatesa transaction with the Memory Write and Invalidate command ignoresthe Latency Timer until a cacheline boundary. When the transactionreaches a cacheline boundary and the Latency Timer has expired (andGNT# is deasserted), the master must terminate the transaction.

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3.3.3.2. Target Initiated Termination

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5HWU\ refers to termination requested before any data is transferred becausethe target is busy and temporarily unable to process the transaction.This condition may occur, for example, because the device cannotmeet the initial latency requirement, is currently locked by anothermaster, or there is a conflict for a internal resource.

Retry is a special case of Disconnect without data being transferred onthe initial data phase.

The target signals Retry by asserting STOP# and not assertingTRDY# on the initial data phase of the transaction (STOP# cannot beasserted during the turn-around cycle between the address phase andfirst data phase of a read transaction). When the target uses Retry, nodata is transferred.

Disconnect refers to termination requested with or after data was transferred onthe initial data phase because the target is unable to respond within thetarget subsequent latency requirement and, therefore, is temporarilyunable to continue bursting. This might be because the burst crosses aresource boundary or a resource conflict occurs. Data may or may nottransfer on the data phase where Disconnect is signaled. Notice thatDisconnect differs from Retry in that Retry is always on the initialdata phase, and no data transfers. If data is transferred with or beforethe target terminates the transaction, it is a Disconnect. This may alsooccur on the initial data phase because the target is not capable ofdoing a burst.

Disconnect with data may be signaled on any data phase by assertingTRDY# and STOP# together. This termination is used when thetarget is only willing to complete the current data phase and no more.

Disconnect without data may be signaled on any subsequent dataphase (meaning data was transferred on the previous data phase) bydeasserting TRDY# and asserting STOP#.

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Target-Abort refers to an abnormal termination requested because the targetdetected a fatal error or the target will never be able to complete therequest. Although it may cause a fatal error for the applicationoriginally requesting the transaction, the transaction completesgracefully, thus, preserving normal operation for other agents. Forexample, a master requests all bytes in an I/O Address SpaceDWORD to be read, but the target design restricts access to a singlebyte in this range. Since the target cannot complete the request, thetarget terminates the request with Target-Abort.

Once the target has claimed an access by asserting DEVSEL#, it cansignal Target-Abort on any subsequent clock. The target signalsTarget-Abort by deasserting DEVSEL# and asserting STOP# at thesame time.

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Revision 2.2

64

3.3.3.3.3. Discarding a Delayed Transaction

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3.3.3.3.4. Memory Writes and Delayed Transactions

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Revision 2.2

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Implementation Note: Deadlock When Memory Write Data is NotAccepted

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Revision 2.2

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Revision 2.2

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Revision 2.2

69

Implementation Note: System Arbitration Algorithm

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Revision 2.2

70

3.4.1. Arbitration Signaling Protocol

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19 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would winarbitration at a given instant in time.

Revision 2.2

71

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Revision 2.2

72

3.4.2. Fast Back-to-Back Transactions

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The second type of fast back-to-back support places the burden of no contention on allpotential targets. The Fast Back-to-Back Capable bit in the Status register may behardwired to a logical one (high) if, and, only if, the device, while acting as a bus target,meets the following two requirements:

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20 It is recommended that this be done by returning the target state machine (refer to Appendix B) from theB_BUSY state to the IDLE state as soon as FRAME# is deasserted and the device’s decode time has beenmet (a miss occurs) or when DEVSEL# is asserted by another target and not waiting for a bus Idle state(IRDY# deasserted).

Revision 2.2

73

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Revision 2.2

74

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3.4.3. Arbitration Parking

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Revision 2.2

75

3.5. Latency3&,LVDORZODWHQF\KLJKWKURXJKSXW,2EXV%RWKWDUJHWVDQGPDVWHUVDUHOLPLWHGDVWRWKHQXPEHURIZDLWVWDWHVWKH\FDQDGGWRDWUDQVDFWLRQ)XUWKHUPRUHHDFKPDVWHUKDVDSURJUDPPDEOHWLPHUOLPLWLQJLWVPD[LPXPWHQXUHRQWKHEXVGXULQJWLPHVRIKHDY\EXVWUDIILF*LYHQWKHVHWZROLPLWVDQGWKHEXVDUELWUDWLRQRUGHUZRUVWFDVHEXVDFTXLVLWLRQODWHQFLHVFDQEHSUHGLFWHGZLWKUHODWLYHO\KLJKSUHFLVLRQIRUDQ\3&,EXVPDVWHU(YHQEULGJHVWRVWDQGDUGH[SDQVLRQEXVHVZLWKORQJDFFHVVWLPHV,6$(,6$RU0&FDQEHGHVLJQHGWRKDYHPLQLPDOLPSDFWRQWKH3&,EXVDQGVWLOONHHS3&,EXVDFTXLVLWLRQODWHQF\SUHGLFWDEOH

3.5.1. Target Latency

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3.5.1.1. Target Initial Latency

7DUJHWLQLWLDOODWHQF\LVWKHQXPEHURIFORFNVIURPWKHDVVHUWLRQRIFRAME#WRWKHDVVHUWLRQRITRDY#ZKLFKFRPSOHWHVWKHLQLWLDOGDWDSKDVHRUWRWKHDVVHUWLRQRISTOP#LQWKH5HWU\DQG7DUJHW$ERUWFDVHV7KLVQXPEHURIFORFNVYDULHVGHSHQGLQJRQZKHWKHUWKHFRPPDQGLVDUHDGRUZULWHDQGLIDZULWHZKHWKHULWFDQEHSRVWHGRUQRW$PHPRU\ZULWHFRPPDQGVKRXOGVLPSO\EHSRVWHGE\WKHWDUJHWLQDEXIIHUDQGZULWWHQWRWKHILQDOGHVWLQDWLRQODWHU,QWKLVFDVHWKHWDUJHWLQLWLDOODWHQF\LVVPDOOEHFDXVHWKHWUDQVDFWLRQZDVVLPSO\DUHJLVWHUWRUHJLVWHUWUDQVIHU0HHWLQJWDUJHWLQLWLDOODWHQF\RQUHDGWUDQVDFWLRQVLVPRUHGLIILFXOWVLQFHWKLVODWHQF\LVDFRPELQDWLRQRIWKHDFFHVVWLPHRIWKHVWRUDJHPHGLDHJGLVN'5$0HWFDQGWKHGHOD\RIWKHLQWHUIDFHORJLF0HHWLQJLQLWLDOODWHQF\RQ,2DQGFRQILJXUDWLRQZULWHWUDQVDFWLRQVDUHVLPLODUWRUHDGODWHQF\

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Revision 2.2

76

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Implementation Note: Working with Older Targets that Violate theTarget Initial Latency Specification

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Revision 2.2

77

Implementation Note: An Example of Option 2

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Implementation Note: Using More Than One Option to Meet InitialLatency

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3.5.1.2. Target Subsequent Latency

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Revision 2.2

78

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3.5.2. Master Data Latency

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3.5.3. Memory Write Maximum Completion Time Limit

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Revision 2.2

79

Implementation Note: Meeting Maximum Completion Time Limit byRestricting Use of the Device

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3.5.4. Arbitration Latency

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Revision 2.2

80

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3.5.4.1. Bandwidth and Latency Considerations

In PCI systems, there is a tradeoff between the desire to achieve low latency and thedesire to achieve high bandwidth (throughput). High throughput is achieved by allowingdevices to use long burst transfers. Low latency is achieved by reducing the maximumburst transfer length. The following discussion is provided (for a 32-bit bus) to illustratethis tradeoff.

A given PCI bus master introduces latency on PCI each time it uses the PCI bus to do atransaction. This latency is a function of the behavior of both the master and the targetdevice during the transaction as well as the state of the master’s GNT# signal. The buscommand used, transaction burst length, master data latency for each data phase, and theLatency Timer are the primary parameters which control the master’s behavior. The buscommand used, target latency, and target subsequent latency are the primary parameterswhich control the target’s behavior.

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A master is required to assert its IRDY# within eight clocks for any given data phase(initial and subsequent). For the first data phase, a target is required to assert its TRDY#or STOP# within 16 clocks from the assertion of FRAME# (unless the access hits amodified cacheline in which case 32 clocks are allowed for host bus bridges). For allsubsequent data phases in a burst transfer, the target must assert its TRDY# or STOP#within eight clocks. If the effects of the Latency Timer are ignored, it is astraightforward exercise to develop equations for the worst case latencies that a PCI busmaster can introduce from these specification requirements.

latency_max (clocks) = 32 + 8 * (n-1) if a modified cacheline is hit

(for a host bus bridge only)

or = 16 + 8 * (n-1) if not a modified cacheline

where n is the total number of data transfers in the transaction

However, it is more useful to consider transactions that exhibit typical behavior. PCI isdesigned so that data transfers between a bus master and a target occur as register toregister transfers. Therefore, bus masters typically do not insert wait states since theyonly request transactions when they are prepared to transfer data. Targets typically havean initial access latency less than the 16 (32 for modified cacheline hit for host busbridge) clock maximum allowed. Once targets begin transferring data (complete theirfirst data phase), they are typically able to sustain burst transfers at full rate (one clockper data phase) until the transaction is either completed by the master or the target’sbuffers are filled or are temporarily empty. The target can use the target Disconnectprotocol to terminate the burst transaction early when its buffers fill or temporarilyempty during the transaction. Using these more realistic considerations, the worst caselatency equations can be modified to give a typical latency (assuming that the target’sinitial data phase latency is eight clocks) again ignoring the effects of the Latency Timer.

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DataPhases

BytesTransferred

TotalClocks

Latency Timer(clocks)

Bandwidth(MB/s)

Latency(ms)

8 32 16 14 60 .48

16 64 24 22 80 .72

32 128 40 38 96 1.20

64 256 72 70 107 2.16

Data Phases Number of data phases completed during transaction

Bytes Transferred Total number of bytes transferred during transaction (assuming

32-bit transfers)

Total Clocks Total number of clocks used to complete the transfer

total_clocks = 8 + (n-1) + 1 (Idle time on bus)

Latency Timer Latency Timer value in clocks such that the Latency Timer

expires in next to last data phase

latency_timer = total_clocks - 2

Bandwidth Calculated bandwidth in MB/s

bandwidth = bytes_transferred / (total clocks * 30 ns)

Latency Latency in microseconds introduced by transaction

latency = total clocks * 30 ns

Table 3-4 clearly shows that as the burst length increases, the amount of data transferredincreases. Note: The amount of data doubles between each row in the table, while thelatency increases by less than double. The amount of data transferred between the firstrow and the last row increases by a factor of 8, while the latency increases by a factor of4.5. The longer the transaction (more data phases), the more efficiently the bus is beingused. However, this increase in efficiency comes at the expense of larger buffers.

3.5.4.2. Determining Arbitration Latency

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Table 3-5 lists the requirements of each device in the target system and how manytransactions each device must complete to sustain its bandwidth requirements within10 µs time slices.

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The last column indicates how many different transactions that are required to movethe data. This assumes that the entire transfer cannot be completed as a singletransaction.

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Device Bandwidth(MB/s)

Bytes/10 ms Time Used(ms)

Number ofTransactions

per Slice

Notes

Graphics 50 500 6.15 10 1

LAN 4 40 0.54 1 2

Disk 5 50 0.63 1 3

ISA bridge 4 40 0.78 2 4

PCI-to PCIbridge

9 90 1.17 2 5

Total 72 720 9.27 16

Notes:

1. Graphics is a combination of host bus bridge and frame grabber writing data to the frame buffer.The host moves 300 bytes using five transactions with 15 data phases each, assuming eightclocks of target initial latency. The frame grabber moves 200 bytes using five transactions with10 data phases each, assuming eight clocks of target initial latency.

2. The LAN uses a single transaction with 10 data phases with eight clocks of target initial latency.

3. The disk uses a single transaction with 13 data phases with eight clocks of target initial latency.

4. The ISA bridge uses two transactions with five data phases each with eight clocks of target initiallatency.

5. The PCI-to-PCI bridge uses two transactions. One transaction is similar to the LAN and thesecond is similar to the disk requirements.

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Device Bandwidth(MB/s)

Bytes/10 ms Time Used(ms)

Number ofTransactions

per Slice

Notes

Hostwriting tothe framebuffer

40 400 4.2 5 1

Framegrabber

20 200 3.7 5 2

Notes

1. The host uses five transactions with 20 data phases each, assuming eight clocks of target initiallatency.

2. The frame grabber uses five transactions with 10 data phases each, assuming eight clocks oftarget initial latency.

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3.5.4.3. Determining Buffer Requirements

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Revision 2.2

88

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3.6. Other Bus Operations

3.6.1. Device Selection

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Revision 2.2

89

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Revision 2.2

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Revision 2.2

91

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AD[15::00]

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Encoded message

Message dependent (optional) data field

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3.6.3. Address/Data Stepping

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Revision 2.2

92

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Revision 2.2

95

3.7.2. Parity Checking

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Revision 2.2

96

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97

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Revision 2.2

98

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3.7.5. Delayed Transactions and Data Parity Errors

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22 If the actual target resides on a PCI bus segment generated by a PCI-to-PCI bridge, the target completionphase occurs across a PCI bus segment. In this case, the PCI-to-PCI Bridge Architecture Specificationdetails additional requirements for error handling during the target completion phase of a read DelayedTransaction.

23 Memory Read, Memory Read Line, Memory Read Multiple, Configuration Read, I/O Read, or InterruptAcknowledge.

24 Configuration Write or I/O Write, but never Memory Write and Invalidate or Memory Write.

Revision 2.2

99

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3.7.6. Error Recovery

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25 This includes two commands: Memory Write and Invalidate and Memory Write.

Revision 2.2

100

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Implementation Note: Recovery from Data Parity Errors

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Revision 2.2

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Revision 2.2

102

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Revision 2.2

103

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The deadlock occurs when the following steps are met:

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Logic internal to a device must never use the signal received from the bus while thatdevice is driving the bus. If internal logic requires the state of a bus signal while thedevice is driving the bus, that logic must use the internal signal (the one going to theoutput buffer of the device) rather than the signal received from the device inputbuffer. For example, if logic internal to a device continuously monitors the state ofFRAME# on the bus, that logic must use the signal from the device input bufferwhen the device is not the current bus master, and it must use the internallygenerated FRAME# when the device is the current bus master.

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Chapter 4Electrical Specification

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4.1.1. 5V to 3.3V Transition Road Map

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"5 volt" Connector "3.3 volt" Connector

Dual Voltage Signaling BoardI/O buffers powered on

connector dependent rail

"5 volt" BoardI/O buffers powered on

5 volt rail

"3.3 volt" BoardI/O buffers powered on

3.3 volt rail

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27 While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden andexpense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI componentof this type is used on the Universal board, its I/O buffers may optionally be connected to the 3.3V railrather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O"designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V railwith a simple diode must never be used in the 5V signaling environment.") Since the effective operation ofthese high clamp diodes may be critical to both signal quality and device reliability, the designer mustprovide enough extra "I/O" designated power pins on a component to handle the current spikes associatedwith the 5V maximum AC waveforms (Section 4.2.1.3.).

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4.1.2. Dynamic vs. Static Drive Specification

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28 It may be desirable to perform some production tests at bare silicon pads. Such tests may have differentparameters than those specified here and must be correlated back to this specification.

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117

4.2.1. 5V Signaling Environment

4.2.1.1. DC Specifications

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Symbol Parameter Condition Min Max Units Notes

Vcc Supply Voltage 4.75 5.25 V

Vih Input High Voltage 2.0 Vcc+0.5 V

Vil Input Low Voltage -0.5 0.8 V

Iih Input High LeakageCurrent

Vin = 2.7 70 µA 1

Iil Input Low LeakageCurrent

Vin = 0.5 -70 µA 1

Voh Output High Voltage Iout = -2 mA 2.4 V

Vol Output Low Voltage Iout = 3 mA, 6 mA 0.55 V 2

Cin Input Pin Capacitance 10 pF 3

Cclk CLK Pin Capacitance 5 12 pF

CIDSEL IDSEL Pin Capacitance 8 pF 4

Lpin Pin Inductance 20 nH 5

IOff PME# input leakage Vo ≤ 5.25 VVcc off or floating

– 1 µA 6

NOTES:

1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have6 mA; the latter include, FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, INTA#,INTB#, INTC#, INTD#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted tomotherboard-only devices up to 16 pF, in order to accommodate PGA packaging. This means, in general,that components for expansion boards need to use alternatives to ceramic PGA packaging (i.e., PQFP,SGA, etc.).

4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].

5. This is a recommendation, not an absolute requirement. The actual value should be provided with thecomponent data sheet.

6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power isremoved from Vcc of the component. This assumes that no event has occurred to cause the device toattempt to assert PME#.

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4.2.1.2. AC Specifications

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Symbol Parameter Condition Min Max Units Notes

Ioh(AC) Switching0<Vout<1.4 -44 mA 1

Current High 1.4<Vout<2.4 -44+(Vout-1.4)/0.024 mA 1, 2

3.1<Vout<Vcc Eqt’n A 1, 3

(Test Point) Vout = 3.1 -142 mA 3

Iol(AC) SwitchingVout > 2.2 95 mA 1

Current Low 2.2>Vout>0.55 Vout/0.023 mA 1

0.71>Vout>0 Eqt’n B 1, 3

(Test Point) Vout = 0.71 206 mA 3

Icl Low ClampCurrent

-5 < Vin ≤ -1 -25+(Vin+1)/0.015 mA

slewr Output Rise SlewRate

0.4V to 2.4V load 1 5 V / ns 4

slewf Output Fall SlewRate

2.4V to 0.4V load 1 5 V / ns 4

NOTES:

1. Refer to the V/I curves in Figure 4-2. Switching current characteristics for REQ# and GNT# are permittedto be one half of that specified here; i.e., half size output drivers may be used on these signals. Thisspecification does not apply to CLK and RST# which are system outputs. "Switching Current High"specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drainoutputs.

2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DCdrive point rather than toward the voltage rail (as is done in the pull-down curve). This difference isintended to allow for an optional N-channel pull-up.

3. Maximum current requirements must be met as drivers pull beyond the first step voltage. Equationsdefining these maximums (A and B) are provided with the respective diagrams in Figure 4-3. Theequation-defined maximums should be met by design. In order to facilitate component testing, amaximum current test point is defined for each side of the output driver.

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119

4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than theinstantaneous rate at any point within the transition range. The specified load (diagram below) is optional;i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCILocal Bus Specification. However, adherence to both maximum and minimum parameters is required (themaximum is not simply a guideline). Since adherence to the maximum slew rate was not required prior torevision 2.1 of the specification, there may be components in the market for some time that have fasteredge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than thisspecification could occur and should ensure that signal integrity modeling accounts for this. Rise slewrate does not apply to open drain outputs.

1K Ω10 pF

outputbuffer

pin 1/2 in. max.

Vcc

1K Ω

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Current (mA)-44 -176

Vcc

Vol

tage

2.4

1.4

-2 Current (mA)95 380

Vcc

Volta

ge

2.2

0.55

3, 6

DC drivepoint

AC drivepoint

Pull Up Pull Down

DCdrive point

AC drivepoint

testpoint

testpoint

Equation A: Equation B:

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4.2.1.3. Maximum AC Ratings and Device Protection

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121

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4 nSec(max)

11 v, p-to-p(minimum)

11 nSec(min)

62.5 nSec(16 MHz)

Overvoltage WaveformVoltage Source Impedance

R = 55 Ω

10.75 v, p-to-p(minimum)

Undervoltage WaveformVoltage Source Impedance

R = 25 Ω

+ 5.25 v

- 5.5 v

+ 11 v

0 v

VEvaluation

Setup

RInput

Buffer

5v. supply

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29 Waveforms based on worst case (strongest) driver, maximum and minimum system configurations, withno internal clamp diodes.

30 It is possible to use alternative clamps, such as a diode stack to the 3.3V rail or a circuit to ground, if itcan be insured that the I/O pin will never be clamped below the 5V level.

Revision 2.2

122

4.2.2. 3.3V Signaling Environment

4.2.2.1. DC Specifications

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Symbol Parameter Condition Min Max Units Notes

Vcc Supply Voltage 3.0 3.6 V

Vih Input High Voltage 0.5Vcc Vcc + 0.5 V

Vil Input Low Voltage -0.5 0.3Vcc V

Vipu Input Pull-up Voltage 0.7Vcc V 1

Iil Input Leakage Current 0 < Vin < Vcc +10 µA 2

Voh Output High Voltage Iout = -500 µA 0.9Vcc V

Vol Output Low Voltage Iout = 1500 µA 0.1Vcc V

Cin Input Pin Capacitance 10 pF 3

Cclk CLK Pin Capacitance 5 12 pF

CIDSEL IDSEL Pin Capacitance 8 pF 4

Lpin Pin Inductance 20 nH 5

IOff PME# input leakage Vo ≤ 3.6 VVcc off orfloating

– 1 µA 6

NOTES:

1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistorsare calculated to pull a floated network. Applications sensitive to static power utilization must assure thatthe input buffer is conducting minimum current at this input voltage.

2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted tomotherboard-only devices up to 16 pF in order to accommodate PGA packaging. This would mean ingeneral that components for expansion boards need to use alternatives to ceramic PGA packaging; i.e.,PQFP, SGA, etc.

4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].

5. This is a recommendation, not an absolute requirement. The actual value should be provided with thecomponent data sheet.

6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power isremoved from Vccof the component. This assumes that no event has occurred to cause the device toattempt to assert PME#.

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Revision 2.2

123

4.2.2.2. AC Specifications

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Symbol Parameter Condition Min Max Units Notes

Ioh(AC) Switching0<Vout<0.3Vcc -12Vcc mA 1

Current High 0.3Vcc<Vout<0.9Vcc -17.1(Vcc-Vout) mA 1

0.7Vcc<Vout<Vcc Eqt’n C 1, 2

(Test Point) Vout = 0.7Vcc -32Vcc mA 2

Iol(AC) SwitchingVcc>Vout>0.6Vcc 16Vcc mA 1

Current Low 0.6Vcc>Vout>0.1Vcc 26.7Vout mA 1

0.18Vcc>Vout>0 Eqt’n D 1, 2

(Test Point) Vout = 0.18Vcc 38Vcc mA 2

Icl Low ClampCurrent

-3<Vin ≤ -1 -25+(Vin+1)/0.015 mA

Ich High ClampCurrent

Vcc+4>Vin ≥ Vcc+1 25+(Vin-Vcc-1)/0.015 mA

slewrOutput Rise SlewRate

0.2Vcc - 0.6Vcc load 1 4 V/ns 3

slewfOutput Fall SlewRate

0.6Vcc - 0.2Vccl load 1 4 V/ns 3

NOTES:

1. Refer to the V/I curves in Figure 4-4. Switching current characteristics for REQ# and GNT# are permittedto be one half of that specified here; i.e., half size output drivers may be used on these signals. Thisspecification does not apply to CLK and RST# which are system outputs. "Switching Current High"specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drainoutputs.

2. Maximum current requirements must be met as drivers pull beyond the first step voltage. Equationsdefining these maximums (C and D) are provided with the respective diagrams in Figure 4-5. Theequation-defined maximums should be met by design. In order to facilitate component testing, amaximum current test point is defined for each side of the output driver.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than theinstantaneous rate at any point within the transition range. The specified load (diagram below) is optional;i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCILocal Bus Specification. However, adherence to both maximum and minimum parameters is required (themaximum is not simply a guideline). Rise slew rate does not apply to open drain outputs.

1K Ω10 pF

outputbuffer

pin 1/2 in. max.

Vcc

1K Ω

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DCdrive point

Current (mA)-12

Vcc

Vol

tage

0.9Vcc

-0.5 16

Vcc

1.5

0.1Vcc

0.6Vcc

64

0.3Vcc

Pull Up

-48 Current (mA)

Vol

tage

DC drivepoint

AC drivepoint

Pull Down

AC drivepoint

testpoint

testpoint

0.5 Vcc

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4.2.2.3. Maximum AC Ratings and Device Protection

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4 nSec(max)

7.1 v, p-to-p(minimum)

11 nSec(min)

62.5 nSec(16 MHz)

Overvoltage WaveformVoltage Source Impedance

R = 29 Ω

7.1 v, p-to-p(minimum)

Undervoltage WaveformVoltage Source Impedance

R = 28 Ω

+ 3.6 v

- 3.5 v

+ 7.1 v

0 v

VEvaluation

Setup

RInput

Buffer

3.3v. supply

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4.2.3. Timing Specification

4.2.3.1. Clock Specification

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0.8 v

1.5 v

2.4 v

0.4 v

2 v, p-to-p(minimum)

T_high

T_low

0.3 Vcc

T_cyc

0.5 Vcc

5 volt Clock

3.3 volt Clock

0.4 Vcc

0.6 Vcc

0.2 Vcc

0.4 Vcc, p-to-p(minimum)

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7DEOH&ORFNDQG5HVHW6SHFLILFDWLRQV

Symbol Parameter Min Max Units Notes

Tcyc CLK Cycle Time 30 ∞ ns 1

Thigh CLK High Time 11 ns

Tlow CLK Low Time 11 ns

- CLK Slew Rate 1 4 V/ns 2

- RST# Slew Rate 50 - mV/ns 3

NOTES:

1. In general, all PCI components must work with any clock frequency betweennominal DC and 33 MHz. Device operational parameters at frequencies under16 MHz may be guaranteed by design rather than by testing. The clockfrequency may be changed at any time during the operation of the system solong as the clock edges remain "clean" (monotonic) and the minimum cycleand high and low times are not violated. For example, the use of spreadspectrum techniques to reduce EMI emissions is included in this requirement.Refer to Section 7.6.41. for the spread spectrum requirements for 66 MHz.The clock may only be stopped in a low state. A variance on this specificationis allowed for components designed for use on the system motherboard only.These components may operate at any single fixed frequency up to 33 MHzand may enforce a policy of no frequency changes.

2. Rise and fall times are specified in terms of the edge rate measured in V/ns.This slew rate must be met across the minimum peak-to-peak portion of theclock waveform as shown in Figure 4-6.

3. The minimum RST# slew rate applies only to the rising (deassertion) edge ofthe reset signal and ensures that system noise cannot render an otherwisemonotonic signal to appear to bounce in the switching range. RST#waveforms and timing are discussed in Section 4.3.2.

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4.2.3.2. Timing Parameters

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Symbol Parameter Min Max Units Notes

Tval CLK to Signal Valid Delay - bused signals 2 11 ns 1, 2, 3

Tval(ptp) CLK to Signal Valid Delay - point to point 2 12 ns 1, 2, 3

Ton Float to Active Delay 2 ns 1, 7

Toff Active to Float Delay 28 ns 1, 7

Tsu Input Setup Time to CLK - bused signals 7 ns 3, 4, 8

Tsu(ptp) Input Setup Time to CLK - point to point 10, 12 ns 3, 4

Th Input Hold Time from CLK 0 ns 4

Trst Reset active time after power stable 1 ms 5

Trst-clk Reset active time after CLK STABLE 100 µs 5

Trst-off Reset Active to Output Float delay 40 ns 5, 6,7

Trrsu REQ64# to RST# Setup time 10*Tcyc ns

Trrh RST# to REQ64# Hold time 0 50 ns

Trhfa RST# High to First configuration Access 225 clocks

Trhff RST# High to First FRAME# assertion 5 clocks

NOTES:

1. See the timing measurement conditions in Figure 4-7.

2. For parts compliant to the 5V signaling environment:Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pFequivalent load. Actual test capacitance may vary, but results must be correlated to thesespecifications. Note that faster buffers may exhibit some ring back when attached to a 50 pF lumpload which should be of no consequence as long as the output buffers are in full compliance withslew rate and V/I curve specifications.

For parts compliant to the 3.3V signaling environment:Minimum times are evaluated with same load used for slew rate measurement (as shown inTable 4-4, note 3); maximum times are evaluated with the following load circuits, for high-going and low-going edges respectively.

25 Ω10 pF

Vcc

1/2 in. max.

25 Ω 10 pF

Tval(max) Rising Edge

1/2 in. max.

outputbuffer

pin

Tval(max) Falling Edge

3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup timesthan do bused signals. GNT# has a setup of 10; REQ# has a setup of 12. All other signals are bused.

4. See the timing measurement conditions in Figure 4-8.

5. CLK is stable when it meets the requirements in Section 4.2.3.1. RST# is asserted and deassertedasynchronously with respect to CLK. Refer to Section 4.3.2. for more information.

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6. All output drivers must be asynchronously floated when RST# is active. Refer to Section 3.10.2. forspecial requirements for AD[63::32], C/BE[7::4]#, and PAR64 when they are not connected (as in a 64-bitexpansion board installed in a 32-bit connector).

7. For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the totalcurrent delivered through the component pin is less than or equal to the leakage current specification.

8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signalsat the same time. Refer to Section 3.10., item 9, for additional details.

4.2.3.3. Measurement and Test Conditions

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CLK

OUTPUTDELAY

T_val

T_on

V_test

T_off

Tri-StateOUTPUT

V_test (5v. signaling)V_trise, V_tfall (3.3v. signaling)

V_th

V_tl

output current leakage current

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INPUTinputsvalid

V_th

V_tl

T_hT_su

CLK

V_test

V_test

V_test V_max

V_th

V_tl

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Symbol 5V Signaling 3.3V Signaling Units

Vth 2.4 0.6Vcc V (Note)

Vtl 0.4 0.2Vcc V (Note)

Vtest 1.5 0.4Vcc V

Vtrise n/a 0.285Vcc V

Vtfall n/a 0.615Vcc V

Vmax 2.0 0.4Vcc V (Note)

Input SignalEdge Rate

1 V / ns

NOTE:

The input test for the 5V environment is done with 400 mV of overdrive(over Vih and Vil); the test for the 3.3V environment is done with0.1Vcc of overdrive. Timing parameters must be met with no moreoverdrive than this. Vmax specifies the maximum peak-to-peakwaveform allowed for measuring input timing. Production testing mayuse different voltage values, but must correlate results back to theseparameters.

4.2.4. Indeterminate Inputs and Metastability

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Revision 2.2

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4.2.5. Vendor Provided Specification

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4.2.6. Pinout Recommendation

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PCI Component

All PCI Shared SignalsBelow this Line

JTAG

RST#CLKGNTREQ

AD[31]..

AD[24]C/BE3#IDSEL

C/B

E2#

FRA

ME

#IR

DY

#TR

DY

#D

EV

SE

L#S

TOP

#LO

CK

#P

ER

R#

SE

RR

#P

AR

C/B

E1#

AD

[23]

.A

D[1

6]

AD

[15]

. .A

D[8

]

AD[0].

AD[7]C/BE0#

AD[32]..

AD[63]C/BE4#C/BE5#C/BE6#C/BE7#

REQ64#ACK64#

PCI Card Edge

PAR64

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4.3. System (Motherboard) Specification

4.3.1. Clock Skew

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31 Non-resistive connections of IDSEL to one of the AD[xx] lines create a technical violation of the singleload per expansion board rule. PCI protocol provides for pre-driving of address lines in configurationcycles, and it is recommended that this be done in order to allow a resistive coupling of IDSEL. In absenceof this, signal performance must be derated for the extra IDSEL load.

32 The system designer must address an additional source of skew. This clock skew occurs between twocomponents that have clock input trip points at opposite ends of the Vil - Vih range. In certaincircumstances, this can add to the clock skew measurement as described here. In all cases, total clock skewmust be limited to the specified number.

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7DEOH&ORFN6NHZ3DUDPHWHUV

Symbol 5V Signaling 3.3V Signaling Units

Vtest 1.5 0.4 Vcc V

Tskew 2 (max) 2 (max) ns

CLK(@Device #1)

CLK(@Device #2)

V_testV_ih

T_skew

T_skew

T_skew

V_testV_il

V_il

V_ih

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4.3.2. Reset

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7KHYDOXHRI7IDLOLVWKHPLQLPXPRI

• QVPD[LPXPIURPHLWKHUSRZHUUDLOJRLQJRXWRIVSHFLILFDWLRQH[FHHGLQJVSHFLILHGWROHUDQFHVE\PRUHWKDQP9

• QVPD[LPXPIURPWKH9UDLOIDOOLQJEHORZWKH9UDLOE\PRUHWKDQP9

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7KHV\VWHPPXVWJXDUDQWHHWKDWWKHEXVUHPDLQVLQWKHLGOHVWDWHIRUDPLQLPXPWLPHGHOD\IROORZLQJWKHGHDVVHUWLRQRIRST#WRDGHYLFHEHIRUHWKHV\VWHPZLOOSHUPLWWKH

33 Component vendors should note that a fixed timing relationship between RST# and power sequencingcannot be guaranteed in all cases.

Revision 2.2

134

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• RST# LVGHDVVHUWHG

• 7KHGHYLFHLVUHDG\WRSDUWLFLSDWHLQWKHEXVVLJQDOLQJSURWRFRO

• 7KHEXVLVLQWKHLGOHVWDWH

Implementation Note: Reset

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Revision 2.2

135

Implementation Note: Trhfa'HYLFHVDUHHQFRXUDJHGWRFRPSOHWHWKHLULQLWLDOL]DWLRQDQGEHUHDG\WRDFFHSWWKHLUILUVWF\FOHJHQHUDOO\D&RQILJXUDWLRQ5HDGF\FOHDVVRRQDVSRVVLEOHDIWHUWKHGHDVVHUWLRQRIRST#6RPHV\VWHPLPSOHPHQWDWLRQVZLOODFFHVVGHYLFHVSULRUWRZDLWLQJWKHIXOOYDOXHRI7UKIDLIWKH\NQRZLQDGYDQFHWKDWDOOGHYLFHVDUHUHDG\VRRQHU)RUH[DPSOHDV\VWHPZLWKQR3&,VORWVZRXOGRQO\QHHGWRZDLWIRUWKHLQLWLDOL]DWLRQUHTXLUHPHQWVRIWKHHPEHGGHGGHYLFHV6LPLODUO\DQLQWHOOLJHQWH[SDQVLRQERDUGWKDWLQLWLDOL]HGLWVRZQHPEHGGHG3&,GHYLFHVZRXOGRQO\QHHGWRZDLWIRUWKHLQLWLDOL]DWLRQUHTXLUHPHQWVRIWKRVHGHYLFHV

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32:(5

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34 This reset timing figure optionally shows the "PWR_GOOD" signal as a pulse which is used to time theRST# pulse. In many systems, "PWR_GOOD" may be a level, in which case the RST# pulse must betimed in another way.

Revision 2.2

136

4.3.3. Pull-ups

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7KHIRUPXODVIRUPLQLPXPDQGPD[LPXPSXOOXSUHVLVWRUVDUHSURYLGHGEHORZ5PLQLVSULPDULO\GULYHQE\,ROWKH'&ORZRXWSXWFXUUHQWZKHUHDVWKHQXPEHURIORDGVRQO\KDVDVHFRQGDU\HIIHFW2QWKHRWKHUKDQG5PD[LVSULPDULO\GULYHQE\WKHQXPEHURIORDGVSUHVHQW7KHVSHFLILFDWLRQSURYLGHVIRUDPLQLPXP5YDOXHWKDWLVFDOFXODWHGEDVHGRQORDGVEHOLHYHGWREHDZRUVWFDVHDQGDW\SLFDO5YDOXHWKDWLVFDOFXODWHGDVWKHPD[LPXP5YDOXHZLWKORDGV7KHPD[LPXP5YDOXHLVSURYLGHGE\IRUPXODRQO\DQGZLOOEHWKHKLJKHVWLQDV\VWHPZLWKWKHVPDOOHVWQXPEHURIORDGV

5 9FF 9 , ,RO RO LOPLQ PD[ > @ > @= − + ⋅ , where 16 = max number of loads

5 9FF 9 QXP ORDGV ,[ LKPD[ PLQ= − ×> @ > B @ ,

where: 9 Y[ = for 5V signaling, and 9 9FF[ = for 3.3V signaling.

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7DEOH0LQLPXPDQG7\SLFDO3XOOXS5HVLVWRU9DOXHV

Signaling Rail Rmin Rtypical Rmax

5V 963 Ω 2.7 KΩ @ 10% see formula

3.3V 2.42 KΩ 8.2 KΩ @ 10% see formula

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Revision 2.2

137

4.3.4. Power

4.3.4.1. Power Requirements

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7DEOH3RZHU6XSSO\5DLO7ROHUDQFHV

Power Rail Expansion Boards (Short and Long)

5 V ±5% 5 A max. (system dependent)

3.3 V ±0.3 V 7.6 A max. (system dependent)

12 V ±5% 500 mA

-12 V ±10% 100 mA

4.3.4.2. Sequencing

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Revision 2.2

138

4.3.4.3. Decoupling

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4.3.5. System Timing Budget

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Revision 2.2

139

Implementation Note: Determining the End of Tprop7KHHQGRI7SURSLVDOZD\VGHWHUPLQHGE\WKHFDOFXODWLRQPHWKRGWKDWSURGXFHVWKHORQJHUYDOXHRI7SURS7KHVKDSHRIWKHZDYHIRUPDWWKHLQSXWEXIIHUZLOOGHWHUPLQHZKLFKPHDVXUHPHQWPHWKRGZLOOSURGXFHWKHORQJHUYDOXH

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Revision 2.2

140

DrivingBus

DrivingTest Load

2.0V

1.0V

thV

ihV

testVDrivingBus

DrivingTest Load

thV

ihV

testV

DrivingBus

DrivingTest Load

2.0V

1.0V

thV

ihV

testV

Driving Bus

Driving Test Load

tlV

ilV

testV

DrivingBus

Tprop

2.0V

1.0V

tlV

ilV

testV

DrivingTest Load

ilV

tlV

testV

InputSignalEdgeRate

Input SignalEdge Rate

Driving Test Load

Input SignalEdge Rate

Input SignalEdge Rate

Driving Bus

(a) (b)

(c) (d)

(e) (f)

2.0V

1.0V

2.0V

1.0V

2.0V

1.0V

Tprop

Tprop Tprop

Tprop

Tprop

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Revision 2.2

141

4.3.6. Physical Requirements

4.3.6.1. Routing and Layout Recommendations for Four-LayerMotherboards

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4.3.6.2. Motherboard Impedance

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4.3.7. Connector Pin Assignments

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5V System Environment 3.3V System Environment

Pin Side B Side A Side B Side A Comments

1 -12V TRST# -12V TRST# 32-bit connector start

2 TCK +12V TCK +12V3 Ground TMS Ground TMS4 TDO TDI TDO TDI5 +5V +5V +5V +5V6 +5V INTA# +5V INTA#7 INTB# INTC# INTB# INTC#8 INTD# +5V INTD# +5V9 PRSNT1# Reserved PRSNT1# Reserved10 Reserved +5V (I/O) Reserved +3.3V (I/O)

11 PRSNT2# Reserved PRSNT2# Reserved12 Ground Ground CONNECTOR KEY 3.3 volt key

13 Ground Ground CONNECTOR KEY 3.3 volt key

14 Reserved 3.3Vaux Reserved 3.3Vaux15 Ground RST# Ground RST#16 CLK +5V (I/O) CLK +3.3V (I/O)

17 Ground GNT# Ground GNT#18 REQ# Ground REQ# Ground19 +5V (I/O) PME# +3.3V (I/O) PME#20 AD[31] AD[30] AD[31] AD[30]21 AD[29] +3.3V AD[29] +3.3V22 Ground AD[28] Ground AD[28]23 AD[27] AD[26] AD[27] AD[26]24 AD[25] Ground AD[25] Ground25 +3.3V AD[24] +3.3V AD[24]26 C/BE[3]# IDSEL C/BE[3]# IDSEL27 AD[23] +3.3V AD[23] +3.3V28 Ground AD[22] Ground AD[22]29 AD[21] AD[20] AD[21] AD[20]30 AD[19] Ground AD[19] Ground31 +3.3V AD[18] +3.3V AD[18]32 AD[17] AD[16] AD[17] AD[16]33 C/BE[2]# +3.3V C/BE[2]# +3.3V34 Ground FRAME# Ground FRAME#35 IRDY# Ground IRDY# Ground36 +3.3V TRDY# +3.3V TRDY#37 DEVSEL# Ground DEVSEL# Ground38 Ground STOP# Ground STOP#39 LOCK# +3.3V LOCK# +3.3V40 PERR# Reserved* PERR# Reserved*41 +3.3V Reserved* +3.3V Reserved*42 SERR# Ground SERR# Ground

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7DEOH3&,&RQQHFWRU3LQRXWFRQWLQXHG

5V System Environment 3.3V System Environment

Pin Side B Side A Side B Side A Comments

43 +3.3V PAR +3.3V PAR44 C/BE[1]# AD[15] C/BE[1]# AD[15]45 AD[14] +3.3V AD[14] +3.3V46 Ground AD[13] Ground AD[13]47 AD[12] AD[11] AD[12] AD[11]48 AD[10] Ground AD[10] Ground49 Ground AD[09] M66EN AD[09] 66 MHz / gnd

50 CONNECTOR KEY Ground Ground 5 volt key

51 CONNECTOR KEY Ground Ground 5 volt key

52 AD[08] C/BE[0]# AD[08] C/BE[0]#53 AD[07] +3.3V AD[07] +3.3V54 +3.3V AD[06] +3.3V AD[06]55 AD[05] AD[04] AD[05] AD[04]56 AD[03] Ground AD[03] Ground57 Ground AD[02] Ground AD[02]58 AD[01] AD[00] AD[01] AD[00]59 +5V (I/O) +5V (I/O) +3.3V (I/O) +3.3V (I/O)

60 ACK64# REQ64# ACK64# REQ64#61 +5V +5V +5V +5V62 +5V +5V +5V +5V 32-bit connector end

CONNECTOR KEY CONNECTOR KEY 64-bit spacer

CONNECTOR KEY CONNECTOR KEY 64-bit spacer

63 Reserved Ground Reserved Ground 64-bit connector start

64 Ground C/BE[7]# Ground C/BE[7]#65 C/BE[6]# C/BE[5]# C/BE[6]# C/BE[5]#66 C/BE[4]# +5V (I/O) C/BE[4]# +3.3V (I/O)

67 Ground PAR64 Ground PAR6468 AD[63] AD[62] AD[63] AD[62]69 AD[61] Ground AD[61] Ground70 +5V (I/O) AD[60] +3.3V (I/O) AD[60]71 AD[59] AD[58] AD[59] AD[58]72 AD[57] Ground AD[57] Ground73 Ground AD[56] Ground AD[56]74 AD[55] AD[54] AD[55] AD[54]75 AD[53] +5V (I/O) AD[53] +3.3V (I/O)

76 Ground AD[52] Ground AD[52]77 AD[51] AD[50] AD[51] AD[50]78 AD[49] Ground AD[49] Ground79 +5V (I/O) AD[48] +3.3V (I/O) AD[48]80 AD[47] AD[46] AD[47] AD[46]81 AD[45] Ground AD[45] Ground82 Ground AD[44] Ground AD[44]

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5V System Environment 3.3V System Environment

Pin Side B Side A Side B Side A Comments

83 AD[43] AD[42] AD[43] AD[42]84 AD[41] +5V (I/O) AD[41] +3.3V (I/O)

85 Ground AD[40] Ground AD[40]86 AD[39] AD[38] AD[39] AD[38]87 AD[37] Ground AD[37] Ground88 +5V (I/O) AD[36] +3.3V (I/O) AD[36]89 AD[35] AD[34] AD[35] AD[34]90 AD[33] Ground AD[33] Ground91 Ground AD[32] Ground AD[32]92 Reserved Reserved Reserved Reserved93 Reserved Ground Reserved Ground94 Ground Reserved Ground Reserved 64-bit connector end

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4.4. Expansion Board Specification

4.4.1. Board Pin Assignment

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PRSNT1# PRSNT2# Expansion Configuration

Open Open No expansion board present

Ground Open Expansion board present, 25 W maximum

Open Ground Expansion board present, 15 W maximum

Ground Ground Expansion board present, 7.5 W maximum

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5V Board Universal Board 3.3V Board

Pin Side B Side A Side B Side A Side B Side A Comments

1 -12V TRST# -12V TRST# -12V TRST# 32-bit start

2 TCK +12V TCK +12V TCK +12V3 Ground TMS Ground TMS Ground TMS4 TDO TDI TDO TDI TDO TDI5 +5V +5V +5V +5V +5V +5V6 +5V INTA# +5V INTA# +5V INTA#7 INTB# INTC# INTB# INTC# INTB# INTC#8 INTD# +5V INTD# +5V INTD# +5V9 PRSNT1# Reserved PRSNT1# Reserved PRSNT1# Reserved10 Reserved +5V Reserved +VI/O Reserved +3.3V11 PRSNT2# Reserved PRSNT2# Reserved PRSNT2# Reserved12 Ground Ground KEYWAY KEYWAY 3.3V key

13 Ground Ground KEYWAY KEYWAY 3.3V key

14 Reserved 3.3Vaux Reserved 3.3Vaux Reserved 3.3Vaux15 Ground RST# Ground RST# Ground RST#16 CLK +5V CLK +VI/O CLK +3.3V17 Ground GNT# Ground GNT# Ground GNT#18 REQ# Ground REQ# Ground REQ# Ground19 +5V PME# +VI/O PME# +3.3V PME#20 AD[31] AD[30] AD[31] AD[30] AD[31] AD[30]21 AD[29] +3.3V AD[29] +3.3V AD[29] +3.3V22 Ground AD[28] Ground AD[28] Ground AD[28]23 AD[27] AD[26] AD[27] AD[26] AD[27] AD[26]24 AD[25] Ground AD[25] Ground AD[25] Ground25 +3.3V AD[24] +3.3V AD[24] +3.3V AD[24]26 C/BE[3]# IDSEL C/BE[3]# IDSEL C/BE[3]# IDSEL27 AD[23] +3.3V AD[23] +3.3V AD[23] +3.3V28 Ground AD[22] Ground AD[22] Ground AD[22]29 AD[21] AD[20] AD[21] AD[20] AD[21] AD[20]30 AD[19] Ground AD[19] Ground AD[19] Ground31 +3.3V AD[18] +3.3V AD[18] +3.3V AD[18]32 AD[17] AD[16] AD[17] AD[16] AD[17] AD[16]33 C/BE[2]# +3.3V C/BE[2]# +3.3V C/BE[2]# +3.3V34 Ground FRAME# Ground FRAME# Ground FRAME#35 IRDY# Ground IRDY# Ground IRDY# Ground36 +3.3V TRDY# +3.3V TRDY# +3.3V TRDY#37 DEVSEL# Ground DEVSEL# Ground DEVSEL# Ground38 Ground STOP# Ground STOP# Ground STOP#39 LOCK# +3.3V LOCK# +3.3V LOCK# +3.3V40 PERR# Reserved PERR# Reserved PERR# Reserved41 +3.3V Reserved +3.3V Reserved +3.3V Reserved42 SERR# Ground SERR# Ground SERR# Ground

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7DEOH3&,([SDQVLRQ%RDUG3LQRXWFRQWLQXHG

5V Board Universal Board 3.3V Board

Pin Side B Side A Side B Side A Side B Side A Comments

43 +3.3V PAR +3.3V PAR +3.3V PAR44 C/BE[1]# AD[15] C/BE[1]# AD[15] C/BE[1]# AD[15]45 AD[14] +3.3V AD[14] +3.3V AD[14] +3.3V46 Ground AD[13] Ground AD[13] Ground AD[13]47 AD[12] AD[11] AD[12] AD[11] AD[12] AD[11]48 AD[10] Ground AD[10] Ground AD[10] Ground49 Ground AD[09] M66EN AD[09] M66EN AD[09] 66 MHz /gnd

50 KEYWAY KEYWAY Ground Ground 5V key

51 KEYWAY KEYWAY Ground Ground 5V key

52 AD[08] C/BE[0]# AD[08] C/BE[0]# AD[08] C/BE[0]#53 AD[07] +3.3V AD[07] +3.3V AD[07] +3.3V54 +3.3V AD[06] +3.3V AD[06] +3.3V AD[06]55 AD[05] AD[04] AD[05] AD[04] AD[05] AD[04]56 AD[03] Ground AD[03] Ground AD[03] Ground57 Ground AD[02] Ground AD[02] Ground AD[02]58 AD[01] AD[00] AD[01] AD[00] AD[01] AD[00]59 +5V +5V +VI/O +VI/O +3.3V +3.3V60 ACK64# REQ64# ACK64# REQ64# ACK64# REQ64#61 +5V +5V +5V +5V +5V +5V62 +5V +5V +5V +5V +5V +5V 32-bit end

KEYWAY KEYWAY KEYWAY 64-bit spacer

KEYWAY KEYWAY KEYWAY 64-bit spacer

63 Reserved Ground Reserved Ground Reserved Ground 64-bit start

64 Ground C/BE[7]# Ground C/BE[7]# Ground C/BE[7]#65 C/BE[6]# C/BE[5]# C/BE[6]# C/BE[5]# C/BE[6]# C/BE[5]#66 C/BE[4]# +5V C/BE[4]# +VI/O C/BE[4]# +3.3V67 Ground PAR64 Ground PAR64 Ground PAR6468 AD[63] AD[62] AD[63] AD[62] AD[63] AD[62]69 AD[61] Ground AD[61] Ground AD[61] Ground70 +5V AD[60] +VI/O AD[60] +3.3V AD[60]71 AD[59] AD[58] AD[59] AD[58] AD[59] AD[58]72 AD[57] Ground AD[57] Ground AD[57] Ground73 Ground AD[56] Ground AD[56] Ground AD[56]74 AD[55] AD[54] AD[55] AD[54] AD[55] AD[54]75 AD[53] +5V AD[53] +VI/O AD[53] +3.3V76 Ground AD[52] Ground AD[52] Ground AD[52]77 AD[51] AD[50] AD[51] AD[50] AD[51] AD[50]78 AD[49] Ground AD[49] Ground AD[49] Ground79 +5V AD[48] +VI/O AD[48] +3.3V AD[48]80 AD[47] AD[46] AD[47] AD[46] AD[47] AD[46]81 AD[45] Ground AD[45] Ground AD[45] Ground82 Ground AD[44] Ground AD[44] Ground AD[44]

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5V Board Universal Board 3.3V Board

Pin Side B Side A Side B Side A Side B Side A Comments

83 AD[43] AD[42] AD[43] AD[42] AD[43] AD[42]84 AD[41] +5V AD[41] +VI/O AD[41] +3.3V85 Ground AD[40] Ground AD[40] Ground AD[40]86 AD[39] AD[38] AD[39] AD[38] AD[39] AD[38]87 AD[37] Ground AD[37] Ground AD[37] Ground88 +5V AD[36] +VI/O AD[36] +3.3V AD[36]89 AD[35] AD[34] AD[35] AD[34] AD[35] AD[34]90 AD[33] Ground AD[33] Ground AD[33] Ground91 Ground AD[32] Ground AD[32] Ground AD[32]92 Reserved Reserved Reserved Reserved Reserved Reserved93 Reserved Ground Reserved Ground Reserved Ground94 Ground Reserved Ground Reserved Ground Reserved 64-bit end

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Pin Type 5V Board Universal Board 3.3V Board

Ground 22 18 (Note) 22 (Note)+5 V 13 8 8

+3.3 V 12 12 17I/O pwr 0 5 0

Reserv’d 4 4 4

NOTE:

If the M66EN pin is implemented, the number of ground pins for a Universalboard is 17 and the number of ground pins for a 3.3V board is 21.

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Pin Type 5V Board Universal Board 3.3V Board

Ground 16 16 16+5 V 6 0 0

+3.3 V 0 0 6I/O pwr 0 6 0

Reserv’d 5 5 5

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4.4.2. Power Requirements

4.4.2.1. Decoupling

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4.4.2.2. Power Consumption

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35 While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden andexpense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI componentof this type is used on the Universal Board, its I/O buffers may optionally be connected to the 3.3V railrather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O"designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V railwith a simple diode must never be used in the 5V signaling environment.") Since the effective operation ofthese high clamp diodes may be critical to both signal quality and device reliability, the designer mustprovide enough extra "I/O" designated power pins on a component to handle the current spikes associatedwith the 5V maximum AC waveforms (Section 4.2.1.3.).

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4.4.3. Physical Requirements

4.4.3.1. Trace Length Limits

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4.4.3.2. Routing Recommendations for Four-Layer ExpansionBoards

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4.4.3.4. Signal Loading

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Chapter 5Mechanical Specification

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36 It is highly recommended that adapter card designers implement I/O brackets which mount on thebackside of PCI cards as soon as possible to reduce their exposure to causing EMC leakage in systems.

37 It is highly recommended that system designers initiate requirements which include the use of this newdesign by their adapter card suppliers.

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5.2.1. Connector Physical Description

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5.2.1.1. Connector Physical Requirements

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Part Materials

Connector Housing High-temperature thermoplastic, UL flammability rating94V-0, color: white.

Contacts Phosphor bronze.

Contact Finish 0.000030 inch minimum gold over 0.000050 inchminimum nickel in the contact area. Alternate finish:gold flash over 0.000040 inch (1 micron) minimumpalladium or palladium-nickel over nickel in the contactarea.

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5.2.1.2. Connector Performance Specification

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Parameter Specification

Durability 100 mating cycles without physical damage orexceeding low level contact resistance requirementwhen mated with the recommended card edge.

Mating Force 6 oz. (1.7N) max. avg. per opposing contact pair usingMIL-STD-1344, Method 2013.1 and gauge perMIL-C-21097 with profile as shown in add-in boardspecification.

Contact Normal Force 75 grams minimum.

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Parameter Specification

Contact Resistance (low signal level) 30 mΩ max. initial, 10 mΩ max.increase through testing. Contact resistance, test perMIL-STD-1344, Method 3002.1.

Insulation Resistance 1000 MΩ min. per MIL STD 202, Method 302,Condition B.

Dielectric WithstandVoltage

500 VAC RMS. per MIL-STD-1344, Method D3001.1Condition 1.

Capacitance 2 pF max. @ 1 MHz.

Current Rating 1A, 30 °C rise above ambient.

Voltage Rating 125V.

Certification UL Recognition and CSA Certification required.

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Parameter Specification

Operating Temperature -40 °C to 105 °C

Thermal Shock -55 °C to 85 °C, 5 cycles per MIL-STD-1344, Method1003.1.

Flowing Mixed Gas Test Battelle, Class II. Connector mated with board andtested per Battelle method.

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5.2.2. Planar Implementation

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38 It is highly recommended that LPX system chassis designers utilize the PCI riser connector whenimplementing riser cards on LPX systems and using adapter cards slots on 0.800” spacing.

39 It is highly recommended that LPX system chassis designers utilize the taller riser style of ISA and EISAconnectors when combining PCI and ISA/EISA.

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Chapter 6Configuration Space

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40 The device dependent region contains device specific information and is not described in this document.

41 The PC Card Standard is available from PCMCIA and contact information can be found athttp://www.pc-card.com

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6.2. Configuration Space Functions3&,KDVWKHSRWHQWLDOIRUJUHDWO\LQFUHDVLQJWKHHDVHZLWKZKLFKV\VWHPVPD\EHFRQILJXUHG7RUHDOL]HWKLVSRWHQWLDODOO3&,GHYLFHVPXVWSURYLGHFHUWDLQIXQFWLRQVWKDWV\VWHPFRQILJXUDWLRQVRIWZDUHFDQXWLOL]H7KLVVHFWLRQDOVROLVWVWKHIXQFWLRQVWKDWQHHGWREHVXSSRUWHGE\3&,GHYLFHVYLDUHJLVWHUVGHILQHGLQWKHSUHGHILQHGKHDGHUSRUWLRQRIWKH&RQILJXUDWLRQ6SDFH7KHH[DFWIRUPDWRIWKHVHUHJLVWHUVLHQXPEHURIELWVLPSOHPHQWHGLVGHYLFHVSHFLILF+RZHYHUVRPHJHQHUDOUXOHVPXVWEHIROORZHG$OOUHJLVWHUVPXVWEHFDSDEOHRIEHLQJUHDGDQGWKHGDWDUHWXUQHGPXVWLQGLFDWHWKHYDOXHWKDWWKHGHYLFHLVDFWXDOO\XVLQJ

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6.2.1. Device Identification

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Vendor ID This field identifies the manufacturer of the device. Validvendor identifiers are allocated by the PCI SIG to ensureuniqueness. 0FFFFh is an invalid value for Vendor ID.

Device ID This field identifies the particular device. This identifier isallocated by the vendor.

Revision ID This register specifies a device specific revision identifier.The value is chosen by the vendor. Zero is an acceptablevalue. This field should be viewed as a vendor definedextension to the Device ID.

Header Type This byte identifies the layout of the second part of thepredefined header (beginning at byte 10h in ConfigurationSpace) and also whether or not the device contains multiplefunctions. Bit 7 in this register is used to identify a multi-function device. If the bit is 0, then the device is singlefunction. If the bit is 1, then the device has multiplefunctions. Bits 6 through 0 identify the layout of the secondpart of the predefined header. The encoding 00h specifies thelayout shown in Figure 6-1. The encoding 01h is defined forPCI-to-PCI bridges and is defined in the document PCI toPCI Bridge Architecture Specification. The encoding 02h isdefined for a CardBus bridge and is documented in the PCCard Standard. All other encodings are reserved.

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Class Code The Class Code register is read-only and is used to identifythe generic function of the device and, in some cases, aspecific register-level programming interface. The register isbroken into three byte-size fields. The upper byte (at offset0Bh) is a base class code which broadly classifies the type offunction the device performs. The middle byte (at offset 0Ah)is a sub-class code which identifies more specifically thefunction of the device. The lower byte (at offset 09h)identifies a specific register-level programming interface (ifany) so that device independent software can interact with thedevice. Encodings for base class, sub-class, and programminginterface are provided in Appendix D. All unspecifiedencodings are reserved.

6.2.2. Device Control

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Bit Location Description

0 Controls a device’s response to I/O Space accesses. A value of 0disables the device response. A value of 1 allows the device torespond to I/O Space accesses. State after RST# is 0.

1 Controls a device’s response to Memory Space accesses. A value of0 disables the device response. A value of 1 allows the device torespond to Memory Space accesses. State after RST# is 0.

2 Controls a device’s ability to act as a master on the PCI bus. A valueof 0 disables the device from generating PCI accesses. A value of 1allows the device to behave as a bus master. State after RST# is 0.

3 Controls a device’s action on Special Cycle operations. A value of 0causes the device to ignore all Special Cycle operations. A value of 1allows the device to monitor Special Cycle operations. State afterRST# is 0.

4 This is an enable bit for using the Memory Write and Invalidatecommand. When this bit is 1, masters may generate the command.When it is 0, Memory Write must be used instead. State after RST# is0. This bit must be implemented by master devices that can generatethe Memory Write and Invalidate command.

5 This bit controls how VGA compatible and graphics devices handleaccesses to VGA palette registers. When this bit is 1, palettesnooping is enabled (i.e., the device does not respond to paletteregister writes and snoops the data). When the bit is 0, the deviceshould treat palette write accesses like all other accesses. VGAcompatible devices should implement this bit. Refer to Section 3.10.for more details on VGA palette snooping.

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Bit Location Description

6 This bit controls the device’s response to parity errors. When the bit isset, the device must take its normal action when a parity error isdetected. When the bit is 0, the device sets its Detected Parity Errorstatus bit (bit 15 in the Status register) when an error is detected, butdoes not assert PERR# and continues normal operation. This bit’sstate after RST# is 0. Devices that check parity must implement thisbit. Devices are still required to generate parity even if parity checkingis disabled.

7 This bit is used to control whether or not a device does address/datastepping. Devices that never do stepping must hardwire this bit to 0.Devices that always do stepping must hardwire this bit to 1. Devicesthat can do either, must make this bit read/write and have it initialize to1 after RST#.

8 This bit is an enable bit for the SERR# driver. A value of 0 disablesthe SERR# driver. A value of 1 enables the SERR# driver. This bit’sstate after RST# is 0. All devices that have an SERR# pin mustimplement this bit. Address parity errors are reported only if this bitand bit 6 are 1.

9 This optional read/write bit controls whether or not a master can dofast back-to-back transactions to different devices. Initializationsoftware will set the bit if all targets are fast back-to-back capable. Avalue of 1 means the master is allowed to generate fast back-to-backtransactions to different agents as described in Section 3.4.2. A valueof 0 means fast back-to-back transactions are only allowed to thesame agent. This bit’s state after RST# is 0.

10-15 Reserved.

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6.2.3. Device Status

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Signaled Target AbortReceived Target AbortReceived Master AbortSignaled System ErrorDetected Parity Error

Reserved

5

66 MHz CapableCapabilities List

4

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Bit Location Description

0-3 Reserved.

4 This optional read-only bit indicates whether or not this deviceimplements the pointer for a New Capabilities linked list at offset 34h.A value of zero indicates that no New Capabilities linked list isavailable. A value of one indicates that the value read at offset 34h is apointer in Configuration Space to a linked list of new capabilities. Referto Section 6.7. for details on New Capabilities.

5 This optional read-only bit indicates whether or not this device iscapable of running at 66 MHz as defined in Chapter 7. A value of zeroindicates 33 MHz. A value of 1 indicates that the device is 66 MHzcapable.

6 This bit is reserved42.

7 This optional read-only bit indicates whether or not the target iscapable of accepting fast back-to-back transactions when thetransactions are not to the same agent. This bit can be set to 1 if thedevice can accept these transactions and must be set to 0 otherwise.Refer to Section 3.4.2. for a complete description of requirements forsetting this bit.

8 This bit is only implemented by bus masters. It is set when threeconditions are met: 1) the bus agent asserted PERR# itself (on a read)or observed PERR# asserted (on a write); 2) the agent setting the bitacted as the bus master for the operation in which the error occurred;and 3) the Parity Error Response bit (Command register) is set.

9-10 These bits encode the timing of DEVSEL#. Section 3.6.1. specifiesthree allowable timings for assertion of DEVSEL#. These areencoded as 00b for fast, 01b for medium, and 10b for slow (11b isreserved). These bits are read-only and must indicate the slowest timethat a device asserts DEVSEL# for any bus command exceptConfiguration Read and Configuration Write.

42 In Revision 2.1 of this specification, this bit was used to indicate whether or not a device supported UserDefinable Features.

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Bit Location Description

11 This bit must be set by a target device whenever it terminates atransaction with Target-Abort. Devices that will never signal Target-Abort do not need to implement this bit.

12 This bit must be set by a master device whenever its transaction isterminated with Target-Abort. All master devices must implement thisbit.

13 This bit must be set by a master device whenever its transaction(except for Special Cycle) is terminated with Master-Abort. All masterdevices must implement this bit.

14 This bit must be set whenever the device asserts SERR#. Deviceswho will never assert SERR# do not need to implement this bit.

15 This bit must be set by the device whenever it detects a parity error,even if parity error handling is disabled (as controlled by bit 6 in theCommand register).

6.2.4. Miscellaneous Registers

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7 Return 1 if device supports BIST. Return 0 if the device is not BISTcapable.

6 Write a 1 to invoke BIST. Device resets the bit when BIST is complete.Software should fail the device if BIST is not complete after 2 seconds.

5-4 Reserved. Device returns 0.

3-0 A value of 0 means the device has passed its test. Non-zero valuesmean the device failed. Device-specific failure codes can be encodedin the non-zero value.

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0,1B*17DQG0$;B/$7

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Implementation Example: Choosing MIN_GNT and MAX_LAT

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6XEV\VWHP9HQGRU,'DQG6XEV\VWHP,'

7KHVHUHJLVWHUVDUHXVHGWRXQLTXHO\LGHQWLI\WKHH[SDQVLRQERDUGRUVXEV\VWHPZKHUHWKH3&,GHYLFHUHVLGHV7KH\SURYLGHDPHFKDQLVPIRUH[SDQVLRQERDUGYHQGRUVWRGLVWLQJXLVKWKHLUERDUGVIURPRQHDQRWKHUHYHQWKRXJKWKHERDUGVPD\KDYHWKHVDPH3&,FRQWUROOHURQWKHPDQGWKHUHIRUHWKHVDPH9HQGRU,'DQG'HYLFH,'

43 For x86 based PCs, the values in this register correspond to IRQ numbers (0-15) of the standard dual8259 configuration. The value 255 is defined as meaning "unknown" or "no connection" to the interruptcontroller. Values between 15 and 254 are reserved.

Revision 2.2

201

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6.2.5. Base Addresses

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6.2.5.1. Address Maps

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44 A company has only one Vendor ID. That value can be used in either the Vendor ID field ofconfiguration space (offset 00h) or the Subsystem Vendor ID field of configuration space (offset 2Ch). It isused in the Vendor ID field (offset 00h) if the company built the silicon. It is used in the Subsystem VendorID field (offset 2Ch) if the company built the add-in card. If a company builds both the silicon and the add-in card, then the same value would be used in both fields.

Revision 2.2

202

6SDFHPXVWUHWXUQDLQELWVHH)LJXUH%DVH$GGUHVVUHJLVWHUVWKDWPDSWR,26SDFHPXVWUHWXUQDLQELWVHH)LJXUH

)LJXUH%DVH$GGUHVV5HJLVWHUIRU0HPRU\

031

Base Address 10

IO space indicatorReserved

12

)LJXUH%DVH$GGUHVV5HJLVWHUIRU,2

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%DVH$GGUHVVUHJLVWHUVWKDWPDSLQWR0HPRU\6SDFHFDQEHELWVRUELWVZLGHWRVXSSRUWPDSSLQJLQWRDELWDGGUHVVVSDFHZLWKELWKDUGZLUHGWRD)RU0HPRU\%DVH$GGUHVVUHJLVWHUVELWVDQGKDYHDQHQFRGHGPHDQLQJDVVKRZQLQ7DEOH%LWVKRXOGEHVHWWRLIWKHGDWDLVSUHIHWFKDEOHDQGUHVHWWRRWKHUZLVH$GHYLFHFDQPDUNDUDQJHDVSUHIHWFKDEOHLIWKHUHDUHQRVLGHHIIHFWVRQUHDGVWKHGHYLFHUHWXUQVDOOE\WHVRQUHDGVUHJDUGOHVVRIWKHE\WHHQDEOHVDQGKRVWEULGJHVFDQPHUJHSURFHVVRUZULWHVUHIHUWR6HFWLRQLQWRWKLVUDQJHZLWKRXWFDXVLQJHUURUV%LWVDUHUHDGRQO\

45 Any device that has a range that behaves like normal memory should mark the range as prefetchable. Alinear frame buffer in a graphics device is an example of a range that should be marked prefetchable.

Revision 2.2

203

7DEOH0HPRU\%DVH$GGUHVV5HJLVWHU%LWV(QFRGLQJ

Bits 2/1 Meaning

00 Base register is 32 bits wide and mapping can bedone anywhere in the 32-bit Memory Space.

01 Reserved46

10 Base register is 64 bits wide and can be mappedanywhere in the 64-bit address space.

11 Reserved

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3RZHUXSVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHVE\ZULWLQJDYDOXHRIDOOVWRWKHUHJLVWHUDQGWKHQUHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQVLQDOOGRQWFDUHDGGUHVVELWVHIIHFWLYHO\VSHFLI\LQJWKHDGGUHVVVSDFHUHTXLUHG8QLPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVDUHKDUGZLUHGWR]HUR

7KLVGHVLJQLPSOLHVWKDWDOODGGUHVVVSDFHVXVHGDUHDSRZHURIWZRLQVL]HDQGDUHQDWXUDOO\DOLJQHG'HYLFHVDUHIUHHWRFRQVXPHPRUHDGGUHVVVSDFHWKDQUHTXLUHGEXWGHFRGLQJGRZQWRD.%VSDFHIRUPHPRU\LVVXJJHVWHGIRUGHYLFHVWKDWQHHGOHVVWKDQWKDWDPRXQW)RULQVWDQFHDGHYLFHWKDWKDVE\WHVRIUHJLVWHUVWREHPDSSHGLQWR0HPRU\6SDFHPD\FRQVXPHXSWR.%RIDGGUHVVVSDFHLQRUGHUWRPLQLPL]HWKHQXPEHURIELWVLQWKHDGGUHVVGHFRGHU'HYLFHVWKDWGRFRQVXPHPRUHDGGUHVVVSDFHWKDQWKH\XVHDUHQRWUHTXLUHGWRUHVSRQGWRWKHXQXVHGSRUWLRQRIWKDWDGGUHVVVSDFH'HYLFHVWKDWPDSFRQWUROIXQFWLRQVLQWR,26SDFHPXVWQRWFRQVXPHPRUHWKDQE\WHVSHU,2%DVH$GGUHVVUHJLVWHU7KHXSSHUELWVRIWKH,2%DVH$GGUHVVUHJLVWHUPD\EHKDUGZLUHGWR]HURIRUGHYLFHVLQWHQGHGIRUELW,2V\VWHPVVXFKDV3&FRPSDWLEOHV+RZHYHUDIXOOELWGHFRGHRI,2DGGUHVVHVPXVWVWLOOEHGRQH

46 The encoding to support memory space below 1M was supported in previous versions of thespecification. System software should recognize this encoding and handle appropriately.

Revision 2.2

204

Implementation Note: Sizing a 32 bit Base Address RegisterExample

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$W\SHKSUHGHILQHGKHDGHUKDVVL[':25'ORFDWLRQVDOORFDWHGIRU%DVH$GGUHVVUHJLVWHUVVWDUWLQJDWRIIVHWKLQ&RQILJXUDWLRQ6SDFH$GHYLFHPD\XVHDQ\RIWKHORFDWLRQVWRLPSOHPHQW%DVH$GGUHVVUHJLVWHUV$QLPSOHPHQWHGELW%DVH$GGUHVVUHJLVWHUFRQVXPHVWZRFRQVHFXWLYH':25'ORFDWLRQV6RIWZDUHORRNLQJIRULPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVPXVWVWDUWDWRIIVHWKDQGFRQWLQXHXSZDUGVWKURXJKRIIVHWK$W\SLFDOGHYLFHZLOOUHTXLUHRQHPHPRU\UDQJHIRULWVFRQWUROIXQFWLRQV6RPHJUDSKLFVGHYLFHVPD\XVHWZRUDQJHVRQHIRUFRQWUROIXQFWLRQVDQGDQRWKHUIRUDIUDPHEXIIHU$GHYLFHWKDWZDQWVWRPDSFRQWUROIXQFWLRQVLQWRERWKPHPRU\DQG,26SDFHVDWWKHVDPHWLPHPXVWLPSOHPHQWWZR%DVH$GGUHVVUHJLVWHUVRQHPHPRU\DQGRQH,27KHGULYHUIRUWKDWGHYLFHPLJKWRQO\XVHRQHVSDFHLQZKLFKFDVHWKHRWKHUVSDFHZLOOEHXQXVHG'HYLFHVDUHUHFRPPHQGHGDOZD\VWRPDSFRQWUROIXQFWLRQVLQWR0HPRU\6SDFH

6.2.5.2. Expansion ROM Base Address Register

6RPH3&,GHYLFHVHVSHFLDOO\WKRVHWKDWDUHLQWHQGHGIRUXVHRQH[SDQVLRQERDUGVLQ3&DUFKLWHFWXUHVUHTXLUHORFDO(3520VIRUH[SDQVLRQ520UHIHUWR6HFWLRQIRUDGHILQLWLRQRI520FRQWHQWV7KHIRXUE\WHUHJLVWHUDWRIIVHWKLQDW\SHKSUHGHILQHGKHDGHULVGHILQHGWRKDQGOHWKHEDVHDGGUHVVDQGVL]HLQIRUPDWLRQIRUWKLVH[SDQVLRQ520)LJXUHVKRZVKRZWKLVZRUGLVRUJDQL]HG7KHUHJLVWHUIXQFWLRQVH[DFWO\OLNHDELW%DVH$GGUHVVUHJLVWHUH[FHSWWKDWWKHHQFRGLQJDQGXVDJHRIWKHERWWRPELWVLVGLIIHUHQW7KHXSSHUELWVFRUUHVSRQGWRWKHXSSHUELWVRIWKH([SDQVLRQ520EDVHDGGUHVV7KHQXPEHURIELWVRXWRIWKHVHWKDWDGHYLFHDFWXDOO\LPSOHPHQWVGHSHQGVRQKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHV)RULQVWDQFHDGHYLFHWKDWUHTXLUHVD.%DUHDWRPDSLWVH[SDQVLRQ520ZRXOGLPSOHPHQWWKHWRSELWVLQWKHUHJLVWHUOHDYLQJWKHERWWRPRXWRIWKHVHKDUGZLUHGWR'HYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWLPSOHPHQWWKLVUHJLVWHU

'HYLFHLQGHSHQGHQWFRQILJXUDWLRQVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHVE\ZULWLQJDYDOXHRIDOOVWRWKHDGGUHVVSRUWLRQRIWKHUHJLVWHUDQGWKHQUHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQVLQDOOGRQWFDUHELWVHIIHFWLYHO\VSHFLI\LQJWKHVL]HDQGDOLJQPHQWUHTXLUHPHQWV7KHDPRXQWRIDGGUHVVVSDFHDGHYLFHUHTXHVWVPXVWQRWEHJUHDWHUWKDQ0%

Revision 2.2

205

031Expansion ROM Base Address

Reserved

11011

(Upper 21 bits)

Expansion ROM Enable

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6.3. PCI Expansion ROMs7KH3&,VSHFLILFDWLRQSURYLGHVDPHFKDQLVPZKHUHGHYLFHVFDQSURYLGHH[SDQVLRQ520FRGHWKDWFDQEHH[HFXWHGIRUGHYLFHVSHFLILFLQLWLDOL]DWLRQDQGSRVVLEO\DV\VWHPERRWIXQFWLRQUHIHUWR6HFWLRQ7KHPHFKDQLVPDOORZVWKH520WRFRQWDLQVHYHUDOGLIIHUHQWLPDJHVWRDFFRPPRGDWHGLIIHUHQWPDFKLQHDQGSURFHVVRUDUFKLWHFWXUHV7KLVVHFWLRQVSHFLILHVWKHUHTXLUHGLQIRUPDWLRQDQGOD\RXWRIFRGHLPDJHVLQWKHH[SDQVLRQ5201RWHWKDW3&,GHYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWDOORZWKDW520WREHDFFHVVHGZLWKDQ\FRPELQDWLRQRIE\WHHQDEOHV7KLVVSHFLILFDOO\PHDQVWKDW':25'DFFHVVHVWRWKHH[SDQVLRQ520PXVWEHVXSSRUWHG

7KHLQIRUPDWLRQLQWKH520VLVODLGRXWWREHFRPSDWLEOHZLWKH[LVWLQJ,QWHO[([SDQVLRQ520KHDGHUVIRU,6$(,6$DQG0&DGDSWHUVEXWLWZLOODOVRVXSSRUWRWKHUPDFKLQHDUFKLWHFWXUHV7KHLQIRUPDWLRQDYDLODEOHLQWKHKHDGHUKDVEHHQH[WHQGHGVRWKDWPRUHRSWLPXPXVHFDQEHPDGHRIWKHIXQFWLRQSURYLGHGE\WKHDGDSWHUDQGVRWKDWWKHPLQLPXPDPRXQWRI0HPRU\6SDFHLVXVHGE\WKHUXQWLPHSRUWLRQRIWKHH[SDQVLRQ520FRGH

7KH3&,([SDQVLRQ520KHDGHULQIRUPDWLRQVXSSRUWVWKHIROORZLQJIXQFWLRQV

• $OHQJWKFRGHLVSURYLGHGWRLGHQWLI\WKHWRWDOFRQWLJXRXVDGGUHVVVSDFHQHHGHGE\WKH3&,GHYLFH520LPDJHDWLQLWLDOL]DWLRQ

• $QLQGLFDWRULGHQWLILHVWKHW\SHRIH[HFXWDEOHRULQWHUSUHWLYHFRGHWKDWH[LVWVLQWKH520DGGUHVVVSDFHLQHDFK520LPDJH

• $UHYLVLRQOHYHOIRUWKHFRGHDQGGDWDRQWKH520LVSURYLGHG

• 7KH9HQGRU,'DQG'HYLFH,'RIWKHVXSSRUWHG3&,GHYLFHDUHLQFOXGHGLQWKH520 47Note that it is the address decoder that is shared, not the registers themselves. The Expansion ROM BaseAddress register and other Base Address registers must be able to hold unique values at the same time.

Revision 2.2

206

2QHPDMRUGLIIHUHQFHLQWKHXVDJHPRGHOEHWZHHQ3&,H[SDQVLRQ520VDQGVWDQGDUG,6$(,6$DQG0&520VLVWKDWWKH520FRGHLVQHYHUH[HFXWHGLQSODFH,WLVDOZD\VFRSLHGIURPWKH520GHYLFHWR5$0DQGH[HFXWHGIURP5$07KLVHQDEOHVG\QDPLFVL]LQJRIWKHFRGHIRULQLWLDOL]DWLRQDQGUXQWLPHDQGSURYLGHVVSHHGLPSURYHPHQWVZKHQH[HFXWLQJUXQWLPHFRGH

6.3.1. PCI Expansion ROM Contents

3&,GHYLFHH[SDQVLRQ520VPD\FRQWDLQFRGHH[HFXWDEOHRULQWHUSUHWLYHIRUPXOWLSOHSURFHVVRUDUFKLWHFWXUHV7KLVPD\EHLPSOHPHQWHGLQDVLQJOHSK\VLFDO520ZKLFKFDQFRQWDLQDVPDQ\FRGHLPDJHVDVGHVLUHGIRUGLIIHUHQWV\VWHPDQGSURFHVVRUDUFKLWHFWXUHVVHH)LJXUH(DFKLPDJHPXVWVWDUWRQDE\WHERXQGDU\DQGPXVWFRQWDLQWKH3&,H[SDQVLRQ520KHDGHU7KHVWDUWLQJSRLQWRIHDFKLPDJHGHSHQGVRQWKHVL]HRISUHYLRXVLPDJHV7KHODVWLPDJHLQD520KDVDVSHFLDOHQFRGLQJLQWKHKHDGHUWRLGHQWLI\LWDVWKHODVWLPDJH

Image 0

Image 1

Image N

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6.3.1.1. PCI Expansion ROM Header Format

7KHLQIRUPDWLRQUHTXLUHGLQHDFK520LPDJHLVVSOLWLQWRWZRGLIIHUHQWDUHDV2QHDUHDWKH520KHDGHULVUHTXLUHGWREHORFDWHGDWWKHEHJLQQLQJRIWKH520LPDJH7KHVHFRQGDUHDWKH3&,'DWD6WUXFWXUHPXVWEHORFDWHGLQWKHILUVW.%RIWKHLPDJH7KHIRUPDWIRUWKH3&,([SDQVLRQ520+HDGHULVJLYHQEHORZ7KHRIIVHWLVDKH[DGHFLPDOQXPEHUIURPWKHEHJLQQLQJRIWKHLPDJHDQGWKHOHQJWKRIHDFKILHOGLVJLYHQLQE\WHV

([WHQVLRQVWRWKH3&,([SDQVLRQ520+HDGHUDQGRUWKH3&,'DWD6WUXFWXUHPD\EHGHILQHGE\VSHFLILFV\VWHPDUFKLWHFWXUHV([WHQVLRQVIRU3&$7FRPSDWLEOHV\VWHPVDUHGHVFULEHGLQ6HFWLRQ

Revision 2.2

207

Offset Length Value Description0h 1 55h ROM Signature, byte 11h 1 AAh ROM Signature, byte 2

2h-17h 16h xx Reserved (processor architecture unique data)18h-19h 2 xx Pointer to PCI Data Structure

ROM Signature The ROM Signature is a two-byte field containing a 55h inthe first byte and AAh in the second byte. This signaturemust be the first two bytes of the ROM address space foreach image of the ROM.

Pointer to PCI DataStructure

The Pointer to the PCI Data Structure is a two-byte pointer inlittle endian format that points to the PCI Data Structure. Thereference point for this pointer is the beginning of the ROMimage.

6.3.1.2. PCI Data Structure Format

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Offset Length Description0 4 Signature, the string "PCIR"4 2 Vendor Identification6 2 Device Identification8 2 ReservedA 2 PCI Data Structure LengthC 1 PCI Data Structure RevisionD 3 Class Code10 2 Image Length12 2 Revision Level of Code/Data14 1 Code Type15 1 Indicator16 2 Reserved

Signature These four bytes provide a unique signature for the PCI DataStructure. The string "PCIR" is the signature with "P" beingat offset 0, "C" at offset 1, etc.

Vendor Identification The Vendor Identification field is a 16-bit field with the samedefinition as the Vendor Identification field in theConfiguration Space for this device.

Device Identification The Device Identification field is a 16-bit field with the samedefinition as the Device Identification field in theConfiguration Space for this device.

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Resvd Reserved 16-bit field.

Note that in earlier versions of the PCI Local BusSpecification this field pointed to ROM located Vital ProductData. This has been superseded by Vital Product Data asdescribed in Section 6.4.

PCI Data StructureLength

The PCI Data Structure Length is a 16-bit field that definesthe length of the data structure from the start of the datastructure (the first byte of the Signature field). This field is inlittle-endian format and is in units of bytes.

PCI Data StructureRevision

The PCI Data Structure Revision field is an eight-bit field thatidentifies the data structure revision level. This revision levelis 0.

Class Code The Class Code field is a 24-bit field with the same fields anddefinition as the class code field in the Configuration Spacefor this device.

Image Length The Image Length field is a two-byte field that represents thelength of the image. This field is in little-endian format, andthe value is in units of 512 bytes.

Revision Level The Revision Level field is a two-byte field that contains therevision level of the code in the ROM image.

Code Type The Code Type field is a one-byte field that identifies thetype of code contained in this section of the ROM. The codemay be executable binary for a specific processor and systemarchitecture or interpretive code. The following code typesare assigned:

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Indicator Bit 7 in this field tells whether or not this is the last image inthe ROM. A value of 1 indicates "last image;" a value of 0indicates that another image follows. Bits 0-6 are reserved.

48 Open Firmware is a processor architecture and system architecture independent standard for dealing withdevice specific option ROM code. Documentation for Open Firmware is available in the IEEE 1275-1994Standard for Boot (Initialization, Configuration) Firmware Core Requirements and Practices. A relateddocument, PCI Bus Binding to IEEE 1275-1994, specifies the application of Open Firmware to the PCIlocal bus, including PCI-specific requirements and practices. This document may be obtained usinganonymous FTP to the machine playground.sun.com with the filename/pub/p1275/bindings/postscript/PCI.ps.

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6.3.2. Power-on Self Test (POST) Code

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6.3.3. PC-compatible Expansion ROMs

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6.3.3.1. ROM Header Extensions

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Offset Length Value Description0h 1 55h ROM Signature byte 11h 1 AAh ROM Signature byte 22h 1 xx Initialization Size - size of the code in units of

512 bytes3h 3 xx Entry point for INIT function. POST does a

FAR CALL to this location.6h-17h 12h xx Reserved (application unique data)18h-19h 2 xx Pointer to PCI Data Structure

6.3.3.1.1. POST Code Extensions

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6.3.3.1.2. INIT Function Extensions

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6.3.3.1.3. Image Structure

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Header

PCI Data structureRuntime size

Initialization size

Checksum byte

Checksum byte

Image size

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6.4. Vital Product Data9LWDO3URGXFW'DWD93'LVWKHLQIRUPDWLRQWKDWXQLTXHO\GHILQHVLWHPVVXFKDVWKHKDUGZDUHVRIWZDUHDQGPLFURFRGHHOHPHQWVRIDV\VWHP7KH93'SURYLGHVWKHV\VWHPZLWKLQIRUPDWLRQRQYDULRXV)58V)LHOG5HSODFHDEOH8QLWLQFOXGLQJ3DUW1XPEHU6HULDO1XPEHUDQGRWKHUGHWDLOHGLQIRUPDWLRQ93'DOVRSURYLGHVDPHFKDQLVPIRUVWRULQJLQIRUPDWLRQVXFKDVSHUIRUPDQFHDQGIDLOXUHGDWDRQWKHGHYLFHEHLQJPRQLWRUHG7KHREMHFWLYHIURPDV\VWHPSRLQWRIYLHZLVWRFROOHFWWKLVLQIRUPDWLRQE\UHDGLQJLWIURPWKHKDUGZDUHVRIWZDUHDQGPLFURFRGHFRPSRQHQWV

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6.8.1. Message Capability Structure

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6.8.1.1. Capability ID

7::0 CAP_ID The value of 05h in this field identifies the function asmessage signaled interrupt capable. This field isread only.

6.8.1.2. Next Pointer

7::0 NXT_PTR Pointer to the next item in the capabilities list. Mustbe NULL for the final item in the list. This field is readonly.

6.8.1.3. Message Control

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Bits Field Description

15::08 ReservedAlways returns 0 on a read and a write operation hasno effect.

7 64 bit addresscapable

If 1, the function is capable of generating a 64-bitmessage address.

If 0, the function is not capable of generating a 64-bitmessage address.

This bit is read only.

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Bits Field Description

6::4 Multiple MessageEnable

System software writes to this field to indicate thenumber of allocated messages (equal to or less thanthe number of requested messages). The number ofallocated messages is aligned to a power of two. If afunction requests four messages (indicated by aMultiple Message Capable encoding of “010”), systemsoftware can allocate either four, two, or onemessage by writing a “010”, “001, or “000” to thisfield, respectively. When MSI is enabled, a device willbe allocated at least 1 message. The encoding isdefined as:

Encoding # of messages allocated

000 1

001 2

010 4

011 8

100 16

101 32

110 Reserved

111 Reserved

This field’s state after reset is “000”.

This field is read/write.

3::1 Multiple MessageCapable

System software reads this field to determine thenumber of requested messages. The number ofrequested messages must be aligned to a power oftwo (if a function requires three messages, it requestsfour by initializing this field to “010”). The encoding isdefined as:

Encoding # of messages requested

000 1

001 2

010 4

011 8

100 16

101 32

110 Reserved

111 Reserved

This field is read/only.

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Bits Field Description

0 MSI EnableIf 1, the function is permitted to use MSI to requestservice and is prohibited from using its INTx# pin (ifimplemented). System configuration software setsthis bit to enable MSI. A device driver is prohibitedfrom writing this bit to mask a function’s servicerequest.

If 0, the function is prohibited from using MSI torequest service.

This bit’s state after reset is 0 (MSI is disabled).

This bit is read/write.

6.8.1.4. Message Address

Bits Field Description

31::02 MessageAddress

System-specified message address.

If the Message Enable bit (bit 0 of the MessageControl register) is set, the contents of this registerspecify the DWORD aligned address (AD[31::02]) forthe MSI memory write transaction. AD[1::0] aredriven to zero during the address phase.

This field is read/write.

01::00 Reserved Always returns 0 on read. Write operations have noeffect.

6.8.1.5. Message Upper Address (Optional)

Bits Field Description

31::00 Message UpperAddress

System-specified message upper address.

This register is optional and is implemented only if thedevice supports a 64-bit message address (bit 7 inMessage Control register set)49. If the MessageEnable bit (bit 0 of the Message Control register) isset, the contents of this register (if non-zero) specifythe upper 32-bits of a 64-bit message address(AD[63::32]). If the contents of this register are zero,the device uses the 32 bit address specified by themessage address register.

This field is read/write.

49 This register is required when the device supports 64-bit addressing (DAC) when acting as a master.

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6.8.1.6. Message Data

Bits Field Description

15::00 Message Data System-specified message.

Each MSI function is allocated up to 32 uniquemessages.

System architecture specifies the number of uniquemessages supported by the system.

If the Message Enable bit (bit 0 of the MessageControl register) is set, the message data is drivenonto the lower word (AD[15::00]) of the memory writetransaction’s data phase. AD[31::16] are driven tozero during the memory write transaction’s dataphase. C/BE[3::0]# are asserted during the dataphase of the memory write transaction.

The Multiple Message Enable field (bits 6-4 of theMessage Control register) defines the number of loworder message data bits the function is permitted tomodify to generate its system software allocatedmessages. For example, a Multiple Message Enableencoding of “010” indicates the function has beenallocated four messages and is permitted to modifymessage data bits 1 and 0 (a function modifies thelower message data bits to generate the allocatednumber of messages). If the Multiple MessageEnable field is “000”, the function is not permitted tomodify the message data.

This field is read/write.

6.8.2. MSI Operation

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6.8.2.1. MSI Transaction Termination

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If the MSI write transaction results in a data parity error, the master that originated theMSI write transaction is required to assert SERR# (if bit 8 in the Command register isset) and to set the appropriated bits in the Status register (refer to Section 3.7.4.).

6.8.2.2. MSI Transaction Reception and Ordering Requirements

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Chapter 766 MHz PCI Specification

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7.3. Device Implementation Considerations

7.3.1. Configuration Space

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7.5. Protocol

7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition

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50 Configuration software identifies agent capabilities by checking the 66MHZ_CAPABLE bit in the Statusregister. This includes both the primary and secondary Status registers in a PCI-to-PCI bridge. This allowsconfiguration software to detect a 33 MHz PCI agent on a 66 MHz PCI bus or a 66 MHz PCI agent on a33 MHz PCI bus and issue a warning to the user describing the situation.

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Bus66MHZ_CAPABLE51

Agent66MHZ_CAPABLE Description

0 0 33 MHz PCI agent located on a33 MHz PCI bus

0 1 66 MHz PCI agent located on a33 MHz PCI bus52

1 0 33 MHz PCI agent located on a66 MHz PCI bus52

1 1 66 MHz PCI agent located on a66 MHz PCI bus

7.5.2. Latency

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7.6. Electrical Specification

7.6.1. Overview

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51 The bus 66MHZ_CAPABLE status bit is located in a bridge’s Status registers.

52 This condition may cause the configuration software to generate a warning to the user stating that thecard is installed in an inappropriate socket and should be relocated.

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7.6.2. Transition Roadmap to 66 MHz PCI

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Tcyc ≥ Tval + Tprop + Tskew + Tsu

Tval =11 ns Tprop = 10 ns Tskew = 2ns Tsu=7ns

Tval Tprop Tskew Tsu6 ns 5 ns 1 ns 3 ns

Tcyc = 30 ns

Tcyc = 15 ns

33 MHZ

66 MHZ

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7.6.3. Signaling Environment

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7.6.3.1. DC Specifications

5HIHUWR6HFWLRQ

7.6.3.2. AC Specifications

7DEOH$&6SHFLILFDWLRQV

Symbol Parameter Condition Min Max Units Notes

AC Drive Points

Ioh(AC,min) Switching CurrentHigh, minimum

Vout = 0.3Vcc -12Vcc - mA 1

Ioh(AC,max) Switching CurrentHigh, maximum

Vout = 0.7Vcc - -32Vcc mA

Iol(AC,min) Switching CurrentLow, minimum

Vout = 0.6Vcc 16Vcc - mA 1

Iol(AC,max) SwitchingCurrent Low,maximum

Vout = 0.18Vcc - 38Vcc mA

DC Drive Points

VOH Output highvoltage

Iout = -0.5 mA 0.9Vcc - V 2

VOL Output lowvoltage

Iout = 1.5 mA - 0.1Vcc V 2

Slew Rate

tr Output rise slewrate

0.3Vcc to 0.6Vcc 1 4 V/ns 3

tf Output fall slewrate

0.6Vcc to 0.3Vcc 1 4 V/ns 3

Clamp Current

Ich High clampcurrent

Vcc + 4 > Vin ≥ Vcc + 1 25 + (Vin - Vcc - 1) / 0.015 - mA

Icl Low clampcurrent

-3 < Vin ≤ -1 -25 + (Vin + 1) / 0.015 - mA

NOTES:1. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half

size drivers may be used on these signals. This specification does not apply to CLK and RST# which are systemoutputs. "Switching Current High" specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, andINTD# which are open drain outputs.

2. These DC values are duplicated from Section 4.2.2.1. and are included here for completeness.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than theinstantaneous rate at any point within the transition range. The specified load (see Figure 7-7) is optional. Thedesigner may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local BusSpecification. However, adherence to both maximum and minimum parameters is required (the maximum is notsimply a guideline). Rise slew rate does not apply to open drain outputs.

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7.6.3.3. Maximum AC Ratings and Device Protection

5HIHUWR6HFWLRQ

7.6.4. Timing Specification

7.6.4.1. Clock Specification

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T_high

T_low

0.3 Vcc

T_cyc

0.5 Vcc

3.3 volt Clock

0.4 Vcc

0.6 Vcc

0.2 Vcc

0.4 Vcc, p-to-p(minimum)

)LJXUH9&ORFN:DYHIRUP

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Revision 2.2

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7DEOH&ORFN6SHFLILFDWLRQV

66 MHz 33 MHz4

Symbol Parameter Min Max Min Max Units Notes

Tcyc CLK Cycle Time 15 30 30 ∞ ns 1,3

Thigh CLK High Time 6 11 ns

Tlow CLK Low Time 6 11 ns

- CLK Slew Rate 1.5 4 1 4 V/ns 2

Spread Spectrum Requirements

fmod modulationfrequency

30 33 - - kHz

fspread frequencyspread

-1 9 %

NOTES:

1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLKrequirements vary depending upon whether the clock frequency is above 33 MHz.

a. Device operational parameters at frequencies at or under 33 MHz will conform to the specifications inChapter 4. The clock frequency may be changed at any time during the operation of the system solong as the clock edges remain "clean" (monotonic) and the minimum cycle and high and low timesare not violated. The clock may only be stopped in a low state. A variance on this specification isallowed for components designed for use on the system planar only. Refer to Section 4.2.3.1. formore information.

b. For clock frequencies between 33 MHz and 66 MHz, the clock frequency may not change exceptwhile RST# is asserted or when spread spectrum clocking (SSC) is used to reduce EMI emissions.

2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be metacross the minimum peak-to-peak portion of the clock waveform as shown in Figure 7-2. Clock slew rateis measured by the slew rate circuit shown in Figure 7-7.

3. The minimum clock period must not be violated for any single clock cycle; i.e., accounting for all systemjitter.

4. These values are duplicated from Section 4.2.3.1. and included here for comparison.

Implementation Note: Spread Spectrum Clocking (SSC)

6SUHDGLQJWKHIUHTXHQF\LVRQO\DOORZHGEHORZWKHPD[LPXPFORFNIUHTXHQF\WKDWLVVSHFLILHGLHWKHPLQLPXPFORFNSHULRGVKRZQLQ7DEOHFDQQRWEHYLRODWHG,QRWKHUZRUGVWKHIUHTXHQF\FKDQJHFDQRQO\RFFXUWRUHGXFHWKHIUHTXHQF\RIWKHFORFNDQGQHYHUWRLQFUHDVHLW:KHQ3//VDUHXVHGWRWUDFNCLKWKH\QHHGWRWUDFNWKH66&PRGXODWLRQTXLFNO\LQRUGHUQRWWRDFFXPXODWHH[FHVVLYHSKDVHGLIIHUHQFHEHWZHHQWKH3//LQSXWDQGRXWSXWFORFNVFRPPRQO\UHIHUUHGWRDV66&WUDFNLQJVNHZ7KHDPRXQWRIWUDFNLQJVNHZGHSHQGVRQWKH3//EDQGZLGWKSKDVHDQJOHDWN+]DQGWKHDPRXQWRIWKHVSUHDG,WLVGHVLUDEOHWRPD[LPL]HEDQGZLGWKDQGRUUHGXFHWKHSKDVHDQJOHLQRUGHUWRPLQLPL]HWKHWUDFNLQJVNHZRWKHUZLVHWKH66&IUHTXHQF\VSUHDGRIWKHV\VWHPPXVWEHUHGXFHGWKHUHE\UHGXFLQJWKH66&(0,UHGXFWLRQFDSDELOLW\

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7.6.4.2. Timing Parameters

7DEOH0+]DQG0+]7LPLQJ3DUDPHWHUV

66 MHz 33 MHz7

Symbol Parameter Min Max Min Max Units Notes

Tval CLK to Signal Valid Delay -bused signals

2 6 2 11 ns 1, 2,3, 8

Tval(ptp) CLK to Signal Valid Delay -point to point signals

2 6 2 12 ns 1, 2,3, 8

Ton Float to Active Delay 2 2 ns 1, 8, 9

Toff Active to Float Delay 14 28 ns 1, 9

Tsu Input Setup Time to CLK -bused signals

3 7 ns 3, 4,10

Tsu(ptp) Input Setup Time to CLK -point to point signals

5 10,12 ns 3, 4

Th Input Hold Time from CLK 0 0 ns 4

Trst Reset Active Time afterpower stable

1 1 ms 5

Trst-clk Reset Active Time after CLKstable

100 100 µs 5

Trst-off Reset Active to output floatdelay

40 40 ns 5, 6

trrsu REQ64# to RST# setup time 10Tcyc 10Tcyc ns

trrh RST# to REQ64# hold time 0 50 0 50 ns

Trhfa RST# high to firstConfiguration access

225 225 clocks

Trhff RST# high to first FRAME#assertion

5 5 clocks

NOTES:

1. See the timing measurement conditions in Figure 7-3. It is important that all driven signal transitions drive to theirVoh or Vol level within one Tcyc.

2. Minimum times are measured at the package pin with the load circuit shown in Figure 7-7. Maximum times aremeasured with the load circuit shown in Figures 7-5 and 7-6.

3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.

4. See the timing measurement conditions in Figure 7-4.

5. If M66EN is asserted, CLK is stable when it meets the requirements in Section 7.6.4.1. RST# is asserted anddeasserted asynchronously with respect to CLK. Refer to Section 4.3.2. for more information.

6. All output drivers must be floated when RST# is active. Refer to Section 4.3.2. for more information.

7. These values are duplicated from Section 4.2.3.2. and are included here for comparison.

8. When M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be reduced to1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is deasserted.

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229

9. For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total currentdelivered through the component pin is less than or equal to the leakage current specification.

10. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at thesame time. Refer to Section 3.10., item 9 for additional details.

7.6.4.3. Measurement and Test Conditions

CLK

OUTPUTDELAY

T_val

V_test

V_tfall

V_th

V_tl

T_on

Tri-StateOUTPUT

OUTPUTDELAY

V_trise

T_val

T_off

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INPUTinputsvalid

V_th

V_tl

T_hT_su

CLK

V_test

V_test

V_test V_max

V_th

V_tl

)LJXUH,QSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV

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7DEOH0HDVXUHPHQW&RQGLWLRQ3DUDPHWHUV

Symbol 3.3V Signaling Units NotesVth 0.6Vcc V 1

Vtl 0.2Vcc V 1

Vtest 0.4Vcc V

Vtrise 0.285Vcc V 2

Vtfall 0.615Vcc V 2

Vmax 0.4Vcc V 1

Input SignalSlew Rate

1.5 V/ns 3

NOTES:

1. The test for the 3.3V environment is done with 0.1*Vcc of overdrive.Vmax specifies the maximum peak-to-peak waveform allowed formeasuring input timing. Production testing may use different voltagevalues but must correlate results back to these parameters.

2. Vtrise and Vtfall are reference voltages for timing measurements only.Developers of 66 MHz PCI systems need to design buffers that launchenough energy into a 25 Ω transmission line so that correct inputlevels are guaranteed after the first reflection.

3. Outputs will be characterized and measured at the package pin withthe load shown in Figure 7-7. Input signal slew rate will be measuredbetween 0.3Vcc and 0.6Vcc.

25 Ω 10 pF

1/2 in. max.

outputbuffer

pin

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25 Ω10 pF

Vcc

1/2 in. max.

)LJXUH7YDOPD[)DOOLQJ(GJH

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231

1K Ω10 pF

outputbuffer

pin 1/2 in. max.

Vcc

1K Ω

)LJXUH7YDOPLQDQG6OHZ5DWH

7.6.5. Vendor Provided Specification

5HIHUWR6HFWLRQ

7.6.6. Recommendations

7.6.6.1. Pinout Recommendations

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7.6.6.2. Clocking Recommendations

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Revision 2.2

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Clock Source

PCI Add-inConnector

Add-in Board

Device C66 MHz

66 MHzDevice B

66 MHz Device A

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7.7. System (Planar) Specification

7.7.1. Clock Uncertainty

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7DEOH&ORFN6NHZ3DUDPHWHUV

Symbol 66 MHz 3.3V Signaling 33 MHz 3.3V Signaling Units

Vtest 0.4Vcc 0.4Vcc V

Tskew 1 (max) 2 (max) ns

53 The system designer must address an additional source of clock skew. This clock skew occurs betweentwo components that have clock input trip points at opposite ends of the Vil - Vih range. In certaincircumstances, this can add to the clock skew measurement as described here. In all cases, total clock skewmust be limited to the specified number.

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CLK(@Device #1)

CLK(@Device #2)

V_testV_ih

T_skew

T_skew

T_skew

V_testV_il

V_il

V_ih

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7.7.2. Reset

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7.7.3. Pullups

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7.7.4. Power

7.7.4.1. Power Requirements

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7.7.4.2. Sequencing

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7.7.4.3. Decoupling

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7.7.5. System Timing Budget

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Revision 2.2

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Implementation Note: Determining the End of Tprop7KHHQGRI7SURSLVDOZD\VGHWHUPLQHGE\WKHFDOFXODWLRQPHWKRGWKDWSURGXFHVWKHORQJHUYDOXHRI7SURS7KHVKDSHRIWKHZDYHIRUPDWWKHLQSXWEXIIHUZLOOGHWHUPLQHZKLFKPHDVXUHPHQWPHWKRGZLOOSURGXFHWKHORQJHUYDOXH

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Revision 2.2

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(b)(a)

0.7Vcc

0.6Vcc

0.5Vcc

0.4Vcc

0.3Vcc

0.2Vcc

0.1Vcc

0

testV

triseV

ihV

thV

testV

triseV

ihV

thV

testV

ilV

tlV

tfallV

DrivingTest Load

DrivingTest Load

DrivingBus

Input SignalSlew RateDriving Bus

DrivingTest Load

DrivingBus

DrivingTest Load

Input SignalSlew Rate

Driving Bus

testV

ilV

tlV

tfallV

DrivingTest Load

Driving Bus

DrivingTest Load

Driving Bus

Input SignalSlew Rate

(f)(e)

0.9Vcc

0.8Vcc

0.7Vcc

0.6Vcc

0.5Vcc

0.4Vcc

0.3Vcc

0.2Vcc

0.1Vcc

0

(d)(c)

0.9Vcc

0.8Vcc

0.7Vcc

0.6Vcc

0.5Vcc

0.4Vcc

0.3Vcc

0.2Vcc

0.1Vcc

0

Input SignalSlew Rate

0.7Vcc

0.6Vcc

0.5Vcc

0.4Vcc

0.3Vcc

0.2Vcc

0.1Vcc

0

0.9Vcc

0.8Vcc

0.7Vcc

0.6Vcc

0.5Vcc

0.4Vcc

0.3Vcc

0.2Vcc

0.1Vcc

0

0.9Vcc

0.8Vcc

0.7Vcc

0.6Vcc

0.5Vcc

0.4Vcc

0.3Vcc

0.2Vcc

0.1Vcc

0

testV

triseV

ihV

thV

testV

ilV

tlV

tfallV

TpropTprop

Tprop

Tprop

TpropTprop

)LJXUH0HDVXUHPHQWRI7SURS

UHIHUWR7DEOHIRUSDUDPHWHUYDOXHV

Revision 2.2

236

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Timing Element 33 MHz 66 MHz 50 MHz1 Units Notes

Tcyc 30 15 20 ns

Tval 11 6 6 ns

Tprop 10 5 10 ns 2

Tsu 7 3 3 ns

Tskew 2 1 1 ns 3

NOTES:

1. The 50 MHz example is shown for example purposes only.

2. These times are computed. The other times are fixed. Thus, slowing down the bus clock enables thesystem manufacturer to gain additional distance or add additional loads. The component specificationsare required to guarantee operation at 66 MHz.

3 Clock skew specified here includes all sources of skew. If spread spectrum clocking (SSC) is used on thesystem board, the maximum clock skew at the input of the device on an expansion board includes SSCtracking skew.

7.7.6. Physical Requirements

7.7.6.1. Routing and Layout Recommendations for Four-LayerBoards

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7.7.6.2. Planar Impedance

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7.7.7. Connector Pin Assignments

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54 As a general rule, there will be only one such connector, but more than one are possible in certain cases.

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Appendix ASpecial Cycle Messages

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Appendix BState Machines

This appendix describes master and target state machines. These state machines are forillustrative purposes only and are included to help illustrate PCI protocol. Actualimplementations should not directly use these state machines. The machines arebelieved to be correct; however, if a conflict exists between the specification and thestate machines, the specification has precedence.

The state machines use three types of variables: states, PCI signals, and internal signals.They can be distinguished from each other by:

State in a state machine = STATEPCI signal = SIGNALInternal signal = Signal

The state machines assume no delays from entering a state until signals are generatedand available for use in the machine. All PCI signals are latched on the rising edge ofCLK.

The state machines support some options (but not all) discussed in the PCI specification.A discussion about each state and the options illustrated follows the definition of eachstate machine. The target state machine assumes medium decode and, therefore, doesnot describe fast decode. If fast decode is implemented, the state diagrams (and theirassociated equations) will need to be changed to support fast decode. Caution needs tobe taken when supporting fast decode (Refer to Section 3.4.2.).

The bus interface consists of two parts. The first is the bus sequencer that performs theactual bus operation. The second part is the backend or hardware application. In amaster, the backend generates the transaction and provides the address, data, command,Byte Enables, and the length of the transfer. It is also responsible for the address when atransaction is retried. In a target, the backend determines when a transaction isterminated. The sequencer performs the bus operation as requested and guarantees thePCI protocol is not violated. Note that the target implements a resource lock.

The state machine equations assume a logical operation where "*" is an AND functionand has precedence over "+" which is an OR function. Parentheses have precedenceover both. The "!" character is used to indicate the NOT of the variable. In the statemachine equations, the PCI SIGNALs represent the actual state of the signal on the PCIbus. Low true signals will be true or asserted when they appear as !SIGNAL# and willbe false or deasserted when they appear as SIGNAL#. High true signals will be true or

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asserted when they appear as SIGNAL and will be false or deasserted when they appearas !SIGNAL. Internal signals will be true when they appear as Signal and false whenthey appear as !Signal. A few of the output enable equations use the "==" symbol torefer to the previous state. For example:

OE[PAR] == [S_DATA * !TRDY# * (cmd=read)]

This indicates the output buffer for PAR is enabled when the previous state is S_DATA,TRDY# is asserted, the transaction is a read. The first state machine presented is for thetarget, the second is the master. Caution needs to be taken when an agent is both amaster and a target. Each must have its own state machine that can operateindependently of the other to avoid deadlocks. This means that the target state machinecannot be affected by the master state machine. Although they have similar states, theycannot be built into a single machine.

Note: LOCK# can only be implemented by a bridge; refer to Appendix F for detailsabout the use of LOCK#. For a non-bridge device, the use of LOCK# is prohibited.

F R E E L O C K ED

ID LE B _ BU S Y

S _D AT A

TU R N _ AR

B A CK O F F

Target LOCK Machine

TargetSequencer

Machine

IDLE or TURN_AR -- Idle condition or completed transaction on bus.

goto IDLE if FRAME#goto B_BUSY if !FRAME# * !Hit

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B_BUSY -- Not involved in current transaction.

goto B_BUSY if (!FRAME# + !D_done) * !Hitgoto IDLE if FRAME# * D_done + FRAME# * !D_done * !DEVSEL#goto S_DATA if (!FRAME# + !IRDY#) * Hit * (!Term + Term * Ready)

* (FREE + LOCKED * L_lock#)goto BACKOFF *if (!FRAME# + !IRDY#) * Hit

* (Term * !Ready + LOCKED * !L_lock#)

S_DATA -- Agent has accepted request and will respond.

goto S_DATA if !FRAME# * !STOP# * !TRDY# * IRDY#+ !FRAME# * STOP# + FRAME# * TRDY# * STOP#

goto BACKOFF if !FRAME# * !STOP# * (TRDY# + !IRDY#)goto TURN_AR if FRAME# * (!TRDY# + !STOP#)

BACKOFF -- Agent busy unable to respond at this time.

goto BACKOFF if !FRAME#goto TURN_AR if FRAME#

Target LOCK Machine

FREE -- Agent is free to respond to all transactions.

goto LOCKED if !FRAME# * LOCK# * Hit * (IDLE + TURN_AR)+ L_lock# * Hit * B_BUSY)

goto FREE if ELSE

LOCKED -- Agent will not respond unless LOCK# is deasserted during the addressphase.

goto FREE if FRAME# * LOCK#goto LOCKED if ELSE

Target of a transaction is responsible to drive the following signals: 55

OE[AD[31::00]] = (S_DATA + BACKOFF) * Tar_dly * (cmd = read)OE[TRDY#] = BACKOFF + S_DATA + TURN_AR (See note.)

OE[STOP#] = BACKOFF + S_DATA + TURN_AR (See note.)

OE[DEVSEL#] = BACKOFF + S_DATA + TURN_AR (See note.)

OE[PAR] = OE[AD[31::00]] delayed by one clockOE[PERR#] = R_perr + R_perr (delayed by one clock)

Note: If the device does fast decode, OE[PERR#] must be delayed one clock toavoid contention.

When the target supports the Special Cycle command, an additional term must be included to ensurethese signals are not enabled during a Special Cycle transaction.

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TRDY# = !(Ready * !T_abort * S_DATA * (cmd=write + cmd=read * Tar_dly))STOP# = ![BACKOFF + S_DATA * (T_abort + Term)

* (cmd=write + cmd=read * Tar_dly)]DEVSEL# = ![(BACKOFF + S_DATA) * !T_abort]PAR = even parity across AD[31::00] and C/BE#[3::0] lines.PERR# = R_perr

Definitions

These signals are between the target bus sequencer and the backend. They indicate howthe bus sequencer should respond to the current bus operation.

Hit = Hit on address decode.D_done = Decode done. Device has completed the address decode.T_abort = Target is in an error condition and requires the current transaction to stop.Term = Terminate the transaction. (Internal conflict or > n wait states.)Ready = Ready to transfer data.L_lock# = Latched (during address phase) version of LOCK#.Tar_dly = Turn around delay only required for zero wait state decode.R_perr = Report parity error is a pulse of one PCI clock in duration.Last_target = Device was the target of the last (prior) PCI transaction.

The following paragraphs discuss each state and describe which equations can beremoved if some of the PCI options are not implemented.

The IDLE and TURN_AR are two separate states in the state machine, but are combinedhere because the state transitions are the same from both states. They are implementedas separate states because active signals need to be deasserted before the target tri-statesthem.

If the target cannot do single cycle address decode, the path from IDLE to S_DATA canbe removed. The reason the target requires the path from the TURN_AR state toS_DATA and B_BUSY is for back-to-back bus operations. The target must be able todecode back-to-back transactions.

B_BUSY is a state where the agent waits for the current transaction to complete and thebus to return to the Idle state. B_BUSY is useful for devices that do slow addressdecode or perform subtractive decode. If the target does neither of these two options, thepath to S_DATA and BACKOFF may be removed. The term "!Hit" may be removedfrom the B_BUSY equation also. This reduces the state to waiting for the current bustransaction to complete.

S_DATA is a state where the target transfers data and there are no optional equations.

BACKOFF is where the target goes after it asserts STOP# and waits for the master todeassert FRAME#.

FREE and LOCKED refer to the state of the target with respect to a lock operation. Ifthe target does not implement LOCK#, then these states are not required. FREEindicates when the agent may accept any request when it is the target. If LOCKED, thetarget will retry any request when it is the target unless LOCK# is deasserted during theaddress phase. The agent marks itself locked whenever it is the target of a transactionand LOCK# is deasserted during the address phase. It is a little confusing for the targetto lock itself on a transaction that is not locked. However, from an implementation pointof view, it is a simple mechanism that uses combinatorial logic and always works. Thedevice will unlock itself at the end of the transaction when it detects FRAME# andLOCK# both deasserted.

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The second equation in the goto LOCKED in the FREE state can be removed if fastdecode is done. The first equation can be removed if medium or slow decode is done.L_lock# is LOCK# latched during the address phase and is used when the agent’s decodecompletes.

IDLE

S_TAR

TURN_AR

ADDR

M_DATA

DR_BUS

FREE BUSY

Master LOCK Machine

MasterSequencerMachine

Master Sequencer Machine

IDLE -- Idle condition on bus.

goto ADDR if (Request * !Step) * !GNT# * FRAME# * IRDY#goto DR_BUS if (Request * Step + !Request) * !GNT# * FRAME# * IRDY#

goto IDLE if ELSE

ADDR -- Master starts a transaction.

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M_DATA -- Master transfers data.

goto M_DATA if !FRAME# + FRAME# * TRDY# * STOP#* !Dev_to

goto ADDR if (Request *!Step) * !GNT# * FRAME# * !TRDY# *STOP# * L-cycle * (Sa +FB2B_Ena)

goto S_TAR if FRAME# * !STOP# + FRAME# * Dev_togoto TURN_AR if ELSE

TURN_AR -- Transaction complete, do housekeeping.

goto ADDR if (Request * !Step) * !GNT#goto DR_BUS if (Request * Step + !Request) * !GNT#goto IDLE if GNT#

S_TAR -- Stop was asserted, do turn around cycle.

goto DR_BUS if !GNT#goto IDLE if GNT#

DR_BUS -- Bus parked at this agent or agent is using address stepping.

goto DR_BUS if (Request * Step + !Request)* !GNT#goto ADDR if (Request * !Step) * !GNT#goto IDLE if GNT#

Master LOCK Machine

FREE -- LOCK# is not in use (not owned).

goto FREE if LOCK# + !LOCK# * Own_lockgoto BUSY if !LOCK# * !Own_lock

BUSY -- LOCK# is currently being used (owned).

goto FREE if LOCK# * FRAME#goto BUSY if !LOCK# + !FRAME#

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The master of the transaction is responsible to drive the following signals:

Enable the output buffers:

OE[FRAME#] = ADDR + M_DATAOE[C/BE#[3::0]] = ADDR + M_DATA + DR_BUS

if ADDR drive commandif M_DATA drive byte enablesif DR_BUS if (Step * Request) drive command else drive lines to a valid state

OE[AD[31::00] = ADDR + M_DATA * (cmd=write) + DR_BUSif ADDR drive addressif M_DATA drive dataif DR_BUS if (Step * Request) drive address else drive lines to a valid state

OE [LOCK#] = Own_lock * M_DATA + OE [LOCK#] * (!FRAME# + !LOCK#)OE[IRDY#] == [M_DATA + ADDR]OE[PAR] = OE[AD[31::00]] delayed by one clockOE[PERR#] = R_perr + R_perr (delayed by one clock)

The following signals are generated from state and sampled (not asynchronous) bussignals.

FRAME# = !( ADDR + M_DATA * !Dev_to * [!Comp * (!To + !GNT#) * STOP#] + !Ready )

IRDY# = ![M_DATA * (Ready + Dev_to)]REQ# = ![(Request * !Lock_a + Request * Lock_a * FREE)

*!(S_TAR * Last State was S_TAR)]

LOCK# = Own_lock * ADDR + Target_abort + Master_abort + M_DATA * !STOP# * TRDY# * !Ldt + Own_lock * !Lock_a * Comp * M_DATA * FRAME# * !TRDY#

PAR = even parity across AD[31::00] and C/BE#[3::0] lines.PERR# = R_perr

Master_abort = (M_DATA * Dev_to)Target_abort = (!STOP# * DEVSEL# * M_DATA * FRAME# * !IRDY#)Own_lock = LOCK# * FRAME# * IRDY# * Request * !GNT# * Lock_a

+ Own_lock * (!FRAME# + !LOCK#)

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Definitions

These signals go between the bus sequencer and the backend. They provide informationto the sequencer when to perform a transaction and provide information to the backendon how the transaction is proceeding. If a cycle is retried, the backend will make thecorrect modification to the affected registers and then indicate to the sequencer toperform another transaction. The bus sequencer does not remember that a transactionwas retried or aborted but takes requests from the backend and performs the PCItransaction.

Master_abort = The transaction was aborted by the master. (No DEVSEL#.)Target_abort = The transaction was aborted by the target.Step = Agent using address stepping (wait in the state until !Step).Request = Request pending.Comp = Current transaction in last data phase.L-cycle = Last cycle was a write.To = Master timeout has expired.Dev_to = Devsel timer has expired without DEVSEL# being asserted.Sa = Next transaction to same agent as previous transaction.Lock_a = Request is a locked operation.Ready = Ready to transfer data.Sp_cyc = Special Cycle command.Own_lock = This agent currently owns LOCK#.Ldt = Data was transferred during a LOCK operation.R_perr = Report parity error is a pulse one PCI clock in duration.FB2B_Ena = Fast Back-to-Back Enable (Configuration register bit).

The master state machine has many options built in that may not be of interest to someimplementations. Each state will be discussed indicating what affect certain optionshave on the equations.

IDLE is where the master waits for a request to do a bus operation. The only option inthis state is the term "Step". It may be removed from the equations if address stepping isnot supported. All paths must be implemented. The path to DR_BUS is required toinsure that the bus is not left floating for long periods. The master whose GNT# isasserted must go to the drive bus if its Request is not asserted.

ADDR has no options and is used to drive the address and command on the bus.

M_DATA is where data is transferred. If the master does not support fast back-to-backtransactions, the path to the ADDR state is not required.

The equations are correct from the protocol point of view. However, compilers maygive errors when they check all possible combinations. For example, because ofprotocol, Comp cannot be asserted when FRAME# is deasserted. Comp indicates themaster is in the last data phase, and FRAME# must be deasserted for this to be true.

TURN_AR is where the master deasserts signals in preparation for tri-stating them. Thepath to ADDR may be removed if the master does not do back-to-back transactions.

S_TAR could be implemented a number of ways. The state was chosen to clarify that"state" needs to be remembered when the target asserts STOP#.

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DR_BUS is used when GNT# has been asserted, and the master either is not prepared tostart a transaction (for address stepping) or has none pending. If address stepping is notimplemented, then the equation in goto DR_BUS that has "Step" may be removed andthe goto ADDR equation may also remove "Step".

If LOCK# is not supported by the master, the FREE and BUSY states may be removed.These states are for the master to know the state of LOCK# when it desires to do alocked transaction. The state machine simply checks for LOCK# being asserted. Onceasserted, it stays BUSY until FRAME# and LOCK# are both deasserted signifying thatLOCK# is now free.

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Appendix COperating Rules

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Target Signals 7KHIROORZLQJJHQHUDOUXOHVJRYHUQFRAME#IRDY#TRDY#DQGSTOP#ZKLOH

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F 2QFHWKHWDUJHWDVVHUWVSTOP#LWPXVWNHHSSTOP#DVVHUWHGXQWLOFRAME#LVGHDVVHUWHGZKHUHXSRQLWPXVWGHDVVHUWSTOP#

G 2QFHDWDUJHWKDVDVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL#TRDY#RUSTOP#XQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV

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$QDJHQWFODLPVWREHWKHWDUJHWRIWKHDFFHVVE\DVVHUWLQJDEVSEL#

DEVSEL#PXVWEHDVVHUWHGZLWKRUSULRUWRWKHHGJHDWZKLFKWKHWDUJHWHQDEOHVLWVRXWSXWVTRDY#STOP#RURQDUHDGADOLQHV

2QFHDEVSEL#KDVEHHQDVVHUWHGLWFDQQRWEHGHDVVHUWHGXQWLOWKHODVWGDWDSKDVHKDVFRPSOHWHGH[FHSWWRVLJQDO7DUJHW$ERUW

Data Phases 7KHVRXUFHRIWKHGDWDLVUHTXLUHGWRDVVHUWLWV[RDY#VLJQDOXQFRQGLWLRQDOO\ZKHQ

GDWDLVYDOLGIRDY#RQDZULWHWUDQVDFWLRQTRDY#RQDUHDGWUDQVDFWLRQ

'DWDLVWUDQVIHUUHGEHWZHHQPDVWHUDQGWDUJHWRQHDFKFORFNHGJHIRUZKLFKERWKIRDY#DQGTRDY#DUHDVVHUWHG

/DVWGDWDSKDVHFRPSOHWHVZKHQ

D FRAME#LVGHDVVHUWHGDQGTRDY#LVDVVHUWHGQRUPDOWHUPLQDWLRQRU

E FRAME#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHGWDUJHWWHUPLQDWLRQRU

F FRAME#LVGHDVVHUWHGDQGWKHGHYLFHVHOHFWWLPHUKDVH[SLUHG0DVWHU$ERUWRU

G DEVSEL#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHG7DUJHW$ERUW

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Arbitration 7KHDJHQWLVSHUPLWWHGWRVWDUWDWUDQVDFWLRQRQO\LQWKHIROORZLQJWZRFDVHV

D GNT#LVDVVHUWHGDQGWKHEXVLVLGOHFRAME#DQGIRDY#DUHGHDVVHUWHG

E GNT#LVDVVHUWHGLQWKHODVWGDWDSKDVHRIDWUDQVDFWLRQDQGWKHDJHQWLVVWDUWLQJDQHZWUDQVDFWLRQXVLQJIDVWEDFNWREDFNWLPLQJFRAME#LVGHDVVHUWHGDQGTRDY#RUSTOP#LVDVVHUWHGRUWKHWUDQVDFWLRQWHUPLQDWHVZLWK0DVWHU$ERUW

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D ,IGNT#LVGHDVVHUWHGDQGFRAME#LVDVVHUWHGRQWKHVDPHFORFNWKHEXVWUDQVDFWLRQLVYDOLGDQGZLOOFRQWLQXH

E 2QHGNT#FDQEHGHDVVHUWHGFRLQFLGHQWZLWKDQRWKHUGNT# EHLQJDVVHUWHGLIWKHEXVLVQRWLQWKH,GOHVWDWH2WKHUZLVHDRQHFORFNGHOD\LVUHTXLUHGEHWZHHQWKHGHDVVHUWLRQRIDGNT#DQGWKHDVVHUWLRQRIWKHQH[WGNT#RUHOVHWKHUHPD\EHFRQWHQWLRQRQWKHADOLQHVDQGPAR

F :KLOHFRAME#LVGHDVVHUWHGGNT#PD\EHGHDVVHUWHGDWDQ\WLPHLQRUGHUWRVHUYLFHDKLJKHUSULRULW\PDVWHURULQUHVSRQVHWRWKHDVVRFLDWHGREQ#EHLQJGHDVVHUWHG

:KHQWKHDUELWHUDVVHUWVDQDJHQWVGNT#DQGWKHEXVLVLQWKH,GOHVWDWHWKDWDJHQWPXVWHQDEOHLWVAD[31::00]C/BE[3::0]#DQGRQHFORFNODWHUPARRXWSXWEXIIHUVZLWKLQHLJKW3&,FORFNVUHTXLUHGZKLOHWZRWKUHHFORFNVLVUHFRPPHQGHG

Latency25. All targets are required to complete the initial data phase of a transaction (read or

write) within 16 clocks from the assertion of FRAME#. Host bus bridges have anexception (refer to Section 3.5.1.1.).

56 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would winarbitration at a given instant in time.

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26. The target is required to complete a subsequent data phase within eight clocks fromthe completion of the previous data phase.

27. A master is required to assert its IRDY# within eight clocks for any given data phase(initial and subsequent).

Device Selection28. A target must do a full decode before driving/asserting DEVSEL# or any other

target response signal.

29. A target must assert DEVSEL# (claim the transaction) before it is allowed to issueany other target response.

30. In all cases except Target-Abort, once a target asserts DEVSEL# it must notdeassert DEVSEL# until FRAME# is deasserted (IRDY# is asserted) and the lastdata phase has completed.

31. A PCI device is a target of a Type 0 configuration transaction (read or write) only ifits IDSEL is asserted, and AD[1::0] are “00” during the address phase of thecommand.

Parity 3DULW\LVJHQHUDWHGDFFRUGLQJWRWKHIROORZLQJUXOHV

D 3DULW\LVFDOFXODWHGWKHVDPHRQDOO3&,WUDQVDFWLRQVUHJDUGOHVVRIWKHW\SHRUIRUP

E 7KHQXPEHURI³´VRQAD[31::00]C/BE[3::0]#DQGPARHTXDOVDQHYHQQXPEHU

F 7KHQXPEHURI³´VRQAD[63::32]C/BE[7::4]#DQGPAR64HTXDOVDQHYHQQXPEHU

G *HQHUDWLQJSDULW\LVQRWRSWLRQDOLWPXVWEHGRQHE\DOO3&,FRPSOLDQWGHYLFHV

33. Only the master of a corrupted data transfer is allowed to report parity errors tosoftware using mechanisms other than PERR# (i.e., requesting an interrupt orasserting SERR#). In some cases, the master delegates this responsibility to a PCI-to-PCI bridge handling posted memory write data. See the PCI-to-PCI BridgeArchitecture Specification for details.

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Appendix DClass Codes

7KLVDSSHQGL[GHVFULEHVWKHFXUUHQW&ODVV&RGHHQFRGLQJV7KLVOLVWPD\EHHQKDQFHGDWDQ\WLPH7KH3&,6,*ZHESDJHVFRQWDLQWKHODWHVWYHUVLRQ&RPSDQLHVZLVKLQJWRGHILQHDQHZHQFRGLQJVKRXOGFRQWDFWWKH3&,6,*$OOXQVSHFLILHGYDOXHVDUHUHVHUYHGIRU6,*DVVLJQPHQW

Base Class Meaning

00h Device was built before Class Codedefinitions were finalized

01h Mass storage controller

02h Network controller

03h Display controller

04h Multimedia device

05h Memory controller

06h Bridge device

07h Simple communication controllers

08h Base system peripherals

09h Input devices

0Ah Docking stations

0Bh Processors

0Ch Serial bus controllers

0Dh Wireless controller

0Eh Intelligent I/O controllers

0Fh Satellite communication controllers

10h Encryption/Decryption controllers

11h Data acquisition and signal processingcontrollers

12h - FEh Reserved

FFh Device does not fit in any defined classes

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Base Class Sub-Class Interface Meaning

00h00h 00h All currently implemented devices

except VGA-compatible devices01h 00h VGA-compatible device

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Base Class Sub-Class Interface Meaning00h 00h SCSI bus controller01h xxh IDE controller (see below)

01h 02h 00h Floppy disk controller03h 00h IPI bus controller04h 00h RAID controller80h 00h Other mass storage controller

)LJXUH'3URJUDPPLQJ,QWHUIDFH%\WH/D\RXWIRU,'(&RQWUROOHU&ODVV&RGH

7KH3&,6,*GRFXPHQW3&,,'(&RQWUROOHU6SHFLILFDWLRQFRPSOHWHO\GHVFULEHVWKHOD\RXWDQGPHDQLQJRIELWVWKURXJKLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KHGRFXPHQW%XV0DVWHU3URJUDPPLQJ,QWHUIDFHIRU,'($7$&RQWUROOHUVGHVFULEHVWKHPHDQLQJRIELWLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KLVGRFXPHQWFDQEHREWDLQHGYLD)$;E\FDOOLQJDQGUHTXHVWLQJGRFXPHQW

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Base Class Sub-Class Interface Meaning00h 00h Ethernet controller

02h 01h 00h Token Ring controller02h 00h FDDI controller03h 00h ATM controller04h 00h ISDN controller80h 00h Other network controller

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Base Class Sub-Class Interface Meaning00000000b VGA-compatible controller. Memory

addresses 0A0000h through0BFFFFh. I/O addresses 3B0h to3BBh and 3C0h to 3DFh and allaliases of these addresses.

03h 00h 00000001b 8514-compatible controller -- 2E8hand its aliases, 2EAh-2EFh

01h 00h XGA controller02h 00h 3D controller80h 00h Other display controller

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Base Class Sub-Class Interface Meaning00h 00h Video device01h 00h Audio device

04h 02h 00h Computer telephony device80h 00h Other multimedia device

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Base Class Sub-Class Interface Meaning00h 00h RAM

05h 01h 00h Flash80h 00h Other memory controller

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Base Class Sub-Class Interface Meaning00h 00h Host bridge01h 00h ISA bridge02h 00h EISA bridge

06h 03h 00h MCA bridge00h PCI-to-PCI bridge

04h 01h Subtractive Decode PCI-to-PCIbridge. This interface code identifiesthe PCI-to-PCI bridge as a device thatsupports subtractive decoding inaddition to all the currently definedfunctions of a PCI-to-PCI bridge.

05h 00h PCMCIA bridge06h 00h NuBus bridge07h 00h CardBus bridge08h xxh RACEway bridge (see below)80h 00h Other bridge device

5$&(ZD\LVDQ$16,VWDQGDUG$16,9,7$VZLWFKLQJIDEULF)RUWKH3URJUDPPLQJ,QWHUIDFHELWV>@DUHUHVHUYHGUHDGRQO\DQGUHWXUQ]HURV%LWGHILQHVWKHRSHUDWLRQPRGHDQGLVUHDGRQO\

7UDQVSDUHQWPRGH

(QGSRLQWPRGH

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Base Class 07h

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Base Class Sub-Class Interface Meaning00h Generic XT-compatible serial

controller00h 01h 16450-compatible serial controller

02h 16550-compatible serial controller03h 16650-compatible serial controller04h 16750-compatible serial controller05h 16850-compatible serial controller06h 16950-compatible serial controller00h Parallel port01h Bi-directional parallel port

01h 02h ECP 1.X compliant parallel port03h IEEE1284 controllerFEh IEEE1284 target device (not a

controller)07h 02h 00h Multiport serial controller

00h Generic modem01h Hayes compatible modem, 16450-

compatible interface (see below)03h 02h Hayes compatible modem, 16550-

compatible interface (see below)03h Hayes compatible modem, 16650-

compatible interface (see below)04h Hayes compatible modem, 16750-

compatible interface (see below)80h 00h Other communications device

)RU+D\HVFRPSDWLEOHPRGHPVWKHILUVWEDVHDGGUHVVUHJLVWHUDWRIIVHWKPDSVWKHDSSURSULDWHFRPSDWLEOHLHHWFUHJLVWHUVHWIRUWKHVHULDOFRQWUROOHUDWWKHEHJLQQLQJRIWKHPDSSHGVSDFH1RWHWKDWWKHVHUHJLVWHUVFDQEHHLWKHUPHPRU\RU,2PDSSHGGHSHQGLQJZKDWNLQGRI%$5LVXVHG

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Base Class Sub-Class Interface Meaning00h Generic 8259 PIC01h ISA PIC02h EISA PIC

00h 10h I/O APIC interrupt controller (seebelow)

20h I/O(x) APIC interrupt controller00h Generic 8237 DMA controller

01h 01h ISA DMA controller08h 02h EISA DMA controller

00h Generic 8254 system timer02h 01h ISA system timer.

02h EISA system timers (two timers)03h 00h Generic RTC controller

01h ISA RTC controller04h 00h Generic PCI Hot-Plug controller80h 00h Other system peripheral

)RU,2$3,&,QWHUUXSW&RQWUROOHUWKH%DVH$GGUHVV5HJLVWHUDWRIIVHW[LVXVHGWRUHTXHVWDPLQLPXPRIE\WHVRIQRQSUHIHWFKDEOHPHPRU\7ZRUHJLVWHUVZLWKLQWKDWVSDFHDUHORFDWHGDW%DVH[,26HOHFW5HJLVWHUDQG%DVH[,2:LQGRZ5HJLVWHU)RUDIXOOGHVFULSWLRQRIWKHXVHRIWKHVHUHJLVWHUVUHIHUWRWKHGDWDVKHHWIRUWKH,QWHO(%LQWKH3&,VHW(,6$%ULGJH'DWDERRN

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Base Class Sub-Class Interface Meaning00h 00h Keyboard controller01h 00h Digitizer (pen)02h 00h Mouse controller

09h 03h 00h Scanner controller04h 00h Gameport controller (generic)

10h Gameport controller (see below)80h 00h Other input controller

$JDPHSRUWFRQWUROOHUZLWKD3URJUDPPLQJ,QWHUIDFH KLQGLFDWHVWKDWDQ\%DVH$GGUHVVUHJLVWHUVLQWKLVIXQFWLRQWKDWUHTXHVWDVVLJQ,2DGGUHVVVSDFHWKHUHJLVWHUVLQWKDW,2VSDFHFRQIRUPWRWKHVWDQGDUGµOHJDF\¶JDPHSRUWV7KHE\WHDWRIIVHWKLQDQ,2UHJLRQEHKDYHVDVDOHJDF\JDPHSRUWLQWHUIDFHZKHUHUHDGVWRWKHE\WHUHWXUQMR\VWLFNJDPHSDGLQIRUPDWLRQDQGZULWHVWRWKHE\WHVWDUWWKH5&WLPHU7KHE\WHDWRIIVHWKLVDQDOLDVRIWKHE\WHDWRIIVHWK$OORWKHUE\WHVLQDQ,2UHJLRQDUHXQVSHFLILHGDQGFDQEHXVHGLQYHQGRUXQLTXHZD\V

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Base Class Sub-Class Interface Meaning0Ah 00h 00h Generic docking station

80h 00h Other type of docking station

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Base Class Sub-Class Interface Meaning00h 00h 38601h 00h 486

0Bh 02h 00h Pentium10h 00h Alpha20h 00h PowerPC30h 00h MIPS40h 00h Co-processor

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Base Class Sub-Class Interface Meaning00 00h IEEE 1394 (FireWire)

10h IEEE 1394 following the 1394OpenHCI specification

01h 00h ACCESS.bus02h 00h SSA

00h Universal Serial Bus (USB) followingthe Universal Host ControllerSpecification

0Ch 03h 10h Universal Serial Bus (USB) followingthe Open Host Controller Specification

80h Universal Serial Bus with no specificprogramming interface

FEh USB device (not host controller)04h 00h Fibre Channel05h 00h SMBus (System Management Bus)

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Base Class Sub-Class Interface Meaning00 00h iRDA compatible controller

0Dh 01h 00h Consumer IR controller10h 00h RF controller80h 00h Other type of wireless controller

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Base Class Sub-Class Interface Meaning0Eh 00 xxh Intelligent I/O (I2O) Architecture

Specification 1.000h Message FIFO at offset 040h

7KHVSHFLILFDWLRQIRU,QWHOOLJHQW,2$UFKLWHFWXUH,2FDQEHGRZQORDGHGIURP

IWSLQWHOFRPSXE,$/LR

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Base Class Sub-Class Interface Meaning01h 00h TV

0Fh 02h 00h Audio03h 00h Voice04h 00h Data

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Base Class Sub-Class Interface Meaning00h 00h 1HWZRUNDQGFRPSXWLQJHQGHFU\SWLRQ

10h 10h 00h (QWHUWDLQPHQWHQGHFU\SWLRQ80h 00h Other en/decryption

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Base Class Sub-Class Interface Meaning00h 00h '3,2PRGXOHV

11h 80h 00h 2WKHUGDWDDFTXLVLWLRQVLJQDOSURFHVVLQJFRQWUROOHUV

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Appendix ESystem Transaction Ordering

Many programming tasks, especially those controlling intelligent peripheral devicescommon in PCI systems, require specific events to occur in a specific order. If theevents generated by the program do not occur in the hardware in the order intended bythe software, a peripheral device may behave in a totally unexpected way. PCItransaction ordering rules are written to give hardware the flexibility to optimizeperformance by rearranging certain events that do not affect device operation, yet strictlyenforce the order of events that do affect device operation.

One performance optimization that PCI systems are allowed to do is the posting ofmemory write transactions. Posting means the transaction is captured by an intermediateagent; e.g., a bridge from one bus to another, so that the transaction completes at thesource before it actually completes at the intended destination. This allows the source toproceed with the next operation while the transaction is still making its way through thesystem to its ultimate destination.

While posting improves system performance, it complicates event ordering. Since thesource of a write transaction proceeds before the write actually reaches its destination,other events that the programmer intended to happen after the write may happen beforethe write. Many of the PCI ordering rules focus on posting buffers requiring them to beflushed to keep this situation from causing problems.

If the buffer flushing rules are not written carefully, however, deadlock can occur. Therest of the PCI transaction ordering rules prevent the system buses from deadlockingwhen posting buffers must be flushed.

Simple devices do not post outbound transactions. Therefore, their requirements aremuch simpler than those presented here for bridges. Refer to Section 3.2.5.1. for therequirements for simple devices.

The focus of the remainder of this appendix is on a PCI-to-PCI bridge. This allows thesame terminology to be used to describe a transaction initiated on either interface and iseasier to understand. To apply these rules to other bridges, replace a PCI transactiontype with its equivalent transaction type of the host bus (or other specific bus). Whilethe discussion focuses on a PCI-to-PCI bridge, the concepts can be applied to all bridges.

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The ordering rules for a specific implementation may vary. This appendix covers therules for all accesses traversing a bridge assuming that the bridge can handle multipletransactions at the same time in each direction. Simpler implementations are possiblebut are not discussed here.

E.1 Producer - Consumer Ordering Model

The Producer - Consumer model for data movement between two masters is an exampleof a system that would require this kind of ordering. In this model, one agent, theProducer, produces or creates the data and another agent, the Consumer, consumes oruses the data. The Producer and Consumer communicate between each other via a flagand a status element. The Producer sets the flag when all the data has been written andthen waits for a completion status code. The Consumer waits until it finds the flag set,then it resets the flag, consumes the data, and writes the completion status code. Whenthe Producer finds the completion status code, it clears it and the sequence repeats.Obviously, the order in which the flag and data are written is important. If some of theProducer’s data writes were posted, then without buffer-flushing rules it might bepossible for the Consumer to see the flag set before the data writes had completed. ThePCI ordering rules are written such that no matter which writes are posted, the Consumercan never see the flag set and read the data until the data writes are finished. Thisspecification refers to this condition as “having a consistent view of data.” Notice that ifthe Consumer were to pass information back to the Producer in addition to the statuscode, the order of writing this additional information and the status code becomesimportant, just as it was for the data and flag.

In practice, the flag might be a doorbell register in a device or it might be a main-memory pointer to data located somewhere else in memory. And the Consumer mightsignal the Producer using an interrupt or another doorbell register, rather than having theProducer poll the status element. But in all cases, the basic need remains the same; theProducer’s writes to the data area must complete before the Consumer observes that theflag has been set and reads the data.

This model allows the data, the flag, the status element, the Producer, and the Consumerto reside anywhere in the system. Each of these can reside on different buses and theordering rules maintain a consistent view of the data. For example, in Figure E-1, theagent producing the data, the flag, and the status element reside on Bus 1, while theactual data and the Consumer of the data both reside on Bus 0. The Producer writes thelast data and the PCI-to-PCI bridge between Bus 0 and 1 completes the access by postingthe data. The Producer of the data then writes the flag changing its status to indicate thatthe data is now valid for the Consumer to use. In this case, the flag has been set beforethe final datum has actually been written (to the final destination). PCI ordering rulesrequire that when the Consumer of the data reads the flag (to determine if the data isvalid), the read will cause the PCI-to-PCI bridge to flush the posted write data to thefinal destination before completing the read. When the Consumer determines the data isvalid by checking the flag, the data is actually at the final destination.

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PCI-PCIBridge

Producer Flag

PCI Bus 1

PCI Bus 0

Consumer Data

Status

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The ordering rules lead to the same results regardless of where the Producer, theConsumer, the data, the flag, and the status element actually reside. The data is alwaysat the final destination before the Consumer can read the flag. This is true even when allfive reside on different bus segments of the system. In one configuration, the data willbe forced to the final destination when the Consumer reads the flag. In anotherconfiguration, the read of the flag occurs without forcing the data to its final destination;however, the read request of the actual data pushes the final datum to the finaldestination before completing the read.

A system may have multiple Producer-Consumer pairs operating simultaneously, withdifferent data - flag-status sets located all around the system. But since only oneProducer can write to a single data-flag set, there are no ordering requirements betweendifferent masters. Writes from one master on one bus may occur in one order on onebus, with respect to another master’s writes, and occur in another order on another bus.In this case, the rules allow for some writes to be rearranged; for example, an agent onBus 1 may see Transaction A from a master on Bus 1 complete first, followed byTransaction B from another master on Bus 0. An agent on Bus 0 may see Transaction Bcomplete first followed by Transaction A. Even though the actual transactions completein a different order, this causes no problem since the different masters must beaddressing different data-flag sets.

E.2. Summary of PCI Ordering Requirements

Following is a summary of the general PCI ordering requirements presented inSection 3.2.5. These requirements apply to all PCI transactions, whether they are usingDelayed Transactions or not.

General Requirements

1. The order of a transaction is determined when it completes. Transactions terminatedwith Retry are only requests and can be handled by the system in any order.

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2. Memory writes can be posted in both directions in a bridge. I/O and Configurationwrites are not posted. (I/O writes can be posted in the Host Bridge, but somerestrictions apply.) Read transactions (Memory, I/O, or Configuration) are notposted.

3. Posted memory writes moving in the same direction through a bridge will completeon the destination bus in the same order they complete on the originating bus.

4. Write transactions crossing a bridge in opposite directions have no orderingrelationship.

5. A read transaction must push ahead of it through the bridge any posted writesoriginating on the same side of the bridge and posted before the read. Before theread transaction can complete on its originating bus, it must pull out of the bridgeany posted writes that originated on the opposite side and were posted before theread command completes on the read-destination bus.

6. A bridge can never make the acceptance (posting) of a memory write transaction as atarget contingent on the prior completion of a non-locked transaction as a master onthe same bus. Otherwise, a deadlock may occur. Bridges are allowed to refuse toaccept a memory write for temporary conditions which are guaranteed to be resolvedwith time. A bridge can make the acceptance of a memory write transaction as atarget contingent on the prior completion of locked transaction as a master only ifthe bridge has already established a locked operation with its intended target.

The following is a summary of the PCI ordering requirements specific to DelayedTransactions, presented in Section 3.3.3.3.

Delayed Transaction Requirements

1. A target that uses Delayed Transactions may be designed to have any number ofDelayed Transactions outstanding at one time.

2. Only non-posted transactions can be handled as Delayed Transactions.

3. A master must repeat any transaction terminated with Retry since the target may beusing a Delayed Transaction.

4. Once a Delayed Request has been attempted on the destination bus, it must continueto be repeated until it completes on the destination bus. Before it is attempted on thedestination bus, it is only a request and may be discarded at any time.

5. A Delayed Completion can only be discarded when it is a read from a prefetchableregion, or if the master has not repeated the transaction in 2 15 clocks.

6. A target must accept all memory writes addressed to it, even while completing arequest using Delayed Transaction termination.

7. Delayed Requests and Delayed Completions are not required to be kept in theiroriginal order with respect to themselves or each other.

8. Only a Delayed Write Completion can pass a Posted Memory Write. A PostedMemory Write must be given an opportunity to pass everything except anotherPosted Memory Write.

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9. A single master may have any number of outstanding requests terminated withRetry. However, if a master requires one transaction to be completed before another,it cannot attempt the second one on PCI until the first one has completed.

E.3. Ordering of Requests

A transaction is considered to be a request when it is presented on the bus. When thetransaction is terminated with Retry, it is still considered a request. A transactionbecomes complete or a completion when data actually transfers (or is terminated withMaster-Abort or Target-Abort). The following discussion will refer to transactions asbeing a request or completion depending on the success of the transaction.

A transaction that is terminated with Retry has no ordering relationship with any otheraccess. Ordering of accesses is only determined when an access completes (transfersdata). For example, four masters A, B, C, and D reside on the same bus segment and alldesire to generate an access on the bus. For this example, each agent can only request asingle transaction at a time and will not request another until the current accesscompletes. The order in which transactions complete are based on the algorithm of thearbiter and the response of the target, not the order in which each agent’s REQ# signalwas asserted. Assuming that some requests are terminated with Retry, the order inwhich they complete is independent of the order they were first requested. By changingthe arbiter’s algorithm, the completion of the transactions can be any sequence (i.e., A,B, C, and then D or B, D, C, and then A, and so on). Because the arbiter can change theorder in which transactions are requested on the bus, and, therefore, the completion ofsuch transactions, the system is allowed to complete them in any order it desires. Thismeans that a request from any agent has no relationship with a request from any otheragent. The only exception to this rule is when LOCK# is used, which is described later.

Take the same four masters (A, B, C, and D) used in the previous paragraph andintegrate them onto a single piece of silicon (a multi-function device). For a multi-function device, the four masters operate independent of each other, and each functiononly presents a single request on the bus for this discussion. The order their requestscomplete is the same as if they where separate agents and not a multi-function device,which is based on the arbitration algorithm. Therefore, multiple requests from a singleagent may complete in any order, since they have no relationship to each other.

Another device, not a multi-function device, has multiple internal resources that cangenerate transactions on the bus. If these different sources have some orderingrelationship, then the device must ensure that only a single request is presented on thebus at any one time. The agent must not attempt a subsequent transaction until theprevious transaction completes. For example, a device has two transactions to completeon the bus, Transaction A and Transaction B and A must complete before B to preserveinternal ordering requirements. In this case, the master cannot attempt B until A hascompleted.

The following example would produce inconsistent results if it were allowed to occur.Transaction A is to a flag that covers data, and Transaction B accesses the actual datacovered by the flag. Transaction A is terminated with Retry, because the addressedtarget is currently busy or resides behind a bridge. Transaction B is to a target that isready and will complete the request immediately. Consider what happens when these

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two transactions are allowed to complete in the wrong order. If the master allowsTransaction B to be presented on the bus after Transaction A was terminated with Retry,Transaction B can complete before Transaction A. In this case, the data may be accessedbefore it is actually valid. The responsibility to prevent this from occurring rests withthe master, which must block Transaction B from being attempted on the bus untilTransaction A completes. A master presenting multiple transactions on the bus mustensure that subsequent requests (that have some relationship to a previous request) arenot presented on the bus until the previous request has completed. The system isallowed to complete multiple requests from the same agent in any order. When a masterallows multiple requests to be presented on the bus without completing, it must repeateach request independent of how any of the other requests complete.

E.4. Ordering of Delayed Transactions

A Delayed Transaction progresses to completion in three phases:

1. Request by the master

2. Completion of the request by the target

3. Completion of the transaction by the master

During the first phase, the master generates a transaction on the bus, the target decodesthe access, latches the information required to complete the access, and terminates therequest with Retry. The latched request information is referred to as a Delayed Request.During the second phase, the target independently completes the request on thedestination bus using the latched information from the Delayed Request. The result ofcompleting the Delayed Request on the destination bus produces a Delayed Completion,which consists of the latched information of the Delayed Request and the completionstatus (and data if a read request). During the third phase, the master successfully re-arbitrates for the bus and reissues the original request. The target decodes the requestand gives the master the completion status (and data if a read request). At this point, theDelayed Completion is retired and the transaction has completed.

The number of simultaneous Delayed Transactions a bridge is capable of handling islimited by the implementation and not by the architecture. Table E-1 represents theordering rules when a bridge in the system is capable of allowing multiple transactions toproceed in each direction at the same time. Each column of the table represents anaccess that was accepted by the bridge earlier, while each row represents a transactionjust accepted. The contents of the box indicate what ordering relationship the secondtransaction must have to the first.

PMW - Posted Memory Write is a transaction that has completed on the originating busbefore completing on the destination bus and can only occur for Memory Write andMemory Write and Invalidate commands.

DRR - Delayed Read Request is a transaction that must complete on the destination busbefore completing on the originating bus and can be an I/O Read, Configuration Read,Memory Read, Memory Read Line, or Memory Read Multiple commands. Asmentioned earlier, once a request has been attempted on the destination bus, it mustcontinue to be repeated until it completes on the destination bus. Before it is attempted

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on the destination bus the DRR is only a request and may be discarded at any time toprevent deadlock or improve performance, since the master must repeat the request later.

DWR - Delayed Write Request is a transaction that must complete on the destination busbefore completing on the originating bus and can be an I/O Write or Configuration Writecommand. Note: Memory Write and Memory Write and Invalidate commands must beposted (PMW) and not be completed as DWR. As mentioned earlier, once a request hasbeen attempted on the destination bus, it must continue to be repeated until it completes.Before it is attempted on the destination bus, the DWR is only a request and may bediscarded at any time to prevent deadlock or improve performance, since the mastermust repeat the request later.

DRC - Delayed Read Completion is a transaction that has completed on the destinationbus and is now moving toward the originating bus to complete. The DRC contains thedata requested by the master and the status of the target (normal, Master-Abort, Target-Abort, parity error, etc.).

DWC - Delayed Write Completion is a transaction that has completed on the destinationbus and is now moving toward the originating bus. The DWC does not contain the dataof the access, but only status of how it completed (Normal, Master-Abort, Target-Abort,parity error, etc.). The write data has been written to the specified target.

No - indicates that the subsequent transaction is not allowed to complete before theprevious transaction to preserve ordering in the system. The four No boxes found incolumn 2 prevent PMW data from being passed by other accesses and thereby maintain aconsistent view of data in the system.

Yes - indicates that the subsequent transaction must be allowed to complete before theprevious one or a deadlock can occur.

When blocking occurs, the PMW is required to pass the Delayed Transaction. If themaster continues attempting to complete Delayed Requests, it must be fair in attemptingto complete the PMW. There is no ordering violation when these subsequenttransactions complete before a prior transaction.

Yes/No - indicates that the bridge designer may choose to allow the subsequenttransaction to complete before the previous transaction or not. This is allowed since thereare no ordering requirements to meet or deadlocks to avoid. How a bridge designerchooses to implement these boxes may have a cost impact on the bridge implementationor performance impact on the system.

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Table E-1: Ordering Rules for a Bridge

Row pass Col.?PMW(Col 2)

DRR(Col 3)

DWR(Col 4)

DRC(Col 5)

DWC(Col 6)

PMW (Row 1) No1 Yes5 Yes5 Yes7 Yes7

DRR (Row 2) No2 Yes/No Yes/No Yes/No Yes/No

DWR (Row 3) No3 Yes/No Yes/No Yes/No Yes/No

DRC (Row 4) No4 Yes6 Yes6 Yes/No Yes/No

DWC (Row 5) Yes/No Yes6 Yes6 Yes/No Yes/No

Rule 1 - A subsequent PMW cannot pass a previously accepted PMW.(Col 2, Row 1)

Posted Memory write transactions must complete in the order they arereceived. If the subsequent write is to the flag that covers the data, theConsumer may use stale data if write transactions are allowed to pass eachother.

Rule 2 - A read transaction must push posted write data to maintain ordering.(Col 2, Row 2)

For example, a memory write to a location followed by an immediatememory read of the same location returns the new value (refer toSection 3.10, item 6, for possible exceptions). Therefore, a memory readcannot pass posted write data. An I/O read cannot pass a PMW, because theread may be ensuring the write data arrives at the final destination.

Rule 3 - A non-postable write transaction must push posted write data to maintainordering. (Col 2, Row 3)

A Delayed Write Request may be the flag that covers the data previouslywritten (PMW), and, therefore, the write flag cannot pass the data that itpotentially covers.

Rule 4 - A read transaction must pull write data back to the originating bus of theread transaction. (Col 2, Row 4)

For example, the read of a status register of the device writing data tomemory must not complete before the data is pulled back to the originatingbus; otherwise, stale data may be used.

Rule 5 - A Posted Memory Write must be allowed to pass a Delayed Request (reador write) to avoid deadlocks. (Col 3 and Col 4, Row 1)

A deadlock can occur when bridges that support Delayed Transactions areused with bridges that do not support Delayed Transactions. Referring toFigure E-2, a deadlock can occur when Bridge Y (using DelayedTransactions) is between Bridges X and Z (designed to a previous version ofthis specification and not using Delayed Transactions). Master 1 initiates aread to Target 1 that is forwarded through Bridge X and is queued as aDelayed Request in Bridge Y. Master 3 initiates a read to Target 3 that isforwarded through Bridge Z and is queued as a Delayed Request in Bridge

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Y. After Masters 1 and 3 are terminated with Retry, Masters 2 and 4 beginmemory write transactions of a long duration addressing Targets 2 and 4respectively, which are posted in the write buffers of Bridges X and Zrespectively. When Bridge Y attempts to complete the read in eitherdirection, Bridges X and Z must flush their posted write buffers beforeallowing the Read Request to pass through it.

If the posted write buffers of Bridges X and Z are larger than those of BridgeY, Bridge Y’s buffers will fill. If posted write data is not allowed to pass theDRR, the system will deadlock. Bridge Y cannot discard the read requestsince it has been attempted, and it cannot accept any more write data untilthe read in the opposite direction is completed. Since this condition exists inboth directions, neither DRR can complete because the other is blocking thepath. Therefore, the PMW data is required to pass the DRR when the DRRblocks forward progress of PMW data.

The same condition exists when a DWR sits at the head of both queues,since some old bridges also require the posting buffers to be flushed on anon-posted write cycle.

Rule 6 – A Delayed Completion (read or write) must be allowed to pass a DelayedRequest (read or write) to avoid deadlocks. (Cols 3 and 4, Rows 4 and 5)

A deadlock can occur when two bridges that support Delayed Transactionsare requesting accesses to each other. The common PCI bus segment is onthe secondary bus of Bridge A and the primary bus for Bridge B. If neitherbridge allows Delayed Completions to pass the Delayed Requests, neithercan make progress.

For example, suppose Bridge A’s request to Bridge B completes on BridgeB’s secondary bus, and Bridge B’s request completes on Bridge A’s primarybus. Bridge A’s completion is now behind Bridge B’s request and BridgeB’s completion is behind Bridge A’s request. If neither bridge allowscompletions to pass the requests, then a deadlock occurs because neithermaster can make progress.

Rule 7 - A Posted Memory Write must be allowed to pass a Delayed Completion(read or write) to avoid deadlocks. (Col 5 and Col 6, Row 1)

As in the example for Rule 5, another deadlock can occur in the systemconfiguration in Figure E-2. In this case, however, a DRC sits at the head ofthe queues in both directions of Bridge Y at the same time. Again the oldbridges (X and Z) contain posted write data from another master. Theproblem in this case, however, is that the read transaction cannot be repeateduntil all the posted write data is flushed out of the old bridge and the masteris allowed to repeat its original request. Eventually, the new bridge cannotaccept any more posted data because its internal buffers are full and itcannot drain them until the DRC at the other end completes. When thiscondition exists in both directions, neither DRC can complete because theother is blocking the path. Therefore, the PMW data is required to pass theDRC when the DRC blocks forward progress of PMW data.

The same condition exists when a DWC sits at the head of both queues.

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Transactions that have no ordering constraints

Some transactions enqueued as Delayed Requests or Delayed Completions have noordering relationship with any other Delayed Requests or Delayed Completions. Thedesigner can (for performance or cost reasons) allow or disallow Delayed Requests topass other Delayed Requests and Delayed Completions that were previously enqueued.

Delayed Requests can pass other Delayed Requests (Cols 3 and 4, Rows 2 and 3).

Since Delayed Requests have no ordering relationship with other DelayedRequests, these four boxes are don’t cares.

Delayed Requests can pass Delayed Completions (Col 5 and 6, Rows 2 and 3).

Since Delayed Requests have no ordering relationship with DelayedCompletions, these four boxes are don’t cares.

Delayed Completions can pass other Delayed Completions (Col 5 and 6, Rows 4 and5).

Since Delayed Completions have no ordering relationship with other DelayedCompletions, these four boxes are don’t cares.

Delayed Write Completions can pass posted memory writes or be blocked by them(Col 2, Row 5).

If the DWC is allowed to pass a PMW or if it remains in the same order,there is no deadlock or data inconsistencies in either case. The DWC dataand the PMW data are moving in opposite directions, initiated by mastersresiding on different buses accessing targets on different buses.

PCI-PCIBridge Y

(pre 2.1)

Master 2

PCI Bus N

PCI-PCIBridge X

Master 1 Target 3

(Rev. 2.1)

Master 3

PCI Bus P

PCI-PCIBridge Z

Master 4Target 2

(pre 2.1)

Target 1

Target 4

Figure E-2: Example System with PCI-to-PCI Bridges

E.5. Delayed Transactions and LOCK#

The bridge is required to support LOCK# when a transaction is initiated on its primarybus (and is using the lock protocol), but is not required to support LOCK# ontransactions that are initiated on its secondary bus. If a locked transaction is initiated onthe primary bus and the bridge is the target, the bridge must adhere to the lock semantics

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defined by this specification. The bridge is required to complete (push) all PMWs(accepted from the primary bus) onto the secondary bus before attempting the lock onthe secondary bus. The bridge may discard any requests enqueued, allow the lockedtransaction to pass the enqueued requests, or simply complete all enqueued transactionsbefore attempting the locked transaction on the secondary interface. Once a lockedtransaction has been enqueued by the bridge, the bridge cannot accept any othertransaction from the primary interface until the lock has completed except for acontinuation of the lock itself by the lock master. Until the lock is established on thesecondary interface, the bridge is allowed to continue enqueuing transactions from thesecondary interface, but not the primary interface. Once lock has been established on thesecondary interface, the bridge cannot accept any posted write data moving toward theprimary interface until LOCK# has been released (FRAME# and LOCK# deasserted onthe same rising clock edge). (In the simplest implementation, the bridge does not acceptany other transactions in either direction once lock is established on the secondary bus,except for locked transactions from the lock master.) The bridge must complete PMW,DRC, and DWC transactions moving toward the primary bus before allowing the lockedaccess to complete on the originating bus. The preceding rules are sufficient fordeadlock free operation. However, an implementation may be more or less restrictive,but, in all cases must ensure deadlock-free operation.

E.6. Error Conditions

A bridge is free to discard data or status of a transaction that was completed usingDelayed Transaction termination when the master has not repeated the request within 2 10

PCI clocks (about 30 µs at 33 MHz). However, it is recommended that the bridge notdiscard the transaction until 215 PCI clocks (about 983 µs at 33 MHz) after it acquiredthe data or status. The shorter number is useful in a system where a master designed to aprevious version of this specification frequently fails to repeat a transaction exactly asfirst requested. In this case, the bridge may be programmed to discard the abandonedDelayed Completion early and allow other transactions to proceed. Normally, however,the bridge would wait the longer time, in case the repeat of the transaction is beingdelayed by another bridge or bridges designed to a previous version of this specificationthat did not support Delayed Transactions.

When this timer (referred to as the Discard Timer) expires, the device is required todiscard the data; otherwise, a deadlock may occur.

Note: When the transaction is discarded, data may be destroyed. Thisoccurs when the discarded Delayed Completion is a read to a non-prefetchable region.

When the Discard Timer expires, the device may choose to report or ignore the error.When the data is prefetchable, it is recommended that the device ignore the error sincesystem integrity is not affected. However, when the data is not prefetchable, it isrecommended that the device report the error to its device driver since system integrity isaffected. A bridge may assert SERR# since it typically does not have a device driver.

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Appendix FExclusive Accesses

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57 In previous versions of this specification, a minimum of 16 bytes (naturally aligned) was considered thelock resource. A device was permitted to lock its entire memory address space. This definition still appliesfor an upstream locked access to main memory. For downstream locked access, a resource is the PCI-to-PCI bridge or the Expansion Bus bridge that is addressed by the locked operation.

58 For a SAC, this is the clock after the address phase. For a DAC, this occurs the clock after the firstaddress phase.

59 Once lock has been established, the master retains ownership of LOCK# when terminated with Retry orDisconnect.

60 Consecutive refers to back-to-back locked operations and not a continuation of the current lockedoperation.

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F.2. Starting an Exclusive Access

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61 A locked operation is established when LOCK# is deasserted during the address phase, asserted thefollowing clock, and data is transferred during the current transaction.

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Figure F-1: Starting an Exclusive Access

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F.3. Continuing an Exclusive Access

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F.5. Completing an Exclusive Access

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F.7. Complete Bus Lock

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Appendix GI/O Space Address

Decoding for Legacy Devices

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Appendix HCapability IDs

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ID Capability

0 Reserved

1 PCI Power Management Interface – This capability structure provides astandard interface to control power management features in a PCIdevice. It is fully documented in the PCI Power Management InterfaceSpecification. This document is available from the PCI SIG asdescribed in Chapter 1 of this specification.

2 AGP – This capability structure identifies a controller that is capable ofusing Accelerated Graphics Port features. Full documentation can befound in the Accelerated Graphics Port Interface Specification. This isavailable at http://www.agpforum.org.

3 VPD – This capability structure identifies a device that supports VitalProduct Data. Full documentation of this feature can be found inSection 6.4. and Appendix I of this specification.

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ID Capability

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5 Message Signaled Interrupts – This capability VWUXFWXUHidentifies a PCIfunction that can do message signaled interrupt delivery as defined inSection 6.8. of this specification.

6 CompactPCI Hot Swap – This capability VWUXFWXUHprovides a standardinterface to control and sense status within a device that supports HotSwap insertion and extraction in a CompactPCI system. This capabilityis documented in the CompactPCI Hot Swap Specification PICMG 2.1,R1.0 available at http://www.picmg.org.

7-255 Reserved

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Appendix IVital Product Data

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F VPD Address Pointer to Next ID ID = 03h

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Offset Field Name

Byte 0 Value = 0xxxxyyyb (Type = Small(0), Small Item Name = xxxx,length = yy bytes

Bytes 1 to n Actual information

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Offset Field Name

Byte 0 Value = 1xxxxxxxB (Type = Large(1), Large item name =xxxxxxx)

Byte 1 Length of data items bits[7:0] (lsb)

Byte 2 Length of data items bits[15:8] (msb)

Byte 3 to n Actual data items

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TAG Identifier String

TAG VPD-R list containing one or more VPDkeywords

TAG VPD-W list containing one or more VPDkeywords

TAG End Tag

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I.1. VPD Format,QIRUPDWLRQILHOGVZLWKLQD93'UHVRXUFHW\SHFRQVLVWRIDWKUHHE\WHKHDGHUIROORZHGE\VRPHDPRXQWRIGDWDVHH)LJXUH,7KHWKUHHE\WHKHDGHUFRQWDLQVDWZRE\WHNH\ZRUGDQGDRQHE\WHOHQJWK

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Keyword Length Data

Byte 0 Byte 1 Byte 2 Bytes 3 through n

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I.3.1. VPD Large and Small Resource Data Tags

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Large resource type IdentifierString Tag(0x2)

This tag is the first item in the VPD storagecomponent. It contains the name of the board inalphanumeric characters.

Large resource type VPD-RTag(0x10)

This tag contains the read only VPD keywords for aboard.

Large resource type VPD-WTag(0x11)

This tag contains the read/write VPD keywords forthe board.

Small resource type End Tag(0xF)

This tag identifies the end of VPD in the storagecomponent.

I.3.1.1. Read-Only Fields

PN Board Part Number This keyword is provided as an extension to theDevice ID (or Subsystem ID) in the ConfigurationSpace header in Figure 6-1.

EC EC Level of the Board The characters are alphanumeric and represent theengineering change level for this board.

MN Manufacture ID This keyword is provided as an extension to theVendor ID (or Subsystem Vendor ID) in theConfiguration Space header in Figure 6-1. Thisallows vendors the flexibility to identify anadditional level of detail pertaining to the sourcing ofthis device.

SN Serial Number The characters are alphanumeric and represent theunique board Serial Number.

Vx Vendor Specific This is a vendor specific item and the characters arealphanumeric. The second character (x) of thekeyword can be 0 through Z.

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CP Extended Capability This field allows a new capability to be identified inthe VPD area. Since dynamic control/status cannotbe placed in VPD, the data for this field identifieswhere, in the device’s memory or I/O address space,the control/status registers for the capability can befound. Location of the control/status registers isidentified by providing the index (a value between 0and 5) of the Base Address register that defines theaddress range that contains the registers, and theoffset within that Base Address register range wherethe control/status registers reside. The data area forthis field is four bytes long. The first byte containsthe ID of the extended capability. The second bytecontains the index (zero based) of the Base Addressregister used. The next two bytes contain the offset(in little endian order) within that address rangewhere the control/status registers defined for thatcapability reside.

RV Checksum andReserved

The first byte of this item is a checksum byte. Thechecksum is correct if the sum of all bytes in VPD(from VPD address 0 up to and including this byte)is zero. The remainder of this item is reserved space(as needed) to identify the last byte of read-onlyspace. The read-write area does not have achecksum. This field is required.

I.3.1.2 Read/Write Fields

Vx Vendor Specific This is a vendor specific item and the charactersare alphanumeric. The second character (x) ofthe keyword can be 0 through Z.

Yx System Specific This is a system specific item and the charactersare alphanumeric. The second character (x) ofthe keyword can be 0 through 9 and B throughZ.

YA Asset Tag Identifier This is a system specific item and the charactersare alphanumeric. This keyword contains thesystem asset identifier provided by the systemowner.

RW Remaining Read/WriteArea

This descriptor is used to identify the unusedportion of the read/write space. The productvendor initializes this parameter based on thesize of the read/write space or the spaceremaining following the Vx VPD items. One ormore of the Vx, Yx, and RW items are required.

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I.3.2. VPD Example

The following is an example of a typical VPD.

Offset Item Value

0 Large Resource Type ID String Tag(0x02)

0x82 “Product Name”

1 Length 0x0021

3 Data “ABCD Super-FastWidget Controller”

36 Large Resource Type VPD-R Tag (0x10) 0x90

37 Length 0x0059

39 VPD Keyword “PN”

41 Length 0x08

42 Data “6181682A”

50 VPD Keyword “EC”

52 Length 0x0A

53 Data “4950262536”

63 VPD Keyword “SN”

65 Length 0x08

66 Data “00000194”

74 VPD Keyword “MN”

76 Length 0x04

77 Data “1037”

81 VPD Keyword “RV”

83 Length 0x2C

84 Data Checksum

85 Data Reserved (0x00)

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Offset Item Value

128 Large Resource Type VPD-W Tag (0x11) 0x91

129 Length 0x007E

131 VPD Keyword “V1”

133 Length 0x05

134 Data “65A01”

139 VPD Keyword “Y1”

141 Length 0x0D

142 Data “Error Code 26”

155 VPD Keyword “RW”

157 Length 0x61

158 Data Reserved (0x00)

255 Small Resource Type End Tag (0xF) 0x78

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Glossary

64-bit extension A group of PCI signals that support a 64-bit data path.

Address Spaces A reference to the three separate physical addressregions of PCI: Memory, I/O, and Configuration.

agent An entity that operates on a computer bus.

arbitration latency The time that the master waits after having assertedREQ# until it receives GNT#, and the bus returns tothe idle state after the previous master’s transaction.

backplate The metal plate used to fasten an expansion board tothe system chassis.

BIST register An optional register in the header region used forcontrol and status of built-in self tests.

bridge The logic that connects one computer bus to another,allowing an agent on one bus to access an agent onthe other.

burst transfer The basic bus transfer mechanism of PCI. A burst iscomprised of an address phase and one or more dataphases.

bus commands Signals used to indicate to a target the type oftransaction the master is requesting.

bus device A bus device can be either a bus master or target:

• master -- drives the address phase and transactionboundary (FRAME#). The master initiates atransaction and drives data handshaking (IRDY#)with the target.

• target -- claims the transaction by assertingDEVSEL# and handshakes the transaction(TRDY#) with the initiator.

catastrophic error An error that affects the integrity of system operationsuch as a detected address parity error or an invalidPWR_GOOD signal.

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central resources Bus support functions supplied by the host system,typically in a PCI compliant bridge or standardchipset.

command See bus command.

Configuration Address Space A set of 64 registers (DWORDs) used forconfiguration, initialization, and catastrophic errorhandling. This address space consists of two regions:a header region and a device-dependent region.

configuration transaction Bus transaction used for system initialization andconfiguration via the configuration address space.

DAC Dual address cycle. A PCI transaction where a 64-bitaddress is transferred across a 32-bit data path in twoclock cycles. See also SAC.

deadlock When two devices (one a master, the other a target)require the other device to respond first during asingle bus transaction. For example, a masterrequires the addressed target to assert TRDY# on awrite transaction before the master will assert IRDY#.(This behavior is a violation of this specification.)

Delayed Transaction The process of a target latching a request andcompleting it after the master was terminated withRetry.

device See PCI device.

device dependent region The last 48 DWORDS of the PCI configuration space.The contents of this region are not described in thisdocument.

Discard Timer When this timer expires, a device is permitted todiscard unclaimed Delayed Completions (refer toSection 3.3.3.3.3. and Appendix E).

DWORD A 32-bit block of data.

EISA Extended Industry Standard Architecture expansionbus, based on the IBM PC AT bus, but extended to 32bits of address and data.

expansion board A circuit board that plugs into a motherboard andprovides added functionality.

expansion bus bridge A bridge that has PCI as its primary interface andISA, EISA, or Micro Channel as its secondaryinterface. This specification does not preclude the useof bridges to other buses, although deadlock and othersystem issues for those buses have not beenconsidered.

Function A set of logic that is represented by a singleConfiguration Space.

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header region The first 16 DWORDS of a device’s ConfigurationSpace. The header region consists of fields thatuniquely identify a PCI device and allow the device tobe generically controlled.See also device dependent region.

hidden arbitration Arbitration that occurs during a previous access sothat no PCI bus cycles are consumed by arbitration,except when the bus is idle.

host bus bridge A low latency path through which the processor maydirectly access PCI devices mapped anywhere in thememory, I/O, or configuration address spaces.

Idle state Any clock period that the bus is idle (FRAME# andIRDY# deasserted).

Initialization Time The period of time that begins when RST# isdeasserted and completes 225 PCI clocks later.

ISA Industry Standard Architecture expansion bus builtinto the IBM PC AT computer.

keepers Pullup resistors or active components that are onlyused to sustain a signal state.

latency See arbitration latency, master data latency, targetinitial latency, and target subsequent latency.

Latency Timer A mechanism for ensuring that a bus master does notextend the access latency of other masters beyond aspecified value.

master An agent that initiates a bus transaction.

Master-Abort A termination mechanism that allows a master toterminate a transaction when no target responds.

master data latency The number of PCI clocks until IRDY# is assertedfrom FRAME# being asserted for the first data phaseor from the end of the previous data phase.

MC The Micro Channel architecture expansion bus asdefined by IBM for its PS/2 line of personalcomputers.

motherboard A circuit board containing the basic functions (e.g.,CPU, memory, I/O, and expansion connectors) of acomputer.

multi-function device A device that implements from two to eight functions.Each function has its own Configuration Space that isaddressed by a different encoding of AD[10::08]during the address phase of a configurationtransaction.

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multi-master device A single-function device that contains more than onesource of bus master activity. For example, a devicethat has a receiver and transmitter that operateindependently.

NMI Non-maskable interrupt.

operation A logical sequence of transactions, e.g., Lock.

output driver An electrical drive element (transistor) for a singlesignal on a PCI device.

PCI connector An expansion connector that conforms to theelectrical and mechanical requirements of the PCIlocal bus standard.

PCI device A device that (electrical component) conforms to thePCI specification for operation in a PCI local busenvironment.

PGA Pin grid array component package.

phase One or more clocks in which a single unit ofinformation is transferred, consisting of:

• an address phase (a single address transfer in oneclock for a single address cycle and two clocksfor a dual address cycle)

• a data phase (one transfer state plus zero or morewait states)

positive decoding A method of address decoding in which a deviceresponds to accesses only within an assigned addressrange. See also subtractive decoding.

POST Power-on self test. A series of diagnostic routinesperformed when a system is powered up.

pullups Resistors used to insure that signals maintain stablevalues when no agent is actively driving the bus.

run time The time that follows Initialization Time.

SAC Single address cycle. A PCI transaction where a32-bit address is transferred across a 32-bit data pathin a single clock cycle. See also DAC.

shared slot An arrangement on a PCI motherboard that allows aPCI connector to share the system bus slot nearest thePCI bus layout with an ISA, EISA, or MC busconnector. In an MC system, for example, the sharedslot can accommodate either an MC expansion boardor a PCI expansion board.

single-function device A device that contains only one function.

sideband signals Any signal not part of the PCI specification thatconnects two or more PCI-compliant agents and hasmeaning only to those agents.

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Special Cycle A message broadcast mechanism used forcommunicating processor status and/or (optionally)logical sideband signaling between PCI agents.

stale data Data in a cache-based system that is no longer validand, therefore, must be discarded.

stepping The ability of an agent to spread assertion of qualifiedsignals over several clocks.

subtractive decoding A method of address decoding in which a deviceaccepts all accesses not positively decoded by anotheragent. See also positive decoding.

target An agent that responds (with a positiveacknowledgment by asserting DEVSEL#) to a bustransaction initiated by a master.

Target-Abort A termination mechanism that allows a target toterminate a transaction in which a fatal error hasoccurred, or to which the target will never be able torespond.

target initial latency The number of PCI clocks that the target takes toassert TRDY# for the first data transfer.

target subsequent latency The number of PCI clocks that the target takes toassert TRDY# from the end of the previous dataphase of a burst.

termination A transaction termination brings bus transactions toan orderly and systematic conclusion. Alltransactions are concluded when FRAME# andIRDY# are deasserted (an idle cycle). Terminationmay be initiated by the master or the target.

transaction An address phase plus one or more data phases.

turnaround cycle A bus cycle used to prevent contention when oneagent stops driving a signal and another agent beginsdriving it. A turnaround cycle must last one clockand is required on all signals that may be driven bymore than one agent.

wait state A bus clock in which no transfer occurs.

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